src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18#define SLICE_CYCLES 2048
19
20mLOG_DEFINE_CATEGORY(DS, "DS");
21
22const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
23const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
24const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
25
26static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
27static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
28
29enum {
30 DS7_SP_BASE = 0x380FD80,
31 DS7_SP_BASE_IRQ = 0x380FF80,
32 DS7_SP_BASE_SVC = 0x380FFC0,
33
34 DS9_SP_BASE = 0x3002F7C,
35 DS9_SP_BASE_IRQ = 0x3003F80,
36 DS9_SP_BASE_SVC = 0x3003FC0,
37};
38
39static void DSInit(void* cpu, struct mCPUComponent* component);
40
41static void DS7Reset(struct ARMCore* cpu);
42static void DS7TestIRQ(struct ARMCore* cpu);
43static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44static void DS7ProcessEvents(struct ARMCore* cpu);
45
46static void DS9Reset(struct ARMCore* cpu);
47static void DS9TestIRQ(struct ARMCore* cpu);
48static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
49static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
50static void DS9ProcessEvents(struct ARMCore* cpu);
51
52static void DSProcessEvents(struct DSCommon* dscore);
53static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
54static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
55static void DSBreakpoint(struct ARMCore* cpu, int immediate);
56
57static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
58 UNUSED(cyclesLate);
59 struct DS* ds = context;
60 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
61 if (ds->activeCpu == ds->ds9.cpu) {
62 ds->activeCpu = ds->ds7.cpu;
63 ds->cycleDrift += cycles;
64 cycles = ds->cycleDrift >> 1;
65 timing = &ds->ds7.timing;
66 } else {
67 ds->activeCpu = ds->ds9.cpu;
68 ds->cycleDrift -= cycles << 1;
69 cycles = ds->cycleDrift + SLICE_CYCLES;
70 timing = &ds->ds9.timing;
71 }
72 mTimingSchedule(timing, &ds->slice, cycles);
73 ds->sliceStart = mTimingCurrentTime(timing);
74}
75
76void DSCreate(struct DS* ds) {
77 ds->d.id = DS_COMPONENT_MAGIC;
78 ds->d.init = DSInit;
79 ds->d.deinit = NULL;
80 ds->ds7.p = ds;
81 ds->ds9.p = ds;
82 ds->ds7.cpu = NULL;
83 ds->ds9.cpu = NULL;
84 ds->ds7.ipc = &ds->ds9;
85 ds->ds9.ipc = &ds->ds7;
86}
87
88static void DSInit(void* cpu, struct mCPUComponent* component) {
89 struct DS* ds = (struct DS*) component;
90 struct ARMCore* core = cpu;
91 if (!ds->ds7.cpu) {
92 // The ARM7 must get initialized first
93 ds->ds7.cpu = core;
94 ds->debugger = 0;
95 ds->sync = 0;
96 return;
97 }
98 ds->ds9.cpu = cpu;
99 ds->activeCpu = NULL;
100
101 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
102
103 ds->slice.name = "DS CPU Time Slicing";
104 ds->slice.callback = _slice;
105 ds->slice.context = ds;
106 ds->slice.priority = UINT_MAX;
107
108 CircleBufferInit(&ds->ds7.fifo, 64);
109 CircleBufferInit(&ds->ds9.fifo, 64);
110
111 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
112 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
113 DSMemoryInit(ds);
114
115 ds->video.p = ds;
116
117 ds->ds7.springIRQ = 0;
118 ds->ds9.springIRQ = 0;
119 DSTimerInit(ds);
120 ds->keySource = NULL;
121 ds->rtcSource = NULL;
122 ds->rumble = NULL;
123
124 ds->romVf = NULL;
125
126 ds->keyCallback = NULL;
127
128 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
129 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
130}
131
132void DSUnloadROM(struct DS* ds) {
133 if (ds->romVf) {
134 ds->romVf->close(ds->romVf);
135 ds->romVf = NULL;
136 }
137}
138
139void DSDestroy(struct DS* ds) {
140 CircleBufferDeinit(&ds->ds7.fifo);
141 CircleBufferDeinit(&ds->ds9.fifo);
142 DSUnloadROM(ds);
143 DSMemoryDeinit(ds);
144 mTimingDeinit(&ds->ds7.timing);
145 mTimingDeinit(&ds->ds9.timing);
146}
147
148void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
149 irqh->reset = DS7Reset;
150 irqh->processEvents = DS7ProcessEvents;
151 irqh->swi16 = DS7Swi16;
152 irqh->swi32 = DS7Swi32;
153 irqh->hitIllegal = DSIllegal;
154 irqh->readCPSR = DS7TestIRQ;
155 irqh->writeCP15 = NULL;
156 irqh->hitStub = DSHitStub;
157 irqh->bkpt16 = DSBreakpoint;
158 irqh->bkpt32 = DSBreakpoint;
159}
160
161void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
162 irqh->reset = DS9Reset;
163 irqh->processEvents = DS9ProcessEvents;
164 irqh->swi16 = NULL;
165 irqh->swi32 = NULL;
166 irqh->hitIllegal = DSIllegal;
167 irqh->readCPSR = DS9TestIRQ;
168 irqh->writeCP15 = DS9WriteCP15;
169 irqh->hitStub = DSHitStub;
170 irqh->bkpt16 = DSBreakpoint;
171 irqh->bkpt32 = DSBreakpoint;
172}
173
174void DS7Reset(struct ARMCore* cpu) {
175 ARMSetPrivilegeMode(cpu, MODE_IRQ);
176 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
177 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
178 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
179 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
180 cpu->gprs[ARM_SP] = DS7_SP_BASE;
181
182 struct DS* ds = (struct DS*) cpu->master;
183 mTimingClear(&ds->ds7.timing);
184 CircleBufferInit(&ds->ds7.fifo, 64);
185 DSMemoryReset(ds);
186 DS7IOInit(ds);
187
188 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
189 if (header) {
190 // TODO: Error check
191 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
192 uint32_t base = header->arm7Base - DS_BASE_RAM;
193 uint32_t* basePointer = &ds->memory.ram[base >> 2];
194 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
195 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
196 }
197 cpu->gprs[12] = header->arm7Entry;
198 cpu->gprs[ARM_LR] = header->arm7Entry;
199 cpu->gprs[ARM_PC] = header->arm7Entry;
200 int currentCycles = 0;
201 ARM_WRITE_PC;
202
203 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
204 }
205}
206
207void DS9Reset(struct ARMCore* cpu) {
208 ARMSetPrivilegeMode(cpu, MODE_IRQ);
209 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
210 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
211 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
212 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
213 cpu->gprs[ARM_SP] = DS9_SP_BASE;
214
215 struct DS* ds = (struct DS*) cpu->master;
216 mTimingClear(&ds->ds9.timing);
217 CircleBufferInit(&ds->ds9.fifo, 64);
218 DS9IOInit(ds);
219
220 ds->activeCpu = cpu;
221 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
222 ds->cycleDrift = 0;
223 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
224
225 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
226 if (header) {
227 // TODO: Error check
228 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
229 uint32_t base = header->arm9Base - DS_BASE_RAM;
230 uint32_t* basePointer = &ds->memory.ram[base >> 2];
231 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
232 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
233 }
234 cpu->gprs[12] = header->arm9Entry;
235 cpu->gprs[ARM_LR] = header->arm9Entry;
236 cpu->gprs[ARM_PC] = header->arm9Entry;
237 int currentCycles = 0;
238 ARM_WRITE_PC;
239
240 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
241 }
242}
243
244static void DS7ProcessEvents(struct ARMCore* cpu) {
245 struct DS* ds = (struct DS*) cpu->master;
246 DSProcessEvents(&ds->ds7);
247}
248
249static void DS9ProcessEvents(struct ARMCore* cpu) {
250 struct DS* ds = (struct DS*) cpu->master;
251 DSProcessEvents(&ds->ds9);
252}
253
254static void DSProcessEvents(struct DSCommon* dscore) {
255 struct ARMCore* cpu = dscore->cpu;
256 struct DS* ds = dscore->p;
257 if (dscore->springIRQ && !cpu->cpsr.i) {
258 ARMRaiseIRQ(cpu);
259 dscore->springIRQ = 0;
260 }
261
262 int32_t nextEvent = cpu->nextEvent;
263 while (cpu->cycles >= nextEvent) {
264 int32_t cycles = cpu->cycles;
265
266 cpu->cycles = 0;
267 cpu->nextEvent = INT_MAX;
268
269#ifndef NDEBUG
270 if (cycles < 0) {
271 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
272 }
273#endif
274 nextEvent = cycles;
275 do {
276 nextEvent = mTimingTick(&dscore->timing, nextEvent);
277 } while (ds->cpuBlocked);
278
279 cpu->nextEvent = nextEvent;
280
281 if (ds->earlyExit) {
282 ds->earlyExit = false;
283 break;
284 }
285 if (cpu->halted) {
286 cpu->cycles = nextEvent;
287 }
288#ifndef NDEBUG
289 else if (nextEvent < 0) {
290 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
291 }
292#endif
293 }
294}
295
296void DSRunLoop(struct DS* ds) {
297 if (ds->activeCpu == ds->ds9.cpu) {
298 ARMv5RunLoop(ds->ds9.cpu);
299 } else {
300 ARMv4RunLoop(ds->ds7.cpu);
301 }
302}
303
304void DS7Step(struct DS* ds) {
305 while (ds->activeCpu == ds->ds9.cpu) {
306 ARMv5RunLoop(ds->ds9.cpu);
307 }
308 ARMv4Run(ds->ds7.cpu);
309}
310
311void DS9Step(struct DS* ds) {
312 while (ds->activeCpu == ds->ds7.cpu) {
313 ARMv4RunLoop(ds->ds7.cpu);
314 }
315 ARMv5Run(ds->ds9.cpu);
316}
317
318void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
319 ds->debugger = (struct ARMDebugger*) debugger->platform;
320 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
321 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
322 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
323 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
324}
325
326void DSDetachDebugger(struct DS* ds) {
327 ds->debugger = NULL;
328 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
329 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
330 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
331 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
332}
333
334bool DSLoadROM(struct DS* ds, struct VFile* vf) {
335 DSUnloadROM(ds);
336 ds->romVf = vf;
337 // TODO: error check
338 return true;
339}
340
341bool DSIsROM(struct VFile* vf) {
342 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
343 return false;
344 }
345 uint8_t signature[sizeof(DS_ROM_MAGIC)];
346 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
347 return false;
348 }
349 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
350}
351
352bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
353 size_t size = vf->size(vf);
354 void* data = NULL;
355 uint32_t crc;
356 if (size == DS7_SIZE_BIOS) {
357 data = vf->map(vf, size, MAP_READ);
358 } else if (size == 0x1000) {
359 data = vf->map(vf, size, MAP_READ);
360 }
361 if (!data) {
362 return false;
363 }
364 crc = doCrc32(data, size);
365 if (crc == DS7_BIOS_CHECKSUM) {
366 ds->bios7Vf = vf;
367 ds->memory.bios7 = data;
368 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
369 } else if (crc == DS9_BIOS_CHECKSUM) {
370 ds->bios9Vf = vf;
371 ds->memory.bios9 = data;
372 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
373 } else {
374 mLOG(DS, WARN, "BIOS checksum incorrect");
375 vf->unmap(vf, data, size);
376 return false;
377 }
378 return true;
379}
380
381void DSGetGameCode(struct DS* ds, char* out) {
382 memset(out, 0, 8);
383 if (!ds->romVf) {
384 return;
385 }
386
387 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
388 memcpy(out, "NTR-", 4);
389 memcpy(&out[4], &cart->id, 4);
390 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
391}
392
393void DSGetGameTitle(struct DS* ds, char* out) {
394 memset(out, 0, 12);
395 if (!ds->romVf) {
396 return;
397 }
398
399 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
400 memcpy(out, &cart->title, 4);
401 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
402}
403
404void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
405 struct DS* ds = (struct DS*) cpu->master;
406 if (ds->debugger) {
407 struct mDebuggerEntryInfo info = {
408 .address = _ARMPCAddress(cpu),
409 .opcode = opcode
410 };
411 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
412 }
413 // TODO: More sensible category?
414 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
415}
416
417void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
418 struct DS* ds = (struct DS*) cpu->master;
419 if (ds->debugger) {
420 struct mDebuggerEntryInfo info = {
421 .address = _ARMPCAddress(cpu),
422 .opcode = opcode
423 };
424 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
425 } else {
426 ARMRaiseUndefined(cpu);
427 }
428}
429
430void DSBreakpoint(struct ARMCore* cpu, int immediate) {
431 struct DS* ds = (struct DS*) cpu->master;
432 if (immediate >= CPU_COMPONENT_MAX) {
433 return;
434 }
435 switch (immediate) {
436 case CPU_COMPONENT_DEBUGGER:
437 if (ds->debugger) {
438 struct mDebuggerEntryInfo info = {
439 .address = _ARMPCAddress(cpu)
440 };
441 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
442 }
443 break;
444 default:
445 break;
446 }
447}
448
449void DS7TestIRQ(struct ARMCore* cpu) {
450 struct DS* ds = (struct DS*) cpu->master;
451 if (0) {
452 ds->ds7.springIRQ = 1;
453 cpu->nextEvent = cpu->cycles;
454 }
455}
456
457void DS9TestIRQ(struct ARMCore* cpu) {
458 struct DS* ds = (struct DS*) cpu->master;
459 if (0) {
460 ds->ds9.springIRQ = 1;
461 cpu->nextEvent = cpu->cycles;
462 }
463}
464
465static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
466 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
467}
468
469static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
470 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
471 switch (opcode2) {
472 case 0:
473 cpu->cp15.r2.d = value;
474 break;
475 case 1:
476 cpu->cp15.r2.i = value;
477 break;
478 default:
479 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
480 break;
481 }
482}
483
484static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
485 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
486 switch (opcode2) {
487 case 0:
488 cpu->cp15.r3.d = value;
489 break;
490 default:
491 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
492 break;
493 }
494}
495
496static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
497 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
498}
499
500static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
501 cpu->cp15.r6.region[crm] = value;
502 uint32_t base = ARMProtectionGetBase(value) << 12;
503 uint32_t size = 2 << ARMProtectionGetSize(value);
504 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
505}
506
507static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
508 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
509}
510
511static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
512 uint32_t base = ARMTCMControlGetBase(value) << 12;
513 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
514 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
515 switch (opcode2) {
516 case 0:
517 cpu->cp15.r9.d = value;
518 break;
519 case 1:
520 cpu->cp15.r9.i = value;
521 break;
522 default:
523 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
524 break;
525 }
526}
527
528void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
529 switch (crn) {
530 default:
531 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
532 break;
533 case 0:
534 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
535 ARMRaiseUndefined(cpu);
536 break;
537 case 1:
538 _writeSysControl(cpu, crm, opcode2, value);
539 break;
540 case 2:
541 _writeCacheControl(cpu, crm, opcode2, value);
542 break;
543 case 3:
544 _writeWriteBufferControl(cpu, crm, opcode2, value);
545 break;
546 case 5:
547 _writeAccessControl(cpu, crm, opcode2, value);
548 break;
549 case 6:
550 _writeRegionConfiguration(cpu, crm, opcode2, value);
551 break;
552 case 7:
553 _writeCache(cpu, crm, opcode2, value);
554 break;
555 case 9:
556 _writeTCMControl(cpu, crm, opcode2, value);
557 break;
558 }
559}
560
561void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
562 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
563 ARMRaiseIRQ(cpu);
564 }
565}
566void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
567 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
568 ARMRaiseIRQ(cpu);
569 }
570}
571
572void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
573 if (irq < 16) {
574 io[DS_REG_IF_LO >> 1] |= 1 << irq;
575 } else {
576 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
577 }
578
579 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
580 cpu->halted = 0;
581 if (io[DS_REG_IME >> 1]) {
582 ARMRaiseIRQ(cpu);
583 }
584 }
585}