src/arm/arm.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef ARM_H
7#define ARM_H
8
9#include "util/common.h"
10
11#include "core/cpu.h"
12
13enum {
14 ARM_SP = 13,
15 ARM_LR = 14,
16 ARM_PC = 15
17};
18
19enum ExecutionMode {
20 MODE_ARM = 0,
21 MODE_THUMB = 1
22};
23
24enum PrivilegeMode {
25 MODE_USER = 0x10,
26 MODE_FIQ = 0x11,
27 MODE_IRQ = 0x12,
28 MODE_SUPERVISOR = 0x13,
29 MODE_ABORT = 0x17,
30 MODE_UNDEFINED = 0x1B,
31 MODE_SYSTEM = 0x1F
32};
33
34enum WordSize {
35 WORD_SIZE_ARM = 4,
36 WORD_SIZE_THUMB = 2
37};
38
39enum ExecutionVector {
40 BASE_RESET = 0x00000000,
41 BASE_UNDEF = 0x00000004,
42 BASE_SWI = 0x00000008,
43 BASE_PABT = 0x0000000C,
44 BASE_DABT = 0x00000010,
45 BASE_IRQ = 0x00000018,
46 BASE_FIQ = 0x0000001C
47};
48
49enum RegisterBank {
50 BANK_NONE = 0,
51 BANK_FIQ = 1,
52 BANK_IRQ = 2,
53 BANK_SUPERVISOR = 3,
54 BANK_ABORT = 4,
55 BANK_UNDEFINED = 5
56};
57
58enum LSMDirection {
59 LSM_B = 1,
60 LSM_D = 2,
61 LSM_IA = 0,
62 LSM_IB = 1,
63 LSM_DA = 2,
64 LSM_DB = 3
65};
66
67struct ARMCore;
68
69union PSR {
70 struct {
71#if defined(__POWERPC__) || defined(__PPC__)
72 unsigned n : 1;
73 unsigned z : 1;
74 unsigned c : 1;
75 unsigned v : 1;
76 unsigned : 20;
77 unsigned i : 1;
78 unsigned f : 1;
79 unsigned t : 1;
80 unsigned priv : 5;
81#else
82 unsigned priv : 5;
83 unsigned t : 1;
84 unsigned f : 1;
85 unsigned i : 1;
86 unsigned : 20;
87 unsigned v : 1;
88 unsigned c : 1;
89 unsigned z : 1;
90 unsigned n : 1;
91#endif
92 };
93
94 int32_t packed;
95};
96
97struct ARMMemory {
98 uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
99 uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
100 uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
101
102 void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
103 void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
104 void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
105
106 uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
107 int* cycleCounter);
108 uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
109 int* cycleCounter);
110
111 uint32_t* activeRegion;
112 uint32_t activeMask;
113 uint32_t activeSeqCycles32;
114 uint32_t activeSeqCycles16;
115 uint32_t activeNonseqCycles32;
116 uint32_t activeNonseqCycles16;
117 int32_t (*stall)(struct ARMCore*, int32_t wait);
118 void (*setActiveRegion)(struct ARMCore*, uint32_t address);
119};
120
121struct ARMInterruptHandler {
122 void (*reset)(struct ARMCore* cpu);
123 void (*processEvents)(struct ARMCore* cpu);
124 void (*swi16)(struct ARMCore* cpu, int immediate);
125 void (*swi32)(struct ARMCore* cpu, int immediate);
126 void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
127 void (*bkpt16)(struct ARMCore* cpu, int immediate);
128 void (*bkpt32)(struct ARMCore* cpu, int immediate);
129 void (*readCPSR)(struct ARMCore* cpu);
130 void (*writeCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2, uint32_t value);
131
132 void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
133};
134
135DECL_BITFIELD(ARMCPUID, uint32_t);
136DECL_BITFIELD(ARMCacheType, uint32_t);
137DECL_BITFIELD(ARMTCMType, uint32_t);
138DECL_BITFIELD(ARMTLBType, uint32_t);
139DECL_BITFIELD(ARMMPUType, uint32_t);
140
141DECL_BITFIELD(ARMControlReg, uint32_t);
142DECL_BIT(ARMControlReg, M, 0);
143DECL_BIT(ARMControlReg, A, 1);
144DECL_BIT(ARMControlReg, C, 2);
145DECL_BIT(ARMControlReg, W, 3);
146DECL_BIT(ARMControlReg, P, 4);
147DECL_BIT(ARMControlReg, D, 5);
148DECL_BIT(ARMControlReg, L, 6);
149DECL_BIT(ARMControlReg, B, 7);
150DECL_BIT(ARMControlReg, S, 8);
151DECL_BIT(ARMControlReg, R, 9);
152DECL_BIT(ARMControlReg, F, 10);
153DECL_BIT(ARMControlReg, Z, 11);
154DECL_BIT(ARMControlReg, I, 12);
155DECL_BIT(ARMControlReg, V, 13);
156DECL_BIT(ARMControlReg, RR, 14);
157DECL_BIT(ARMControlReg, L4, 15);
158DECL_BIT(ARMControlReg, FI, 21);
159DECL_BIT(ARMControlReg, U, 22);
160DECL_BIT(ARMControlReg, XP, 23);
161DECL_BIT(ARMControlReg, VE, 24);
162DECL_BIT(ARMControlReg, EE, 25);
163DECL_BIT(ARMControlReg, L2, 26);
164
165DECL_BITFIELD(ARMCoprocessorAccess, uint32_t);
166
167DECL_BITFIELD(ARMCacheability, uint32_t);
168DECL_BIT(ARMCacheability, 0, 0);
169DECL_BIT(ARMCacheability, 1, 1);
170DECL_BIT(ARMCacheability, 2, 2);
171DECL_BIT(ARMCacheability, 3, 3);
172DECL_BIT(ARMCacheability, 4, 4);
173DECL_BIT(ARMCacheability, 5, 5);
174DECL_BIT(ARMCacheability, 6, 6);
175DECL_BIT(ARMCacheability, 7, 7);
176
177DECL_BITFIELD(ARMProtection, uint32_t);
178DECL_BIT(ARMProtection, Enable, 0);
179DECL_BITS(ARMProtection, Size, 1, 5);
180DECL_BITS(ARMProtection, Base, 12, 20);
181
182DECL_BITFIELD(ARMTCMControl, uint32_t);
183DECL_BITS(ARMTCMControl, VirtualSize, 1, 5);
184DECL_BITS(ARMTCMControl, Base, 12, 20);
185
186struct ARMCP15 {
187 struct {
188 ARMCPUID cpuid;
189 ARMCacheType cachetype;
190 ARMTCMType tcmtype;
191 ARMTLBType tlbtype;
192 ARMMPUType mputype;
193 } r0;
194 struct {
195 ARMControlReg c0;
196 uint32_t c1;
197 ARMCoprocessorAccess cpAccess;
198 } r1;
199 struct {
200 ARMCacheability d;
201 ARMCacheability i;
202 } r2;
203 struct {
204 ARMCacheability d;
205 } r3;
206 struct {
207 ARMProtection region[8];
208 } r6;
209 struct {
210 ARMTCMControl d;
211 ARMTCMControl i;
212 } r9;
213};
214
215struct ARMCore {
216 int32_t gprs[16];
217 union PSR cpsr;
218 union PSR spsr;
219
220 int32_t cycles;
221 int32_t nextEvent;
222 int halted;
223
224 int32_t bankedRegisters[6][7];
225 int32_t bankedSPSRs[6];
226
227 int32_t shifterOperand;
228 int32_t shifterCarryOut;
229
230 uint32_t prefetch[2];
231 enum ExecutionMode executionMode;
232 enum PrivilegeMode privilegeMode;
233
234 struct ARMMemory memory;
235 struct ARMInterruptHandler irqh;
236 struct ARMCP15 cp15;
237
238 struct mCPUComponent* master;
239
240 size_t numComponents;
241 struct mCPUComponent** components;
242};
243
244void ARMInit(struct ARMCore* cpu);
245void ARMDeinit(struct ARMCore* cpu);
246void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
247void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
248void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
249
250void ARMReset(struct ARMCore* cpu);
251void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
252void ARMRaiseIRQ(struct ARMCore*);
253void ARMRaiseSWI(struct ARMCore*);
254void ARMRaiseUndefined(struct ARMCore*);
255
256void ARMRun(struct ARMCore* cpu);
257void ARMRunLoop(struct ARMCore* cpu);
258int32_t ARMRunCycles(struct ARMCore* cpu, int32_t cycles);
259void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
260
261#endif