1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm/arm.h"
 12#include "core/log.h"
 13
 14enum DSMemoryRegion {
 15	DS7_REGION_BIOS = 0x0,
 16	DS9_REGION_ITCM = 0x0,
 17	DS9_REGION_ITCM_MIRROR = 0x1,
 18	DS_REGION_RAM = 0x2,
 19	DS_REGION_WORKING_RAM = 0x3,
 20	DS_REGION_IO = 0x4,
 21	DS9_REGION_PALETTE_RAM = 0x5,
 22	DS_REGION_VRAM = 0x6,
 23	DS9_REGION_OAM = 0x7,
 24	DS_REGION_SLOT2 = 0x8,
 25	DS_REGION_SLOT2_EX = 0x9,
 26	DS_REGION_SLOT2_SRAM = 0xA,
 27	DS9_REGION_BIOS = 0xFF,
 28};
 29
 30enum DSMemoryBase {
 31	DS7_BASE_BIOS = 0x00000000,
 32	DS9_BASE_ITCM = 0x00000000,
 33	DS_BASE_RAM = 0x02000000,
 34	DS_BASE_WORKING_RAM = 0x03000000,
 35	DS_BASE_IO = 0x04000000,
 36	DS9_BASE_PALETTE_RAM = 0x05000000,
 37	DS_BASE_VRAM = 0x06000000,
 38	DS9_BASE_OAM = 0x07000000,
 39	DS_BASE_SLOT2 = 0x08000000,
 40	DS_BASE_SLOT2_EX = 0x09000000,
 41	DS9_BASE_BIOS = 0xFFFF0000,
 42};
 43
 44enum {
 45	DS9_SIZE_ITCM = 0x00008000,
 46	DS9_SIZE_DTCM = 0x00004000,
 47	DS7_SIZE_BIOS = 0x00004000,
 48	DS9_SIZE_BIOS = 0x00008000,
 49	DS_SIZE_RAM = 0x00400000,
 50	DS_SIZE_WORKING_RAM = 0x00008000,
 51	DS9_SIZE_PALETTE_RAM = 0x00000800,
 52	DS9_SIZE_OAM = 0x00000800,
 53	DS_SIZE_SLOT2 = 0x02000000,
 54	DS_SIZE_SLOT2_SRAM = 0x00010000,
 55};
 56
 57enum {
 58	DS_OFFSET_MASK = 0x00FFFFFF,
 59	DS_BASE_OFFSET = 24
 60};
 61
 62enum DSDMAControl {
 63	DS_DMA_INCREMENT = 0,
 64	DS_DMA_DECREMENT = 1,
 65	DS_DMA_FIXED = 2,
 66	DS_DMA_INCREMENT_RELOAD = 3
 67};
 68
 69enum DSDMATiming {
 70	DS_DMA_TIMING_NOW = 0,
 71	DS_DMA_TIMING_VBLANK = 1,
 72	DS_DMA_TIMING_HBLANK = 2,
 73	DS7_DMA_TIMING_SLOT1 = 2,
 74	DS_DMA_TIMING_DISPLAY_START = 3,
 75	DS7_DMA_TIMING_CUSTOM = 3,
 76	DS_DMA_TIMING_MEMORY_DISPLAY = 4,
 77	DS9_DMA_TIMING_SLOT1 = 5,
 78	DS_DMA_TIMING_SLOT2 = 6,
 79	DS_DMA_TIMING_GEOM_FIFO = 7,
 80};
 81
 82mLOG_DECLARE_CATEGORY(DS_MEM);
 83
 84DECL_BITFIELD(DSDMARegister, uint16_t);
 85DECL_BITS(DSDMARegister, DestControl, 5, 2);
 86DECL_BITS(DSDMARegister, SrcControl, 7, 2);
 87DECL_BIT(DSDMARegister, Repeat, 9);
 88DECL_BIT(DSDMARegister, Width, 10);
 89DECL_BITS(DSDMARegister, Timing7, 12, 2);
 90DECL_BITS(DSDMARegister, Timing9, 11, 3);
 91DECL_BIT(DSDMARegister, DoIRQ, 14);
 92DECL_BIT(DSDMARegister, Enable, 15);
 93
 94struct DSDMA {
 95	DSDMARegister reg;
 96
 97	uint32_t source;
 98	uint32_t dest;
 99	int32_t count;
100	uint32_t nextSource;
101	uint32_t nextDest;
102	int32_t nextCount;
103	int32_t nextEvent;
104};
105
106struct DSMemory {
107	uint32_t* bios7;
108	uint32_t* bios9;
109	uint32_t* itcm;
110	uint32_t* dtcm;
111	uint32_t* ram;
112	uint32_t* wram;
113	uint32_t* rom;
114
115	size_t romSize;
116
117	char waitstatesSeq32[256];
118	char waitstatesSeq16[256];
119	char waitstatesNonseq32[256];
120	char waitstatesNonseq16[256];
121	char waitstatesPrefetchSeq32[16];
122	char waitstatesPrefetchSeq16[16];
123	char waitstatesPrefetchNonseq32[16];
124	char waitstatesPrefetchNonseq16[16];
125	int activeRegion7;
126	int activeRegion9;
127
128	struct DSDMA dma7[4];
129	struct DSDMA dma9[4];
130	int activeDMA7;
131	int activeDMA9;
132	int32_t nextDMA;
133	int32_t eventDiff;
134};
135
136struct DS;
137void DSMemoryInit(struct DS* ds);
138void DSMemoryDeinit(struct DS* ds);
139
140void DSMemoryReset(struct DS* ds);
141
142uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
143uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
144uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
145
146void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
147void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
148void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
149
150uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
151                         int* cycleCounter);
152uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
153                          int* cycleCounter);
154
155uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
156uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
157uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
158
159void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
160void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
161void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
162
163uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
164                         int* cycleCounter);
165uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
166                          int* cycleCounter);
167
168#endif