src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/memory.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/gb/gb.h>
10#include <mgba/internal/gb/io.h>
11#include <mgba/internal/gb/mbc.h>
12#include <mgba/internal/gb/serialize.h>
13#include <mgba/internal/lr35902/lr35902.h>
14
15#include <mgba-util/memory.h>
16
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory", "gb.memory");
18
19struct OAMBlock {
20 uint16_t low;
21 uint16_t high;
22};
23
24static const struct OAMBlock _oamBlockDMG[] = {
25 { 0xA000, 0xFE00 },
26 { 0xA000, 0xFE00 },
27 { 0xA000, 0xFE00 },
28 { 0xA000, 0xFE00 },
29 { 0x8000, 0xA000 },
30 { 0xA000, 0xFE00 },
31 { 0xA000, 0xFE00 },
32 { 0xA000, 0xFE00 },
33};
34
35static const struct OAMBlock _oamBlockCGB[] = {
36 { 0xA000, 0xC000 },
37 { 0xA000, 0xC000 },
38 { 0xA000, 0xC000 },
39 { 0xA000, 0xC000 },
40 { 0x8000, 0xA000 },
41 { 0xA000, 0xC000 },
42 { 0xC000, 0xFE00 },
43 { 0xA000, 0xC000 },
44};
45
46static void _pristineCow(struct GB* gba);
47
48static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
49 if (UNLIKELY(address >= cpu->memory.activeRegionEnd)) {
50 cpu->memory.setActiveRegion(cpu, address);
51 return cpu->memory.cpuLoad8(cpu, address);
52 }
53 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
54}
55
56static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
57 struct GB* gb = (struct GB*) cpu->master;
58 struct GBMemory* memory = &gb->memory;
59 switch (address >> 12) {
60 case GB_REGION_CART_BANK0:
61 case GB_REGION_CART_BANK0 + 1:
62 case GB_REGION_CART_BANK0 + 2:
63 case GB_REGION_CART_BANK0 + 3:
64 cpu->memory.cpuLoad8 = GBFastLoad8;
65 cpu->memory.activeRegion = memory->romBase;
66 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
67 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
68 break;
69 case GB_REGION_CART_BANK1:
70 case GB_REGION_CART_BANK1 + 1:
71 case GB_REGION_CART_BANK1 + 2:
72 case GB_REGION_CART_BANK1 + 3:
73 cpu->memory.cpuLoad8 = GBFastLoad8;
74 cpu->memory.activeRegion = memory->romBank;
75 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
76 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
77 break;
78 default:
79 cpu->memory.cpuLoad8 = GBLoad8;
80 break;
81 }
82}
83
84static void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
85static void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
86
87void GBMemoryInit(struct GB* gb) {
88 struct LR35902Core* cpu = gb->cpu;
89 cpu->memory.cpuLoad8 = GBLoad8;
90 cpu->memory.load8 = GBLoad8;
91 cpu->memory.store8 = GBStore8;
92 cpu->memory.currentSegment = GBCurrentSegment;
93 cpu->memory.setActiveRegion = GBSetActiveRegion;
94
95 gb->memory.wram = 0;
96 gb->memory.wramBank = 0;
97 gb->memory.rom = 0;
98 gb->memory.romBank = 0;
99 gb->memory.romSize = 0;
100 gb->memory.sram = 0;
101 gb->memory.mbcType = GB_MBC_AUTODETECT;
102 gb->memory.mbcRead = NULL;
103 gb->memory.mbcWrite = NULL;
104
105 gb->memory.rtc = NULL;
106
107 GBIOInit(gb);
108}
109
110void GBMemoryDeinit(struct GB* gb) {
111 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
112 if (gb->memory.rom) {
113 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
114 }
115}
116
117void GBMemoryReset(struct GB* gb) {
118 if (gb->memory.wram) {
119 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
120 }
121 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
122 if (gb->model >= GB_MODEL_CGB) {
123 uint32_t* base = (uint32_t*) gb->memory.wram;
124 size_t i;
125 uint32_t pattern = 0;
126 for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
127 if ((i & 0x1FF) == 0) {
128 pattern = ~pattern;
129 }
130 base[i + 0] = pattern;
131 base[i + 1] = pattern;
132 base[i + 2] = ~pattern;
133 base[i + 3] = ~pattern;
134 }
135 }
136 GBMemorySwitchWramBank(&gb->memory, 1);
137 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
138 gb->memory.currentBank = 1;
139 gb->memory.sramCurrentBank = 0;
140
141 gb->memory.ime = false;
142 gb->memory.ie = 0;
143
144 gb->memory.dmaRemaining = 0;
145 gb->memory.dmaSource = 0;
146 gb->memory.dmaDest = 0;
147 gb->memory.hdmaRemaining = 0;
148 gb->memory.hdmaSource = 0;
149 gb->memory.hdmaDest = 0;
150 gb->memory.isHdma = false;
151
152
153 gb->memory.dmaEvent.context = gb;
154 gb->memory.dmaEvent.name = "GB DMA";
155 gb->memory.dmaEvent.callback = _GBMemoryDMAService;
156 gb->memory.dmaEvent.priority = 0x40;
157 gb->memory.hdmaEvent.context = gb;
158 gb->memory.hdmaEvent.name = "GB HDMA";
159 gb->memory.hdmaEvent.callback = _GBMemoryHDMAService;
160 gb->memory.hdmaEvent.priority = 0x41;
161
162 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
163 switch (gb->memory.mbcType) {
164 case GB_MBC1:
165 gb->memory.mbcState.mbc1.mode = 0;
166 break;
167 default:
168 memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
169 }
170
171 GBMBCInit(gb);
172 gb->memory.sramBank = gb->memory.sram;
173
174 if (!gb->memory.wram) {
175 GBMemoryDeinit(gb);
176 }
177}
178
179void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
180 bank &= 7;
181 if (!bank) {
182 bank = 1;
183 }
184 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
185 memory->wramCurrentBank = bank;
186}
187
188uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
189 struct GB* gb = (struct GB*) cpu->master;
190 struct GBMemory* memory = &gb->memory;
191 if (gb->memory.dmaRemaining) {
192 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
193 block = &block[memory->dmaSource >> 13];
194 if (address >= block->low && address < block->high) {
195 return 0xFF;
196 }
197 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
198 return 0xFF;
199 }
200 }
201 switch (address >> 12) {
202 case GB_REGION_CART_BANK0:
203 case GB_REGION_CART_BANK0 + 1:
204 case GB_REGION_CART_BANK0 + 2:
205 case GB_REGION_CART_BANK0 + 3:
206 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
207 case GB_REGION_CART_BANK1:
208 case GB_REGION_CART_BANK1 + 1:
209 case GB_REGION_CART_BANK1 + 2:
210 case GB_REGION_CART_BANK1 + 3:
211 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
212 case GB_REGION_VRAM:
213 case GB_REGION_VRAM + 1:
214 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
215 case GB_REGION_EXTERNAL_RAM:
216 case GB_REGION_EXTERNAL_RAM + 1:
217 if (memory->rtcAccess) {
218 return memory->rtcRegs[memory->activeRtcReg];
219 } else if (memory->mbcRead) {
220 return memory->mbcRead(memory, address);
221 } else if (memory->sramAccess) {
222 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
223 } else if (memory->mbcType == GB_HuC3) {
224 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
225 }
226 return 0xFF;
227 case GB_REGION_WORKING_RAM_BANK0:
228 case GB_REGION_WORKING_RAM_BANK0 + 2:
229 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
230 case GB_REGION_WORKING_RAM_BANK1:
231 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
232 default:
233 if (address < GB_BASE_OAM) {
234 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
235 }
236 if (address < GB_BASE_UNUSABLE) {
237 if (gb->video.mode < 2) {
238 return gb->video.oam.raw[address & 0xFF];
239 }
240 return 0xFF;
241 }
242 if (address < GB_BASE_IO) {
243 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
244 return 0xFF;
245 }
246 if (address < GB_BASE_HRAM) {
247 return GBIORead(gb, address & (GB_SIZE_IO - 1));
248 }
249 if (address < GB_BASE_IE) {
250 return memory->hram[address & GB_SIZE_HRAM];
251 }
252 return GBIORead(gb, REG_IE);
253 }
254}
255
256void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
257 struct GB* gb = (struct GB*) cpu->master;
258 struct GBMemory* memory = &gb->memory;
259 if (gb->memory.dmaRemaining) {
260 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
261 block = &block[memory->dmaSource >> 13];
262 if (address >= block->low && address < block->high) {
263 return;
264 }
265 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
266 return;
267 }
268 }
269 switch (address >> 12) {
270 case GB_REGION_CART_BANK0:
271 case GB_REGION_CART_BANK0 + 1:
272 case GB_REGION_CART_BANK0 + 2:
273 case GB_REGION_CART_BANK0 + 3:
274 case GB_REGION_CART_BANK1:
275 case GB_REGION_CART_BANK1 + 1:
276 case GB_REGION_CART_BANK1 + 2:
277 case GB_REGION_CART_BANK1 + 3:
278 memory->mbcWrite(gb, address, value);
279 cpu->memory.setActiveRegion(cpu, cpu->pc);
280 return;
281 case GB_REGION_VRAM:
282 case GB_REGION_VRAM + 1:
283 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) | (GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank));
284 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
285 return;
286 case GB_REGION_EXTERNAL_RAM:
287 case GB_REGION_EXTERNAL_RAM + 1:
288 if (memory->rtcAccess) {
289 memory->rtcRegs[memory->activeRtcReg] = value;
290 } else if (memory->sramAccess) {
291 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
292 } else {
293 memory->mbcWrite(gb, address, value);
294 }
295 gb->sramDirty |= GB_SRAM_DIRT_NEW;
296 return;
297 case GB_REGION_WORKING_RAM_BANK0:
298 case GB_REGION_WORKING_RAM_BANK0 + 2:
299 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
300 return;
301 case GB_REGION_WORKING_RAM_BANK1:
302 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
303 return;
304 default:
305 if (address < GB_BASE_OAM) {
306 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
307 } else if (address < GB_BASE_UNUSABLE) {
308 if (gb->video.mode < 2) {
309 gb->video.oam.raw[address & 0xFF] = value;
310 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
311 }
312 } else if (address < GB_BASE_IO) {
313 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
314 } else if (address < GB_BASE_HRAM) {
315 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
316 } else if (address < GB_BASE_IE) {
317 memory->hram[address & GB_SIZE_HRAM] = value;
318 } else {
319 GBIOWrite(gb, REG_IE, value);
320 }
321 }
322}
323
324int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address) {
325 struct GB* gb = (struct GB*) cpu->master;
326 struct GBMemory* memory = &gb->memory;
327 switch (address >> 12) {
328 case GB_REGION_CART_BANK0:
329 case GB_REGION_CART_BANK0 + 1:
330 case GB_REGION_CART_BANK0 + 2:
331 case GB_REGION_CART_BANK0 + 3:
332 return 0;
333 case GB_REGION_CART_BANK1:
334 case GB_REGION_CART_BANK1 + 1:
335 case GB_REGION_CART_BANK1 + 2:
336 case GB_REGION_CART_BANK1 + 3:
337 return memory->currentBank;
338 case GB_REGION_VRAM:
339 case GB_REGION_VRAM + 1:
340 return gb->video.vramCurrentBank;
341 case GB_REGION_EXTERNAL_RAM:
342 case GB_REGION_EXTERNAL_RAM + 1:
343 return memory->sramCurrentBank;
344 case GB_REGION_WORKING_RAM_BANK0:
345 case GB_REGION_WORKING_RAM_BANK0 + 2:
346 return 0;
347 case GB_REGION_WORKING_RAM_BANK1:
348 return memory->wramCurrentBank;
349 default:
350 return 0;
351 }
352}
353
354uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) {
355 struct GB* gb = (struct GB*) cpu->master;
356 struct GBMemory* memory = &gb->memory;
357 switch (address >> 12) {
358 case GB_REGION_CART_BANK0:
359 case GB_REGION_CART_BANK0 + 1:
360 case GB_REGION_CART_BANK0 + 2:
361 case GB_REGION_CART_BANK0 + 3:
362 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
363 case GB_REGION_CART_BANK1:
364 case GB_REGION_CART_BANK1 + 1:
365 case GB_REGION_CART_BANK1 + 2:
366 case GB_REGION_CART_BANK1 + 3:
367 if (segment < 0) {
368 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
369 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
370 return memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
371 } else {
372 return 0xFF;
373 }
374 case GB_REGION_VRAM:
375 case GB_REGION_VRAM + 1:
376 if (segment < 0) {
377 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
378 } else if (segment < 2) {
379 return gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment *GB_SIZE_VRAM_BANK0];
380 } else {
381 return 0xFF;
382 }
383 case GB_REGION_EXTERNAL_RAM:
384 case GB_REGION_EXTERNAL_RAM + 1:
385 if (memory->rtcAccess) {
386 return memory->rtcRegs[memory->activeRtcReg];
387 } else if (memory->sramAccess) {
388 if (segment < 0) {
389 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
390 } else if ((size_t) segment * GB_SIZE_EXTERNAL_RAM < gb->sramSize) {
391 return memory->sram[(address & (GB_SIZE_EXTERNAL_RAM - 1)) + segment *GB_SIZE_EXTERNAL_RAM];
392 } else {
393 return 0xFF;
394 }
395 } else if (memory->mbcRead) {
396 return memory->mbcRead(memory, address);
397 } else if (memory->mbcType == GB_HuC3) {
398 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
399 }
400 return 0xFF;
401 case GB_REGION_WORKING_RAM_BANK0:
402 case GB_REGION_WORKING_RAM_BANK0 + 2:
403 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
404 case GB_REGION_WORKING_RAM_BANK1:
405 if (segment < 0) {
406 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
407 } else if (segment < 8) {
408 return memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment *GB_SIZE_WORKING_RAM_BANK0];
409 } else {
410 return 0xFF;
411 }
412 default:
413 if (address < GB_BASE_OAM) {
414 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
415 }
416 if (address < GB_BASE_UNUSABLE) {
417 if (gb->video.mode < 2) {
418 return gb->video.oam.raw[address & 0xFF];
419 }
420 return 0xFF;
421 }
422 if (address < GB_BASE_IO) {
423 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
424 return 0xFF;
425 }
426 if (address < GB_BASE_HRAM) {
427 return GBIORead(gb, address & (GB_SIZE_IO - 1));
428 }
429 if (address < GB_BASE_IE) {
430 return memory->hram[address & GB_SIZE_HRAM];
431 }
432 return GBIORead(gb, REG_IE);
433 }
434}
435
436void GBMemoryDMA(struct GB* gb, uint16_t base) {
437 if (base > 0xF100) {
438 return;
439 }
440 mTimingDeschedule(&gb->timing, &gb->memory.dmaEvent);
441 mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8);
442 if (gb->cpu->cycles + 8 < gb->cpu->nextEvent) {
443 gb->cpu->nextEvent = gb->cpu->cycles + 8;
444 }
445 gb->memory.dmaSource = base;
446 gb->memory.dmaDest = 0;
447 gb->memory.dmaRemaining = 0xA0;
448}
449
450void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
451 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
452 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
453 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
454 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
455 gb->memory.hdmaSource &= 0xFFF0;
456 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
457 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
458 return;
459 }
460 gb->memory.hdmaDest &= 0x1FF0;
461 gb->memory.hdmaDest |= 0x8000;
462 bool wasHdma = gb->memory.isHdma;
463 gb->memory.isHdma = value & 0x80;
464 if ((!wasHdma && !gb->memory.isHdma) || gb->video.mode == 0) {
465 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
466 gb->cpuBlocked = true;
467 mTimingSchedule(&gb->timing, &gb->memory.hdmaEvent, 0);
468 gb->cpu->nextEvent = gb->cpu->cycles;
469 }
470}
471
472void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
473 struct GB* gb = context;
474 int dmaRemaining = gb->memory.dmaRemaining;
475 gb->memory.dmaRemaining = 0;
476 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
477 // TODO: Can DMA write OAM during modes 2-3?
478 gb->video.oam.raw[gb->memory.dmaDest] = b;
479 gb->video.renderer->writeOAM(gb->video.renderer, gb->memory.dmaDest);
480 ++gb->memory.dmaSource;
481 ++gb->memory.dmaDest;
482 gb->memory.dmaRemaining = dmaRemaining - 1;
483 if (gb->memory.dmaRemaining) {
484 mTimingSchedule(timing, &gb->memory.dmaEvent, 4 - cyclesLate);
485 }
486}
487
488void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
489 struct GB* gb = context;
490 gb->cpuBlocked = true;
491 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
492 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
493 ++gb->memory.hdmaSource;
494 ++gb->memory.hdmaDest;
495 --gb->memory.hdmaRemaining;
496 if (gb->memory.hdmaRemaining) {
497 mTimingDeschedule(timing, &gb->memory.hdmaEvent);
498 mTimingSchedule(timing, &gb->memory.hdmaEvent, 2 - cyclesLate);
499 } else {
500 gb->cpuBlocked = false;
501 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
502 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
503 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
504 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
505 if (gb->memory.isHdma) {
506 --gb->memory.io[REG_HDMA5];
507 if (gb->memory.io[REG_HDMA5] == 0xFF) {
508 gb->memory.isHdma = false;
509 }
510 } else {
511 gb->memory.io[REG_HDMA5] = 0xFF;
512 }
513 }
514}
515
516void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment) {
517 struct GB* gb = (struct GB*) cpu->master;
518 struct GBMemory* memory = &gb->memory;
519 int8_t oldValue = -1;
520
521 switch (address >> 12) {
522 case GB_REGION_CART_BANK0:
523 case GB_REGION_CART_BANK0 + 1:
524 case GB_REGION_CART_BANK0 + 2:
525 case GB_REGION_CART_BANK0 + 3:
526 _pristineCow(gb);
527 oldValue = memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
528 memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)] = value;
529 break;
530 case GB_REGION_CART_BANK1:
531 case GB_REGION_CART_BANK1 + 1:
532 case GB_REGION_CART_BANK1 + 2:
533 case GB_REGION_CART_BANK1 + 3:
534 _pristineCow(gb);
535 if (segment < 0) {
536 oldValue = memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
537 memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)] = value;
538 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
539 oldValue = memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
540 memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0] = value;
541 } else {
542 return;
543 }
544 break;
545 case GB_REGION_VRAM:
546 case GB_REGION_VRAM + 1:
547 if (segment < 0) {
548 oldValue = gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
549 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
550 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank);
551 } else if (segment < 2) {
552 oldValue = gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0];
553 gb->video.vramBank[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0] = value;
554 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0);
555 } else {
556 return;
557 }
558 break;
559 case GB_REGION_EXTERNAL_RAM:
560 case GB_REGION_EXTERNAL_RAM + 1:
561 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
562 return;
563 case GB_REGION_WORKING_RAM_BANK0:
564 case GB_REGION_WORKING_RAM_BANK0 + 2:
565 oldValue = memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
566 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
567 break;
568 case GB_REGION_WORKING_RAM_BANK1:
569 if (segment < 0) {
570 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
571 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
572 } else if (segment < 8) {
573 oldValue = memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0];
574 memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0] = value;
575 } else {
576 return;
577 }
578 break;
579 default:
580 if (address < GB_BASE_OAM) {
581 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
582 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
583 } else if (address < GB_BASE_UNUSABLE) {
584 oldValue = gb->video.oam.raw[address & 0xFF];
585 gb->video.oam.raw[address & 0xFF] = value;
586 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
587 } else if (address < GB_BASE_HRAM) {
588 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
589 return;
590 } else if (address < GB_BASE_IE) {
591 oldValue = memory->hram[address & GB_SIZE_HRAM];
592 memory->hram[address & GB_SIZE_HRAM] = value;
593 } else {
594 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
595 return;
596 }
597 }
598 if (old) {
599 *old = oldValue;
600 }
601}
602
603void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
604 const struct GBMemory* memory = &gb->memory;
605 memcpy(state->wram, memory->wram, GB_SIZE_WORKING_RAM);
606 memcpy(state->hram, memory->hram, GB_SIZE_HRAM);
607 STORE_16LE(memory->currentBank, 0, &state->memory.currentBank);
608 state->memory.wramCurrentBank = memory->wramCurrentBank;
609 state->memory.sramCurrentBank = memory->sramCurrentBank;
610
611 STORE_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
612 STORE_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
613
614 STORE_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
615 STORE_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
616
617 STORE_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
618 state->memory.dmaRemaining = memory->dmaRemaining;
619 memcpy(state->memory.rtcRegs, memory->rtcRegs, sizeof(state->memory.rtcRegs));
620
621 STORE_32LE(memory->dmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.dmaNext);
622 STORE_32LE(memory->hdmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.hdmaNext);
623
624 GBSerializedMemoryFlags flags = 0;
625 flags = GBSerializedMemoryFlagsSetSramAccess(flags, memory->sramAccess);
626 flags = GBSerializedMemoryFlagsSetRtcAccess(flags, memory->rtcAccess);
627 flags = GBSerializedMemoryFlagsSetRtcLatched(flags, memory->rtcLatched);
628 flags = GBSerializedMemoryFlagsSetIme(flags, memory->ime);
629 flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
630 flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
631 STORE_16LE(flags, 0, &state->memory.flags);
632
633 switch (memory->mbcType) {
634 case GB_MBC1:
635 state->memory.mbc1.mode = memory->mbcState.mbc1.mode;
636 state->memory.mbc1.multicartStride = memory->mbcState.mbc1.multicartStride;
637 break;
638 case GB_MBC3_RTC:
639 STORE_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
640 break;
641 case GB_MBC7:
642 state->memory.mbc7.state = memory->mbcState.mbc7.state;
643 state->memory.mbc7.eeprom = memory->mbcState.mbc7.eeprom;
644 state->memory.mbc7.address = memory->mbcState.mbc7.address;
645 state->memory.mbc7.access = memory->mbcState.mbc7.access;
646 state->memory.mbc7.latch = memory->mbcState.mbc7.latch;
647 state->memory.mbc7.srBits = memory->mbcState.mbc7.srBits;
648 STORE_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
649 STORE_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
650 break;
651 default:
652 break;
653 }
654}
655
656void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
657 struct GBMemory* memory = &gb->memory;
658 memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
659 memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
660 LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
661 memory->wramCurrentBank = state->memory.wramCurrentBank;
662 memory->sramCurrentBank = state->memory.sramCurrentBank;
663
664 GBMBCSwitchBank(gb, memory->currentBank);
665 GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
666 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
667
668 LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
669 LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
670
671 LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
672 LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
673
674 LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
675 memory->dmaRemaining = state->memory.dmaRemaining;
676 memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
677
678 uint32_t when;
679 LOAD_32LE(when, 0, &state->memory.dmaNext);
680 if (memory->dmaRemaining) {
681 mTimingSchedule(&gb->timing, &memory->dmaEvent, when);
682 }
683 LOAD_32LE(when, 0, &state->memory.hdmaNext);
684 if (memory->hdmaRemaining) {
685 mTimingSchedule(&gb->timing, &memory->hdmaEvent, when);
686 }
687
688 GBSerializedMemoryFlags flags;
689 LOAD_16LE(flags, 0, &state->memory.flags);
690 memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
691 memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
692 memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
693 memory->ime = GBSerializedMemoryFlagsGetIme(flags);
694 memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
695 memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
696
697 switch (memory->mbcType) {
698 case GB_MBC1:
699 memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
700 memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
701 if (memory->mbcState.mbc1.mode) {
702 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
703 }
704 break;
705 case GB_MBC3_RTC:
706 // TODO?
707 //LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
708 break;
709 case GB_MBC7:
710 memory->mbcState.mbc7.state = state->memory.mbc7.state;
711 memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
712 memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
713 memory->mbcState.mbc7.access = state->memory.mbc7.access;
714 memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
715 memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
716 LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
717 LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
718 break;
719 default:
720 break;
721 }
722}
723
724void _pristineCow(struct GB* gb) {
725 if (!gb->isPristine) {
726 return;
727 }
728 void* newRom = anonymousMemoryMap(GB_SIZE_CART_MAX);
729 memcpy(newRom, gb->memory.rom, gb->memory.romSize);
730 memset(((uint8_t*) newRom) + gb->memory.romSize, 0xFF, GB_SIZE_CART_MAX - gb->memory.romSize);
731 if (gb->memory.rom == gb->memory.romBase) {
732 gb->memory.romBase = newRom;
733 }
734 gb->memory.rom = newRom;
735 GBMBCSwitchBank(gb, gb->memory.currentBank);
736 gb->isPristine = false;
737}