src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77 ds->earlyExit = true;
78}
79
80static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
81 UNUSED(timing);
82 UNUSED(cyclesLate);
83 struct DS* ds = context;
84 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
85 int64_t numerator;
86 int64_t denominator;
87 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
88 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
89 bool max = false;
90 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
91 case 0:
92 numerator = (int64_t)(int32_t) numerator;
93 case 1:
94 case 3:
95 denominator = (int64_t)(int32_t) denominator;
96 break;
97 }
98 if (numerator == INT64_MIN) {
99 max = true;
100 }
101 if (!denominator) {
102 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
103 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
104 numerator >>= 63LL;
105 numerator = -numerator;
106 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
107 return;
108 }
109 if (denominator == -1LL && max) {
110 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
111 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
112 return;
113 }
114 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
115 int64_t result = numerator / denominator;
116 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
117 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
118 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
119}
120
121 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
122 UNUSED(timing);
123 UNUSED(cyclesLate);
124 struct DS* ds = context;
125 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
126 uint64_t param;
127 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
128 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
129 param &= 0xFFFFFFFFULL;
130 }
131
132 uint64_t result = 0;
133 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
134
135 // "bit" starts at the highest power of four <= the argument.
136 while (bit > param) {
137 bit >>= 2;
138 }
139
140 while (bit != 0) {
141 if (param >= param + bit) {
142 param -= param + bit;
143 param = (result >> 1) + bit;
144 } else {
145 param >>= 1;
146 }
147 bit >>= 2;
148 }
149 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
150}
151
152void DSCreate(struct DS* ds) {
153 ds->d.id = DS_COMPONENT_MAGIC;
154 ds->d.init = DSInit;
155 ds->d.deinit = NULL;
156 ds->ds7.p = ds;
157 ds->ds9.p = ds;
158 ds->ds7.cpu = NULL;
159 ds->ds9.cpu = NULL;
160 ds->ds7.ipc = &ds->ds9;
161 ds->ds9.ipc = &ds->ds7;
162}
163
164static void DSInit(void* cpu, struct mCPUComponent* component) {
165 struct DS* ds = (struct DS*) component;
166 struct ARMCore* core = cpu;
167 if (!ds->ds7.cpu) {
168 // The ARM7 must get initialized first
169 ds->ds7.cpu = core;
170 ds->debugger = 0;
171 ds->sync = 0;
172 return;
173 }
174 ds->ds9.cpu = cpu;
175 ds->activeCpu = NULL;
176
177 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
178
179 ds->slice.name = "DS CPU Time Slicing";
180 ds->slice.callback = _slice;
181 ds->slice.context = ds;
182 ds->slice.priority = UINT_MAX;
183
184 CircleBufferInit(&ds->ds7.fifo, 64);
185 CircleBufferInit(&ds->ds9.fifo, 64);
186
187 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
188 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
189 DSMemoryInit(ds);
190 DSDMAInit(ds);
191
192 DSVideoInit(&ds->video);
193 ds->video.p = ds;
194
195 ds->ds7.springIRQ = 0;
196 ds->ds9.springIRQ = 0;
197 DSTimerInit(ds);
198 ds->keySource = NULL;
199 ds->rtcSource = NULL;
200 ds->rumble = NULL;
201
202 ds->romVf = NULL;
203
204 ds->keyCallback = NULL;
205
206 ds->divEvent.name = "DS Hardware Divide";
207 ds->divEvent.callback = _divide;
208 ds->divEvent.context = ds;
209 ds->divEvent.priority = 0x50;
210
211 ds->sqrtEvent.name = "DS Hardware Sqrt";
212 ds->sqrtEvent.callback = _sqrt;
213 ds->sqrtEvent.context = ds;
214 ds->sqrtEvent.priority = 0x51;
215
216 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
217 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
218}
219
220void DSUnloadROM(struct DS* ds) {
221 if (ds->romVf) {
222 ds->romVf->close(ds->romVf);
223 ds->romVf = NULL;
224 }
225}
226
227void DSDestroy(struct DS* ds) {
228 CircleBufferDeinit(&ds->ds7.fifo);
229 CircleBufferDeinit(&ds->ds9.fifo);
230 DSUnloadROM(ds);
231 DSMemoryDeinit(ds);
232 mTimingDeinit(&ds->ds7.timing);
233 mTimingDeinit(&ds->ds9.timing);
234}
235
236void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
237 irqh->reset = DS7Reset;
238 irqh->processEvents = DS7ProcessEvents;
239 irqh->swi16 = DS7Swi16;
240 irqh->swi32 = DS7Swi32;
241 irqh->hitIllegal = DSIllegal;
242 irqh->readCPSR = DS7TestIRQ;
243 irqh->writeCP15 = NULL;
244 irqh->readCP15 = NULL;
245 irqh->hitStub = DSHitStub;
246 irqh->bkpt16 = DSBreakpoint;
247 irqh->bkpt32 = DSBreakpoint;
248}
249
250void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
251 irqh->reset = DS9Reset;
252 irqh->processEvents = DS9ProcessEvents;
253 irqh->swi16 = DS9Swi16;
254 irqh->swi32 = DS9Swi32;
255 irqh->hitIllegal = DSIllegal;
256 irqh->readCPSR = DS9TestIRQ;
257 irqh->writeCP15 = DS9WriteCP15;
258 irqh->readCP15 = DS9ReadCP15;
259 irqh->hitStub = DSHitStub;
260 irqh->bkpt16 = DSBreakpoint;
261 irqh->bkpt32 = DSBreakpoint;
262}
263
264void DS7Reset(struct ARMCore* cpu) {
265 ARMSetPrivilegeMode(cpu, MODE_IRQ);
266 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
267 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
268 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
269 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
270 cpu->gprs[ARM_SP] = DS7_SP_BASE;
271
272 struct DS* ds = (struct DS*) cpu->master;
273 mTimingClear(&ds->ds7.timing);
274 CircleBufferInit(&ds->ds7.fifo, 64);
275 DSMemoryReset(ds);
276 DSDMAReset(&ds->ds7);
277 DS7IOInit(ds);
278
279 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
280 if (header) {
281 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
282 // TODO: Error check
283 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
284 uint32_t base = header->arm7Base - DS_BASE_RAM;
285 uint32_t* basePointer = &ds->memory.ram[base >> 2];
286 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
287 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
288 }
289 cpu->gprs[12] = header->arm7Entry;
290 cpu->gprs[ARM_LR] = header->arm7Entry;
291 cpu->gprs[ARM_PC] = header->arm7Entry;
292 int currentCycles = 0;
293 ARM_WRITE_PC;
294
295 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
296 }
297}
298
299void DS9Reset(struct ARMCore* cpu) {
300 ARMSetPrivilegeMode(cpu, MODE_IRQ);
301 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
302 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
303 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
304 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
305 cpu->gprs[ARM_SP] = DS9_SP_BASE;
306
307 struct DS* ds = (struct DS*) cpu->master;
308 mTimingClear(&ds->ds9.timing);
309 CircleBufferInit(&ds->ds9.fifo, 64);
310 DSVideoReset(&ds->video);
311 DSDMAReset(&ds->ds9);
312 DS9IOInit(ds);
313
314 ds->activeCpu = cpu;
315 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
316 ds->cycleDrift = 0;
317 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
318
319 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
320 if (header) {
321 // TODO: Error check
322 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
323 uint32_t base = header->arm9Base - DS_BASE_RAM;
324 uint32_t* basePointer = &ds->memory.ram[base >> 2];
325 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
326 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
327 }
328 cpu->gprs[12] = header->arm9Entry;
329 cpu->gprs[ARM_LR] = header->arm9Entry;
330 cpu->gprs[ARM_PC] = header->arm9Entry;
331 int currentCycles = 0;
332 ARM_WRITE_PC;
333
334 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
335 }
336}
337
338static void DS7ProcessEvents(struct ARMCore* cpu) {
339 struct DS* ds = (struct DS*) cpu->master;
340 DSProcessEvents(&ds->ds7);
341}
342
343static void DS9ProcessEvents(struct ARMCore* cpu) {
344 struct DS* ds = (struct DS*) cpu->master;
345 DSProcessEvents(&ds->ds9);
346}
347
348static void DSProcessEvents(struct DSCommon* dscore) {
349 struct ARMCore* cpu = dscore->cpu;
350 struct DS* ds = dscore->p;
351 if (dscore->springIRQ && !cpu->cpsr.i) {
352 ARMRaiseIRQ(cpu);
353 dscore->springIRQ = 0;
354 }
355
356 int32_t nextEvent = cpu->nextEvent;
357 while (cpu->cycles >= nextEvent) {
358 int32_t cycles = cpu->cycles;
359
360 cpu->cycles = 0;
361 cpu->nextEvent = INT_MAX;
362
363#ifndef NDEBUG
364 if (cycles < 0) {
365 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
366 }
367#endif
368 nextEvent = cycles;
369 do {
370 nextEvent = mTimingTick(&dscore->timing, nextEvent);
371 } while (ds->cpuBlocked);
372
373 cpu->nextEvent = nextEvent;
374
375 if (ds->earlyExit) {
376 ds->earlyExit = false;
377 break;
378 }
379 if (cpu->halted) {
380 cpu->cycles = nextEvent;
381 }
382#ifndef NDEBUG
383 else if (nextEvent < 0) {
384 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
385 }
386#endif
387 }
388}
389
390void DSRunLoop(struct DS* ds) {
391 if (ds->activeCpu == ds->ds9.cpu) {
392 ARMv5RunLoop(ds->ds9.cpu);
393 } else {
394 ARMv4RunLoop(ds->ds7.cpu);
395 }
396}
397
398void DS7Step(struct DS* ds) {
399 while (ds->activeCpu == ds->ds9.cpu) {
400 ARMv5RunLoop(ds->ds9.cpu);
401 }
402 ARMv4Run(ds->ds7.cpu);
403}
404
405void DS9Step(struct DS* ds) {
406 while (ds->activeCpu == ds->ds7.cpu) {
407 ARMv4RunLoop(ds->ds7.cpu);
408 }
409 ARMv5Run(ds->ds9.cpu);
410}
411
412void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
413 ds->debugger = (struct ARMDebugger*) debugger->platform;
414 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
415 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
416 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
417 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
418}
419
420void DSDetachDebugger(struct DS* ds) {
421 ds->debugger = NULL;
422 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
423 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
424 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
425 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
426}
427
428bool DSLoadROM(struct DS* ds, struct VFile* vf) {
429 DSUnloadROM(ds);
430 ds->romVf = vf;
431 // TODO: error check
432 return true;
433}
434
435bool DSIsROM(struct VFile* vf) {
436 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
437 return false;
438 }
439 uint8_t signature[sizeof(DS_ROM_MAGIC)];
440 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
441 return false;
442 }
443 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
444}
445
446bool DSIsBIOS7(struct VFile* vf) {
447 size_t size = vf->size(vf);
448 void* data = NULL;
449 uint32_t crc;
450 if (size == DS7_SIZE_BIOS) {
451 data = vf->map(vf, size, MAP_READ);
452 }
453 if (!data) {
454 return false;
455 }
456 crc = doCrc32(data, size);
457 vf->unmap(vf, data, size);
458 return crc == DS7_BIOS_CHECKSUM;
459}
460
461bool DSIsBIOS9(struct VFile* vf) {
462 size_t size = vf->size(vf);
463 void* data = NULL;
464 uint32_t crc;
465 if (size == DS9_SIZE_BIOS) {
466 data = vf->map(vf, 0x1000, MAP_READ);
467 } else if (size == 0x1000) {
468 data = vf->map(vf, 0x1000, MAP_READ);
469 }
470 if (!data) {
471 return false;
472 }
473 crc = doCrc32(data, 0x1000);
474 vf->unmap(vf, data, 0x1000);
475 return crc == DS9_BIOS_CHECKSUM;
476}
477
478bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
479 size_t size = vf->size(vf);
480 void* data = NULL;
481 uint32_t crc;
482 if (size == DS7_SIZE_BIOS) {
483 data = vf->map(vf, size, MAP_READ);
484 } else if (size == 0x1000) {
485 data = calloc(DS9_SIZE_BIOS, 1);
486 vf->read(vf, data, size);
487 } else if (size == DS9_SIZE_BIOS) {
488 data = vf->map(vf, size, MAP_READ);
489 }
490 if (!data) {
491 return false;
492 }
493 crc = doCrc32(data, size);
494 if (crc == DS7_BIOS_CHECKSUM) {
495 ds->bios7Vf = vf;
496 ds->memory.bios7 = data;
497 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
498 } else if (crc == DS9_BIOS_CHECKSUM) {
499 ds->bios9Vf = vf;
500 ds->memory.bios9 = data;
501 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
502 } else {
503 mLOG(DS, WARN, "BIOS checksum incorrect");
504 vf->unmap(vf, data, size);
505 return false;
506 }
507 return true;
508}
509
510void DSGetGameCode(struct DS* ds, char* out) {
511 memset(out, 0, 8);
512 if (!ds->romVf) {
513 return;
514 }
515
516 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
517 // TODO: TWL-?
518 memcpy(out, "NTR-", 4);
519 memcpy(&out[4], &cart->id, 4);
520 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
521}
522
523void DSGetGameTitle(struct DS* ds, char* out) {
524 memset(out, 0, 12);
525 if (!ds->romVf) {
526 return;
527 }
528
529 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
530 memcpy(out, &cart->title, 12);
531 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
532}
533
534void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
535 struct DS* ds = (struct DS*) cpu->master;
536 if (ds->debugger) {
537 struct mDebuggerEntryInfo info = {
538 .address = _ARMPCAddress(cpu),
539 .opcode = opcode
540 };
541 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
542 }
543 // TODO: More sensible category?
544 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
545}
546
547void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
548 struct DS* ds = (struct DS*) cpu->master;
549 if (ds->debugger) {
550 struct mDebuggerEntryInfo info = {
551 .address = _ARMPCAddress(cpu),
552 .opcode = opcode
553 };
554 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
555 } else {
556 ARMRaiseUndefined(cpu);
557 }
558}
559
560void DSBreakpoint(struct ARMCore* cpu, int immediate) {
561 struct DS* ds = (struct DS*) cpu->master;
562 if (immediate >= CPU_COMPONENT_MAX) {
563 return;
564 }
565 switch (immediate) {
566 case CPU_COMPONENT_DEBUGGER:
567 if (ds->debugger) {
568 struct mDebuggerEntryInfo info = {
569 .address = _ARMPCAddress(cpu)
570 };
571 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
572 }
573 break;
574 default:
575 break;
576 }
577}
578
579void DS7TestIRQ(struct ARMCore* cpu) {
580 struct DS* ds = (struct DS*) cpu->master;
581 if (!ds->memory.io7[DS_REG_IME >> 1]) {
582 return;
583 }
584 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
585 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
586 if (test) {
587 ds->ds7.springIRQ = test;
588 cpu->nextEvent = cpu->cycles;
589 }
590}
591
592void DS9TestIRQ(struct ARMCore* cpu) {
593 struct DS* ds = (struct DS*) cpu->master;
594 if (!ds->memory.io9[DS_REG_IME >> 1]) {
595 return;
596 }
597 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
598 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
599 if (test) {
600 ds->ds9.springIRQ = test;
601 cpu->nextEvent = cpu->cycles;
602 }
603}
604
605static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
606 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
607}
608
609static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
610 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
611 switch (opcode2) {
612 case 0:
613 cpu->cp15.r2.d = value;
614 break;
615 case 1:
616 cpu->cp15.r2.i = value;
617 break;
618 default:
619 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
620 break;
621 }
622}
623
624static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
625 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
626 switch (opcode2) {
627 case 0:
628 cpu->cp15.r3.d = value;
629 break;
630 default:
631 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
632 break;
633 }
634}
635
636static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
637 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
638}
639
640static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
641 cpu->cp15.r6.region[crm] = value;
642 uint32_t base = ARMProtectionGetBase(value) << 12;
643 uint32_t size = 2 << ARMProtectionGetSize(value);
644 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
645}
646
647static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
648 switch (crm) {
649 case 0:
650 if (opcode2 == 4) {
651 ARMHalt(cpu);
652 return;
653 }
654 break;
655 }
656 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
657}
658
659static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
660 uint32_t base = ARMTCMControlGetBase(value) << 12;
661 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
662 struct DS* ds = (struct DS*) cpu->master;
663 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
664 switch (opcode2) {
665 case 0:
666 cpu->cp15.r9.d = value;
667 ds->memory.dtcmBase = base;
668 ds->memory.dtcmSize = size;
669 break;
670 case 1:
671 cpu->cp15.r9.i = value;
672 ds->memory.itcmSize = size;
673 break;
674 default:
675 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
676 break;
677 }
678}
679
680void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
681 switch (crn) {
682 default:
683 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
684 break;
685 case 0:
686 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
687 ARMRaiseUndefined(cpu);
688 break;
689 case 1:
690 _writeSysControl(cpu, crm, opcode2, value);
691 break;
692 case 2:
693 _writeCacheControl(cpu, crm, opcode2, value);
694 break;
695 case 3:
696 _writeWriteBufferControl(cpu, crm, opcode2, value);
697 break;
698 case 5:
699 _writeAccessControl(cpu, crm, opcode2, value);
700 break;
701 case 6:
702 _writeRegionConfiguration(cpu, crm, opcode2, value);
703 break;
704 case 7:
705 _writeCache(cpu, crm, opcode2, value);
706 break;
707 case 9:
708 _writeTCMControl(cpu, crm, opcode2, value);
709 break;
710 }
711}
712
713static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
714 switch (opcode2) {
715 case 0:
716 return cpu->cp15.r9.d;
717 case 1:
718 return cpu->cp15.r9.i;
719 default:
720 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
721 return 0;
722 }
723}
724
725uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
726 switch (crn) {
727 default:
728 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
729 return 0;
730 case 9:
731 return _readTCMControl(cpu, crm, opcode2);
732 }
733}
734
735void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
736 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
737 ARMRaiseIRQ(cpu);
738 }
739}
740void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
741 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
742 ARMRaiseIRQ(cpu);
743 }
744}
745
746void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
747 if (irq < 16) {
748 io[DS_REG_IF_LO >> 1] |= 1 << irq;
749 } else {
750 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
751 }
752
753 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
754 cpu->halted = 0;
755 if (io[DS_REG_IME >> 1]) {
756 ARMRaiseIRQ(cpu);
757 }
758 }
759}
760
761void DSFrameStarted(struct DS* ds) {
762 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
763 if (callbacks && callbacks->videoFrameStarted) {
764 callbacks->videoFrameStarted(callbacks->context);
765 }
766}
767
768void DSFrameEnded(struct DS* ds) {
769 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
770 if (callbacks && callbacks->videoFrameEnded) {
771 callbacks->videoFrameEnded(callbacks->context);
772 }
773}