1/* Copyright (c) 2013-2015 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GBA_MEMORY_H
  7#define GBA_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm.h"
 12#include "macros.h"
 13
 14#include "gba/hardware.h"
 15#include "gba/savedata.h"
 16
 17enum GBAMemoryRegion {
 18	REGION_BIOS = 0x0,
 19	REGION_WORKING_RAM = 0x2,
 20	REGION_WORKING_IRAM = 0x3,
 21	REGION_IO = 0x4,
 22	REGION_PALETTE_RAM = 0x5,
 23	REGION_VRAM = 0x6,
 24	REGION_OAM = 0x7,
 25	REGION_CART0 = 0x8,
 26	REGION_CART0_EX = 0x9,
 27	REGION_CART1 = 0xA,
 28	REGION_CART1_EX = 0xB,
 29	REGION_CART2 = 0xC,
 30	REGION_CART2_EX = 0xD,
 31	REGION_CART_SRAM = 0xE,
 32	REGION_CART_SRAM_MIRROR = 0xF
 33};
 34
 35enum GBAMemoryBase {
 36	BASE_BIOS = 0x00000000,
 37	BASE_WORKING_RAM = 0x02000000,
 38	BASE_WORKING_IRAM = 0x03000000,
 39	BASE_IO = 0x04000000,
 40	BASE_PALETTE_RAM = 0x05000000,
 41	BASE_VRAM = 0x06000000,
 42	BASE_OAM = 0x07000000,
 43	BASE_CART0 = 0x08000000,
 44	BASE_CART0_EX = 0x09000000,
 45	BASE_CART1 = 0x0A000000,
 46	BASE_CART1_EX = 0x0B000000,
 47	BASE_CART2 = 0x0C000000,
 48	BASE_CART2_EX = 0x0D000000,
 49	BASE_CART_SRAM = 0x0E000000,
 50	BASE_CART_SRAM_MIRROR = 0x0F000000
 51};
 52
 53enum {
 54	SIZE_BIOS = 0x00004000,
 55	SIZE_WORKING_RAM = 0x00040000,
 56	SIZE_WORKING_IRAM = 0x00008000,
 57	SIZE_IO = 0x00000400,
 58	SIZE_PALETTE_RAM = 0x00000400,
 59	SIZE_VRAM = 0x00018000,
 60	SIZE_OAM = 0x00000400,
 61	SIZE_CART0 = 0x02000000,
 62	SIZE_CART1 = 0x02000000,
 63	SIZE_CART2 = 0x02000000,
 64	SIZE_CART_SRAM = 0x00010000,
 65	SIZE_CART_FLASH512 = 0x00010000,
 66	SIZE_CART_FLASH1M = 0x00020000,
 67	SIZE_CART_EEPROM = 0x00002000
 68};
 69
 70enum {
 71	OFFSET_MASK = 0x00FFFFFF,
 72	BASE_OFFSET = 24
 73};
 74
 75enum DMAControl {
 76	DMA_INCREMENT = 0,
 77	DMA_DECREMENT = 1,
 78	DMA_FIXED = 2,
 79	DMA_INCREMENT_RELOAD = 3
 80};
 81
 82enum DMATiming {
 83	DMA_TIMING_NOW = 0,
 84	DMA_TIMING_VBLANK = 1,
 85	DMA_TIMING_HBLANK = 2,
 86	DMA_TIMING_CUSTOM = 3
 87};
 88
 89
 90DECL_BITFIELD(GBADMARegister, uint16_t);
 91DECL_BITS(GBADMARegister, DestControl, 5, 2);
 92DECL_BITS(GBADMARegister, SrcControl, 7, 2);
 93DECL_BIT(GBADMARegister, Repeat, 9);
 94DECL_BIT(GBADMARegister, Width, 10);
 95DECL_BIT(GBADMARegister, DRQ, 11);
 96DECL_BITS(GBADMARegister, Timing, 12, 2);
 97DECL_BIT(GBADMARegister, DoIRQ, 14);
 98DECL_BIT(GBADMARegister, Enable, 15);
 99
100struct GBADMA {
101	GBADMARegister reg;
102
103	uint32_t source;
104	uint32_t dest;
105	int32_t count;
106	uint32_t nextSource;
107	uint32_t nextDest;
108	int32_t nextCount;
109	int32_t nextEvent;
110};
111
112struct GBAMemory {
113	uint32_t* bios;
114	uint32_t* wram;
115	uint32_t* iwram;
116	uint32_t* rom;
117	uint16_t io[SIZE_IO >> 1];
118
119	struct GBACartridgeHardware hw;
120	struct GBASavedata savedata;
121	size_t romSize;
122	uint16_t romID;
123	int fullBios;
124
125	char waitstatesSeq32[256];
126	char waitstatesSeq16[256];
127	char waitstatesNonseq32[256];
128	char waitstatesNonseq16[256];
129	char waitstatesPrefetchSeq32[16];
130	char waitstatesPrefetchSeq16[16];
131	char waitstatesPrefetchNonseq32[16];
132	char waitstatesPrefetchNonseq16[16];
133	int activeRegion;
134	bool prefetch;
135	uint32_t biosPrefetch;
136
137	struct GBADMA dma[4];
138	int activeDMA;
139	int32_t nextDMA;
140	int32_t eventDiff;
141};
142
143void GBAMemoryInit(struct GBA* gba);
144void GBAMemoryDeinit(struct GBA* gba);
145
146void GBAMemoryReset(struct GBA* gba);
147
148uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
149uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
150uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
151
152void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
153void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
154void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
155
156void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old);
157void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old);
158void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old);
159
160uint32_t GBALoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction, int* cycleCounter);
161uint32_t GBAStoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction, int* cycleCounter);
162
163void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters);
164
165void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address);
166void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address);
167void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count);
168uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control);
169
170void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info);
171void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles);
172void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles);
173void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles);
174int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles);
175
176struct GBASerializedState;
177void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state);
178void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state);
179
180#endif