include/mgba/internal/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/core.h>
14#include <mgba/internal/gb/gb.h>
15
16extern const uint32_t GB_SAVESTATE_MAGIC;
17extern const uint32_t GB_SAVESTATE_VERSION;
18
19mLOG_DECLARE_CATEGORY(GB_STATE);
20
21/* Savestate format:
22 * 0x00000 - 0x00003: Version Magic (0x01000002)
23 * 0x00004 - 0x00007: ROM CRC32
24 * 0x00008: Game Boy model
25 * 0x00009 - 0x0000B: Reserved (leave zero)
26 * 0x0000C - 0x0000F: Master cycles
27 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
28 * 0x00020 - 0x00047: CPU state:
29 * | 0x00020: A register
30 * | 0x00021: F register
31 * | 0x00022: B register
32 * | 0x00023: C register
33 * | 0x00024: D register
34 * | 0x00025: E register
35 * | 0x00026: H register
36 * | 0x00027: L register
37 * | 0x00028 - 0x00029: SP register
38 * | 0x0002A - 0x0002B: PC register
39 * | 0x0002C - 0x0002F: Cycles since last event
40 * | 0x00030 - 0x00033: Cycles until next event
41 * | 0x00034 - 0x00035: Reserved (current instruction)
42 * | 0x00036 - 0x00037: Index address
43 * | 0x00038: Bus value
44 * | 0x00039: Execution state
45 * | 0x0003A - 0x0003B: IRQ vector
46 * | 0x0003C - 0x0003F: EI pending cycles
47 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
48 * | 0x00044 - 0x00047: Flags
49 * | bit 0: Is condition met?
50 * | bit 1: Is condition IRQ pending?
51 * | bit 2: Double speed
52 * | bit 3: Is EI pending?
53 * | bits 4 - 31: Reserved
54 * 0x00048 - 0x0005B: Audio channel 1/framer state
55 * | 0x00048 - 0x0004B: Envelepe timing
56 * | bits 0 - 6: Remaining length
57 * | bits 7 - 9: Next step
58 * | bits 10 - 20: Shadow frequency register
59 * | bits 21 - 31: Reserved
60 * | 0x0004C - 0x0004F: Next frame
61 * | 0x00050 - 0x00053: Next channel 3 fade
62 * | 0x00054 - 0x00057: Reserved
63 * | 0x00058 - 0x0005B: Next event
64 * 0x0005C - 0x0006B: Audio channel 2 state
65 * | 0x0005C - 0x0005F: Envelepe timing
66 * | bits 0 - 2: Remaining length
67 * | bits 3 - 5: Next step
68 * | bits 6 - 31: Reserved
69 * | 0x00060 - 0x00067: Reserved
70 * | 0x00068 - 0x0006B: Next event
71 * 0x0006C - 0x00093: Audio channel 3 state
72 * | 0x0006C - 0x0008B: Wave banks
73 * | 0x0008C - 0x0008D: Remaining length
74 * | 0x0008E - 0x0008F: Reserved
75 * | 0x00090 - 0x00093: Next event
76 * 0x00094 - 0x000A3: Audio channel 4 state
77 * | 0x00094 - 0x00097: Linear feedback shift register state
78 * | 0x00098 - 0x0009B: Envelepe timing
79 * | bits 0 - 2: Remaining length
80 * | bits 3 - 5: Next step
81 * | bits 6 - 31: Reserved
82 * | 0x00098 - 0x0009F: Reserved
83 * | 0x000A0 - 0x000A3: Next event
84 * 0x000A4 - 0x000B7: Audio miscellaneous state
85 * | TODO: Fix this, they're in big-endian order, but field is little-endian
86 * | 0x000A4: Channel 1 envelope state
87 * | bits 0 - 3: Current volume
88 * | bits 4 - 5: Is dead?
89 * | bit 6: Is high?
90 * | 0x000A5: Channel 2 envelope state
91 * | bits 0 - 3: Current volume
92 * | bits 4 - 5: Is dead?
93 * | bit 6: Is high?
94* | bits 7: Reserved
95 * | 0x000A6: Channel 4 envelope state
96 * | bits 0 - 3: Current volume
97 * | bits 4 - 5: Is dead?
98 * | bit 6: Is high?
99* | bits 7: Reserved
100 * | 0x000A7: Miscellaneous audio flags
101 * | bits 0 - 3: Current frame
102 * | bit 4: Is channel 1 sweep enabled?
103 * | bit 5: Has channel 1 sweep occurred?
104 * | bit 6: Is channel 3's memory readable?
105 * | bit 7: Reserved
106 * | 0x000A8 - 0x000AF: Rserved
107 * | 0x000B0 - 0x000B3: Next sample
108 * 0x000B4 - 0x000153: Video state
109 * | 0x000B4 - 0x000B5: Current x
110 * | 0x000B6 - 0x000B7: Current y (ly)
111 * | 0x000B8 - 0x000BB: Next frame
112 * | 0x000BC - 0x000BF: Reserved
113 * | 0x000C0 - 0x000C3: Next mode
114 * | 0x000C4 - 0x000C7: Dot cycle counter
115 * | 0x000C8 - 0x000CB: Frame counter
116 * | 0x000CC: Current VRAM bank
117 * | 0x000CD: Palette flags
118 * | bit 0: BCP increment
119 * | bit 1: OCP increment
120 * | bits 2 - 3: Mode
121 * | bits 4 - 7: Reserved
122 * | 0x000CE - 0x000CF: Reserved
123 * | 0x000D0 - 0x000D1: BCP index
124 * | 0x000D1 - 0x000D3: OCP index
125 * | 0x000D4 - 0x00153: Palette entries
126 * 0x00154 - 0x000167: Timer state
127 * | 0x00154 - 0x00157: Next event
128 * | 0x00158 - 0x0015B: Next IRQ
129 * | 0x0015C - 0x0015F: Next DIV
130 * | 0x00160 - 0x00163: Inernal DIV
131 * | 0x00164: TIMA period
132 * | 0x00165: Flags
133 * | bit 0: Is IRQ pending?
134 * | 0x00166 - 0x00167: Reserved
135 * 0x000168 - 0x000197: Memory state
136 * | 0x00168 - 0x00169: Current ROM bank
137 * | 0x0016A: Current WRAM bank
138 * | 0x0016B: Current SRAM bank
139 * | 0x0016C - 0x0016F: Next DMA
140 * | 0x00170 - 0x00171: Next DMA source
141 * | 0x00172 - 0x00173: Next DMA destination
142 * | 0x00174 - 0x00177: Next HDMA
143 * | 0x00178 - 0x00179: Next HDMA source
144 * | 0x0017A - 0x0017B: Next HDMA destination
145 * | 0x0017C - 0x0017D: HDMA remaining
146 * | 0x0017E: DMA remaining
147 * | 0x0017F - 0x00183: RTC registers
148 * | 0x00184 - 0x00193: MBC state
149 * | 0x00194 - 0x00195: Flags
150 * | bit 0: SRAM accessable
151 * | bit 1: RTC accessible
152 * | bit 2: RTC latched
153 * | bit 3: IME
154 * | bit 4: Is HDMA active?
155 * | bits 5 - 7: Active RTC register
156 * | 0x00196 - 0x00197: Reserved (leave zero)
157 * 0x00198 - 0x0025F: Reserved (leave zero)
158 * 0x00260 - 0x002FF: OAM
159 * 0x00300 - 0x0037F: I/O memory
160 * 0x00380 - 0x003FE: HRAM
161 * 0x003FF: Interrupts enabled
162 * 0x00400 - 0x043FF: VRAM
163 * 0x04400 - 0x0C3FF: WRAM
164 * 0x0C400 - 0x0C77F: Reserved
165 * 0x0C780 - 0x117FF: Super Game Boy
166 * | 0x0C780 - 0x0C7D9: Current attributes
167 * | 0x0C7DA: Current command
168 * | 0x0C7DB: Current bit count
169 * | 0x0C7DC - 0x0C7DF: Flags
170 * | bits 0 - 1: Current P1 bits
171 * | bits 2 - 3: Current render mode
172 * | bits 4 - 31: Reserved (leave 0)
173 * | 0x0C7E0 - 0x0C7EF: Current packet
174 * | 0x0C7F0 - 0x0C7FF: Reserved
175 * | 0x0C800 - 0x0E7FF: Character VRAM
176 * | 0x0E800 - 0x0F7FF: Tile map VRAM
177 * | 0x0F800 - 0x107FF: Palette VRAM
178 * | 0x10800 - 0x117FF: Attribute file
179 * Total size: 0x11800 (71,680) bytes
180*/
181
182DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
183DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
184DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
185DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
186DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
187DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
188DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
189DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
190DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
191DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
192DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
193DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
194DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
195
196DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
197DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
198DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
199DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
200
201struct GBSerializedPSGState {
202 struct {
203 GBSerializedAudioEnvelope envelope;
204 int32_t nextFrame;
205 int32_t nextCh3Fade;
206 int32_t reserved;
207 uint32_t nextEvent;
208 } ch1;
209 struct {
210 GBSerializedAudioEnvelope envelope;
211 int32_t reserved[2];
212 int32_t nextEvent;
213 } ch2;
214 struct {
215 uint32_t wavebanks[8];
216 int16_t length;
217 int16_t reserved;
218 uint32_t nextEvent;
219 } ch3;
220 struct {
221 int32_t lfsr;
222 GBSerializedAudioEnvelope envelope;
223 int32_t reserved;
224 uint32_t nextEvent;
225 } ch4;
226};
227
228DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
229DECL_BIT(GBSerializedCpuFlags, Condition, 0);
230DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
231DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
232DECL_BIT(GBSerializedCpuFlags, EiPending, 1);
233
234DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
235DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
236
237DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
238DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
239DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
240DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
241DECL_BIT(GBSerializedVideoFlags, NotModeEventScheduled, 4);
242DECL_BIT(GBSerializedVideoFlags, NotFrameEventScheduled, 5);
243
244DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
245DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
246DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
247
248DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
249DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
250DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
251DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
252DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
253DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
254DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
255
256DECL_BITFIELD(GBSerializedSGBFlags, uint32_t);
257DECL_BITS(GBSerializedSGBFlags, P1Bits, 0, 2);
258DECL_BITS(GBSerializedSGBFlags, RenderMode, 2, 2);
259
260#pragma pack(push, 1)
261struct GBSerializedState {
262 uint32_t versionMagic;
263 uint32_t romCrc32;
264 uint8_t model;
265 uint8_t reservedHeader[3];
266 uint32_t masterCycles;
267
268 char title[16];
269
270 struct {
271 uint8_t a;
272 uint8_t f;
273 uint8_t b;
274 uint8_t c;
275 uint8_t d;
276 uint8_t e;
277 uint8_t h;
278 uint8_t l;
279 uint16_t sp;
280 uint16_t pc;
281
282 int32_t cycles;
283 int32_t nextEvent;
284
285 uint16_t reservedInstruction;
286 uint16_t index;
287 uint8_t bus;
288 uint8_t executionState;
289
290 uint16_t irqVector;
291
292 uint32_t eiPending;
293 int32_t reservedDiPending;
294 GBSerializedCpuFlags flags;
295 } cpu;
296
297 struct {
298 struct GBSerializedPSGState psg;
299 GBSerializedAudioFlags flags;
300 int32_t reserved[2];
301 uint32_t nextSample;
302 } audio;
303
304 struct {
305 int16_t x;
306 int16_t ly;
307 uint32_t nextFrame;
308 uint32_t reserved;
309 uint32_t nextMode;
310 int32_t dotCounter;
311 int32_t frameCounter;
312
313 uint8_t vramCurrentBank;
314 GBSerializedVideoFlags flags;
315 uint16_t reserved2;
316
317 uint16_t bcpIndex;
318 uint16_t ocpIndex;
319
320 uint16_t palette[64];
321 } video;
322
323 struct {
324 uint32_t nextEvent;
325 uint32_t nextIRQ;
326
327 uint32_t nextDiv;
328 uint32_t internalDiv;
329 uint8_t timaPeriod;
330 GBSerializedTimerFlags flags;
331 uint16_t reserved;
332 } timer;
333
334 struct {
335 uint16_t currentBank;
336 uint8_t wramCurrentBank;
337 uint8_t sramCurrentBank;
338
339 uint32_t dmaNext;
340 uint16_t dmaSource;
341 uint16_t dmaDest;
342
343 uint32_t hdmaNext;
344 uint16_t hdmaSource;
345 uint16_t hdmaDest;
346
347 uint16_t hdmaRemaining;
348 uint8_t dmaRemaining;
349 uint8_t rtcRegs[5];
350
351 union {
352 struct {
353 uint8_t mode;
354 uint8_t multicartStride;
355 } mbc1;
356 struct {
357 uint64_t lastLatch;
358 } rtc;
359 struct {
360 uint8_t state;
361 GBMBC7Field eeprom;
362 uint8_t address;
363 uint8_t access;
364 uint8_t latch;
365 uint8_t srBits;
366 uint16_t sr;
367 uint32_t writable;
368 } mbc7;
369 struct {
370 uint8_t reserved[16];
371 } padding;
372 };
373
374 GBSerializedMemoryFlags flags;
375 uint16_t reserved;
376 } memory;
377
378 uint32_t reserved[50];
379
380 uint8_t oam[GB_SIZE_OAM];
381
382 uint8_t io[GB_SIZE_IO];
383 uint8_t hram[GB_SIZE_HRAM];
384 uint8_t ie;
385
386 uint8_t vram[GB_SIZE_VRAM];
387 uint8_t wram[GB_SIZE_WORKING_RAM];
388
389 uint32_t reserved2[0xE0];
390
391 struct {
392 uint8_t attributes[90];
393 uint8_t command;
394 uint8_t bits;
395 GBSerializedSGBFlags flags;
396 uint8_t packet[16];
397 uint32_t reserved[4];
398 uint8_t charRam[SGB_SIZE_CHAR_RAM];
399 uint8_t mapRam[SGB_SIZE_MAP_RAM];
400 uint8_t palRam[SGB_SIZE_PAL_RAM];
401 uint8_t atfRam[SGB_SIZE_ATF_RAM];
402 } sgb;
403};
404#pragma pack(pop)
405
406bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
407void GBSerialize(struct GB* gb, struct GBSerializedState* state);
408
409CXX_GUARD_END
410
411#endif