src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 ARM_STUB;
28}
29
30static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
31 int rm = opcode & 0x0000000F;
32 int immediate = (opcode & 0x00000F80) >> 7;
33 if (immediate) {
34 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
35 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
39 }
40}
41
42static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
43 int rm = opcode & 0x0000000F;
44 ARM_STUB;
45}
46
47static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
48 int rm = opcode & 0x0000000F;
49 int immediate = (opcode & 0x00000F80) >> 7;
50 if (immediate) {
51 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
52 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
53 } else {
54 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
55 cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
56 }
57}
58
59static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
60 int rm = opcode & 0x0000000F;
61 ARM_STUB;
62}
63
64static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int immediate = (opcode & 0x00000F80) >> 7;
67 ARM_STUB;
68}
69
70static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
71 int rm = opcode & 0x0000000F;
72 ARM_STUB;
73}
74
75static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
76 int rotate = (opcode & 0x00000F00) >> 7;
77 int immediate = opcode & 0x000000FF;
78 if (!rotate) {
79 cpu->shifterOperand = immediate;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else {
82 cpu->shifterOperand = ARM_ROR(immediate, rotate);
83 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
84 }
85}
86
87static const ARMInstruction _armTable[0x1000];
88
89static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
90 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
91 *opcodeOut = opcode;
92 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
93}
94
95void ARMStep(struct ARMCore* cpu) {
96 // TODO
97 uint32_t opcode;
98 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
99 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
100
101 int condition = opcode >> 28;
102 if (condition == 0xE) {
103 instruction(cpu, opcode);
104 return;
105 } else {
106 switch (condition) {
107 case 0x0:
108 if (!ARM_COND_EQ) {
109 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
110 return;
111 }
112 break;
113 case 0x1:
114 if (!ARM_COND_NE) {
115 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
116 return;
117 }
118 break;
119 case 0x2:
120 if (!ARM_COND_CS) {
121 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
122 return;
123 }
124 break;
125 case 0x3:
126 if (!ARM_COND_CC) {
127 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
128 return;
129 }
130 break;
131 case 0x4:
132 if (!ARM_COND_MI) {
133 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
134 return;
135 }
136 break;
137 case 0x5:
138 if (!ARM_COND_PL) {
139 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
140 return;
141 }
142 break;
143 case 0x6:
144 if (!ARM_COND_VS) {
145 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
146 return;
147 }
148 break;
149 case 0x7:
150 if (!ARM_COND_VC) {
151 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
152 return;
153 }
154 break;
155 case 0x8:
156 if (!ARM_COND_HI) {
157 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
158 return;
159 }
160 break;
161 case 0x9:
162 if (!ARM_COND_LS) {
163 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
164 return;
165 }
166 break;
167 case 0xA:
168 if (!ARM_COND_GE) {
169 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
170 return;
171 }
172 break;
173 case 0xB:
174 if (!ARM_COND_LT) {
175 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
176 return;
177 }
178 break;
179 case 0xC:
180 if (!ARM_COND_GT) {
181 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
182 return;
183 }
184 break;
185 case 0xD:
186 if (!ARM_COND_GE) {
187 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
188 return;
189 }
190 break;
191 default:
192 break;
193 }
194 }
195 instruction(cpu, opcode);
196}
197
198// Instruction definitions
199// Beware pre-processor antics
200
201#define ARM_ADDITION_S(M, N, D) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 cpu->cpsr.n = ARM_SIGN(D); \
207 cpu->cpsr.z = !(D); \
208 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
209 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
210 }
211
212#define ARM_SUBTRACTION_S(M, N, D) \
213 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
214 cpu->cpsr = cpu->spsr; \
215 _ARMReadCPSR(cpu); \
216 } else { \
217 cpu->cpsr.n = ARM_SIGN(D); \
218 cpu->cpsr.z = !(D); \
219 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
220 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
221 }
222
223#define ARM_NEUTRAL_S(M, N, D) \
224 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
225 cpu->cpsr = cpu->spsr; \
226 _ARMReadCPSR(cpu); \
227 } else { \
228 cpu->cpsr.n = ARM_SIGN(D); \
229 cpu->cpsr.z = !(D); \
230 cpu->cpsr.c = cpu->shifterCarryOut; \
231 }
232
233#define ADDR_MODE_2_ADDRESS (address)
234#define ADDR_MODE_2_RN (cpu->gprs[rn])
235#define ADDR_MODE_2_RM (cpu->gprs[rm])
236#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
237#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
238#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
239#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
240#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
241#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
242#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
243
244#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
245#define ADDR_MODE_3_RN ADDR_MODE_2_RN
246#define ADDR_MODE_3_RM ADDR_MODE_2_RM
247#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
248#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
249#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
250
251#define ARM_LOAD_POST_BODY \
252 if (rd == ARM_PC) { \
253 ARM_WRITE_PC; \
254 }
255
256#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
257 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
258 BODY; \
259 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
260 }
261
262#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
263 DEFINE_INSTRUCTION_ARM(NAME, \
264 int rd = (opcode >> 12) & 0xF; \
265 int rn = (opcode >> 16) & 0xF; \
266 UNUSED(rn); \
267 SHIFTER(cpu, opcode); \
268 BODY; \
269 S_BODY; \
270 POST_BODY; \
271 if (rd == ARM_PC) { \
272 ARM_WRITE_PC; \
273 })
274
275#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
276 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
277 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
278 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
294
295#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
305
306#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
307 DEFINE_INSTRUCTION_ARM(NAME, \
308 uint32_t address; \
309 int rn = (opcode >> 16) & 0xF; \
310 int rd = (opcode >> 12) & 0xF; \
311 int rm = opcode & 0xF; \
312 UNUSED(rm); \
313 address = ADDRESS; \
314 BODY; \
315 WRITEBACK;)
316
317#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
318 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
319 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
320 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
321 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
322 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
323 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
324
325#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
326 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
327 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
328 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
329 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
330 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
331 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
332 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
333 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
334 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
335 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
336
337#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
338 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
344 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
345 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
346 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
350
351#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
354
355#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
356 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
357 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
358 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
359 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
362
363#define ARM_MS_PRE \
364 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
365 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
366
367#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
368
369#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
370#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
371#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
372#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
373#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
374#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
375#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
376#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
377
378#define ARM_M_INCREMENT(BODY) \
379 for (m = rs, i = 0; m; m >>= 1, ++i) { \
380 if (m & 1) { \
381 BODY; \
382 addr += 4; \
383 } \
384 }
385
386#define ARM_M_DECREMENT(BODY) \
387 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
388 if (rs & m) { \
389 BODY; \
390 addr -= 4; \
391 } \
392 }
393
394#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
395 DEFINE_INSTRUCTION_ARM(NAME, \
396 int rn = (opcode >> 16) & 0xF; \
397 int rs = opcode & 0x0000FFFF; \
398 int m; \
399 int i; \
400 ADDRESS; \
401 S_PRE; \
402 LOOP(BODY); \
403 S_POST; \
404 WRITEBACK; \
405 POST_BODY;)
406
407
408#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
409 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
410 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
411 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
412 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
419 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
420 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
421 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
422 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
423 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
424 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
425
426// Begin ALU definitions
427
428DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
429 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
430
431DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
432 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
433 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
434
435DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
436 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
437
438DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
439 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
440
441DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
442 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
443
444DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
445 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
446
447DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
448 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
449
450DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
451 cpu->gprs[rd] = cpu->shifterOperand;, )
452
453DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
454 cpu->gprs[rd] = ~cpu->shifterOperand;, )
455
456DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
457 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
458
459DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d),
460 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
461
462DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d),
463 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
464 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
465
466DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d),
467 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
468 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
469
470DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d),
471 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
472
473DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
474 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
475
476DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
477 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
478
479// End ALU definitions
480
481// Begin multiply definitions
482
483DEFINE_INSTRUCTION_ARM(MLA, ARM_STUB)
484DEFINE_INSTRUCTION_ARM(MLAS, ARM_STUB)
485DEFINE_INSTRUCTION_ARM(MUL, ARM_STUB)
486DEFINE_INSTRUCTION_ARM(MULS, ARM_STUB)
487DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
488DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
489DEFINE_INSTRUCTION_ARM(SMULL, ARM_STUB)
490DEFINE_INSTRUCTION_ARM(SMULLS, ARM_STUB)
491DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
492DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
493DEFINE_INSTRUCTION_ARM(UMULL, ARM_STUB)
494DEFINE_INSTRUCTION_ARM(UMULLS, ARM_STUB)
495
496// End multiply definitions
497
498// Begin load/store definitions
499
500DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;)
501DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;)
502DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;)
503DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;)
504DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;)
505DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
506DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
507DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
508
509DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
510 enum PrivilegeMode priv = cpu->privilegeMode;
511 ARMSetPrivilegeMode(cpu, MODE_USER);
512 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
513 ARMSetPrivilegeMode(cpu, priv);
514 ARM_LOAD_POST_BODY;)
515
516DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
517 enum PrivilegeMode priv = cpu->privilegeMode;
518 ARMSetPrivilegeMode(cpu, MODE_USER);
519 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
520 ARMSetPrivilegeMode(cpu, priv);
521 ARM_LOAD_POST_BODY;)
522
523DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
524 enum PrivilegeMode priv = cpu->privilegeMode;
525 ARMSetPrivilegeMode(cpu, MODE_USER);
526 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
527 ARMSetPrivilegeMode(cpu, priv);)
528
529DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
530 enum PrivilegeMode priv = cpu->privilegeMode;
531 ARMSetPrivilegeMode(cpu, MODE_USER);
532 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
533 ARMSetPrivilegeMode(cpu, priv);)
534
535DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
536 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr);,
537 if (rs & 0x8000) {
538 ARM_WRITE_PC;
539 })
540
541DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i]);, )
542
543DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
544DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
545
546// End load/store definitions
547
548// Begin branch definitions
549
550DEFINE_INSTRUCTION_ARM(B,
551 int32_t offset = opcode << 8;
552 offset >>= 6;
553 cpu->gprs[ARM_PC] += offset;
554 ARM_WRITE_PC;)
555
556DEFINE_INSTRUCTION_ARM(BL, ARM_STUB)
557DEFINE_INSTRUCTION_ARM(BX,
558 int rm = opcode & 0x0000000F;
559 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
560 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
561 if (cpu->executionMode == MODE_THUMB) {
562 THUMB_WRITE_PC;
563 } else {
564 ARM_WRITE_PC;
565 })
566
567// End branch definitions
568
569// Begin miscellaneous definitions
570
571DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
572DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
573
574DEFINE_INSTRUCTION_ARM(MSR,
575 int c = opcode & 0x00010000;
576 int f = opcode & 0x00080000;
577 int32_t operand = cpu->gprs[opcode & 0x0000000F];
578 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
579 if (mask & PSR_USER_MASK) {
580 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
581 }
582 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
583 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
584 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
585 })
586
587DEFINE_INSTRUCTION_ARM(MSRR,
588 int c = opcode & 0x00010000;
589 int f = opcode & 0x00080000;
590 int32_t operand = cpu->gprs[opcode & 0x0000000F];
591 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
592 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
593 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
594
595DEFINE_INSTRUCTION_ARM(MRS, \
596 int rd = (opcode >> 12) & 0xF; \
597 cpu->gprs[rd] = cpu->cpsr.packed;)
598
599DEFINE_INSTRUCTION_ARM(MRSR, \
600 int rd = (opcode >> 12) & 0xF; \
601 cpu->gprs[rd] = cpu->spsr.packed;)
602
603DEFINE_INSTRUCTION_ARM(MSRI,
604 int c = opcode & 0x00010000;
605 int f = opcode & 0x00080000;
606 int rotate = (opcode & 0x00000F00) >> 8;
607 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
608 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
609 if (mask & PSR_USER_MASK) {
610 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
611 }
612 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
613 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
614 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
615 })
616
617DEFINE_INSTRUCTION_ARM(MSRRI,
618 int c = opcode & 0x00010000;
619 int f = opcode & 0x00080000;
620 int rotate = (opcode & 0x00000F00) >> 8;
621 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
622 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
623 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
624 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
625
626DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
627
628#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
629 EMITTER ## NAME
630
631#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
632 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
633 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
634
635#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
636 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
637 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
638 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
639 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
640 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
641 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
642 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
643 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
644 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
645 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
646 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
647 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
648 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
649 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
650 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
651 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
652
653#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
654 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
655 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
656
657#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
658 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
659 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
660 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
661 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
662 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
663 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
664 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
665 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
666 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
667 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
668 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
669 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
670 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
671 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
672 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
673 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
674
675#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
676 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
677 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
678
679#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
680 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
681
682// TODO: Support coprocessors
683#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
684 DO_8(0), \
685 DO_8(0)
686
687#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
688 DO_8(DO_8(DO_INTERLACE(0, 0))), \
689 DO_8(DO_8(DO_INTERLACE(0, 0)))
690
691#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
692 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
693
694#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
695 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
696 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
697 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
698 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
699 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
700 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
701 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
702 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
703 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
704 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
705 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
706 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
707 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
708 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
709 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
710 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
711 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
712 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
713 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
714 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
715 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
716 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
717 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
718 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
719 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
720 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
721 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
722 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
723 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
724 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
725 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
726 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
727 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
728 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
729 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
730 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
731 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
732 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
733 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
734 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
735 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
736 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
737 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
738 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
739 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
740 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
741 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
742 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
743 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
744 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
745 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
746 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
747 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
748 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
749 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
750 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
751 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
752 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
753 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
754 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
755 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
756 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
757 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
758 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
759 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
760 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
761 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
762 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
763 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
764 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
765 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
766 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
767 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
768 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
769 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
770 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
771 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
772 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
773 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
774 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
775 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
776 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
777 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
778 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
779 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
780 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
781 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
782 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
783 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
784 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
785 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
786 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
787 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
788 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
789 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
790 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
791 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
792 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
793 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
794 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
795 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
796 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
797 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
798 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
799 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
800 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
801 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
802 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
803 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
804 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
805 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
806 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
807 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
808 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
809 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
810 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
811 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
812 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
813 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
814 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
815 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
816 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
817 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
818 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
819 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
820 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
821 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
822 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
823 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
824 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
825 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
826 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
827 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
828 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
829 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
830 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
831 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
832 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
833 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
834 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
835 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
836 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
837 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
838 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
839 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
840 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
841 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
842 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
843 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
844 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
845 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
846 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
847 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
848 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
849 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
850 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
851 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
852 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
853 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
854 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
855 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
856 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
857 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
858 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
859 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
860 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
861 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
862 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
863 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
864 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
865 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
866 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
867 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
868 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
869 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
870 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
871 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
872 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
873 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
874 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
875 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
876 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
877 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
878 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
879 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
880 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
881 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
882 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
883 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
884 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
885 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
886 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
887 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
888 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
889 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
890 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
891 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
892 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
893 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
894 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
895 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
896 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
897 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
898 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
899 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
900 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
901 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
902 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
903 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
904 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
905 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
906 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
907 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
908 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
909 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
910 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
911 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
912 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
913 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
914 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
915 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
916 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
917 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
918 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
919 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
920 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
921 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
922 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
923 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
924 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
925 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
926 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
927 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
928 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
929 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
930 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
931 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
932 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
933 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
934 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
935 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
936 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
937 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
938 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
939 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
940 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
941 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
942 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
943 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
944 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
945 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
946 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
947 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
948 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
949 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
950 DECLARE_ARM_SWI_BLOCK(EMITTER)
951
952static const ARMInstruction _armTable[0x1000] = {
953 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
954};