src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39static void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value);
40static void _GBBBD(struct GB* gb, uint16_t address, uint8_t value);
41static void _GBHitek(struct GB* gb, uint16_t address, uint8_t value);
42
43static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
44static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
45static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
46static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
47
48static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
49static uint8_t _GBPKJDRead(struct GBMemory*, uint16_t address);
50static uint8_t _GBBBDRead(struct GBMemory*, uint16_t address);
51static uint8_t _GBHitekRead(struct GBMemory*, uint16_t address);
52
53static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
54static void _GBPocketCamCapture(struct GBMemory*);
55
56static void _GBMBC6MapChip(struct GB*, int half, uint8_t value);
57
58void GBMBCSwitchBank(struct GB* gb, int bank) {
59 size_t bankStart = bank * GB_SIZE_CART_BANK0;
60 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
61 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
62 bankStart &= (gb->memory.romSize - 1);
63 bank = bankStart / GB_SIZE_CART_BANK0;
64 }
65 gb->memory.romBank = &gb->memory.rom[bankStart];
66 gb->memory.currentBank = bank;
67 if (gb->cpu->pc < GB_BASE_VRAM) {
68 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
69 }
70}
71
72void GBMBCSwitchBank0(struct GB* gb, int bank) {
73 size_t bankStart = bank * GB_SIZE_CART_BANK0;
74 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
75 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
76 bankStart &= (gb->memory.romSize - 1);
77 }
78 gb->memory.romBase = &gb->memory.rom[bankStart];
79 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
80 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
81 }
82}
83
84void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
85 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
86 bool isFlash = half ? gb->memory.mbcState.mbc6.flashBank1 : gb->memory.mbcState.mbc6.flashBank0;
87 if (isFlash) {
88 if (bankStart + GB_SIZE_CART_HALFBANK > GB_SIZE_MBC6_FLASH) {
89 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid Flash bank: %0X", bank);
90 bankStart &= GB_SIZE_MBC6_FLASH - 1;
91 bank = bankStart / GB_SIZE_CART_HALFBANK;
92 }
93 bankStart += gb->sramSize - GB_SIZE_MBC6_FLASH;
94 } else {
95 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
96 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
97 bankStart &= gb->memory.romSize - 1;
98 bank = bankStart / GB_SIZE_CART_HALFBANK;
99 if (!bank) {
100 ++bank;
101 }
102 }
103 }
104 if (!half) {
105 if (isFlash) {
106 gb->memory.romBank = &gb->memory.sram[bankStart];
107 } else {
108 gb->memory.romBank = &gb->memory.rom[bankStart];
109 }
110 gb->memory.currentBank = bank;
111 } else {
112 if (isFlash) {
113 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.sram[bankStart];
114 } else {
115 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
116 }
117 gb->memory.mbcState.mbc6.currentBank1 = bank;
118 }
119 if (gb->cpu->pc < GB_BASE_VRAM) {
120 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
121 }
122}
123
124static bool _isMulticart(const uint8_t* mem) {
125 bool success;
126 struct VFile* vf;
127
128 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
129 success = GBIsROM(vf);
130 vf->close(vf);
131
132 if (!success) {
133 return false;
134 }
135
136 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
137 success = GBIsROM(vf);
138 vf->close(vf);
139
140 if (!success) {
141 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
142 success = GBIsROM(vf);
143 vf->close(vf);
144 }
145
146 return success;
147}
148
149static bool _isWisdomTree(const uint8_t* mem, size_t size) {
150 size_t i;
151 for (i = 0x134; i < 0x14C; i += 4) {
152 if (*(uint32_t*) &mem[i] != 0) {
153 return false;
154 }
155 }
156 for (i = 0xF0; i < 0x100; i += 4) {
157 if (*(uint32_t*) &mem[i] != 0) {
158 return false;
159 }
160 }
161 if (mem[0x14D] != 0xE7) {
162 return false;
163 }
164 for (i = 0x300; i < size - 11; ++i) {
165 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
166 return true;
167 }
168 }
169 return false;
170}
171
172static enum GBMemoryBankControllerType _detectUnlMBC(const uint8_t* mem, size_t size) {
173 const struct GBCartridge* cart = (const struct GBCartridge*) &mem[0x100];
174
175 switch (cart->type) {
176 case 0:
177 if (_isWisdomTree(mem, size)) {
178 return GB_UNL_WISDOM_TREE;
179 }
180 break;
181 }
182
183 uint32_t secondaryLogo = doCrc32(&mem[0x184], 0x30);
184 switch (secondaryLogo) {
185 case 0x4fdab691:
186 return GB_UNL_HITEK;
187 case 0xc7d8c1df:
188 case 0x6d1ea662: // Garou
189 if (mem[0x7FFF] != 0x01) { // Make sure we're not using a "fixed" version
190 return GB_UNL_BBD;
191 }
192 }
193
194 return GB_MBC_AUTODETECT;
195}
196
197void GBMBCSwitchSramBank(struct GB* gb, int bank) {
198 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
199 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
200 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
201 bankStart &= (gb->sramSize - 1);
202 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
203 }
204 gb->memory.sramBank = &gb->memory.sram[bankStart];
205 gb->memory.sramCurrentBank = bank;
206}
207
208void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
209 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
210 size_t sramSize = gb->sramSize - GB_SIZE_MBC6_FLASH;
211 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > sramSize) {
212 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
213 bankStart &= (sramSize - 1);
214 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
215 }
216 if (!half) {
217 gb->memory.sramBank = &gb->memory.sram[bankStart];
218 gb->memory.sramCurrentBank = bank;
219 } else {
220 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
221 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
222 }
223}
224
225void GBMBCInit(struct GB* gb) {
226 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
227 if (gb->memory.rom) {
228 if (gb->memory.romSize >= 0x8000) {
229 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
230 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
231 cart = cartFooter;
232 }
233 }
234 switch (cart->ramSize) {
235 case 0:
236 gb->sramSize = 0;
237 break;
238 case 1:
239 gb->sramSize = 0x800;
240 break;
241 default:
242 case 2:
243 gb->sramSize = 0x2000;
244 break;
245 case 3:
246 gb->sramSize = 0x8000;
247 break;
248 case 4:
249 gb->sramSize = 0x20000;
250 break;
251 case 5:
252 gb->sramSize = 0x10000;
253 break;
254 }
255 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
256 gb->memory.mbcType = _detectUnlMBC(gb->memory.rom, gb->memory.romSize);
257 }
258
259 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
260 switch (cart->type) {
261 case 0:
262 case 8:
263 case 9:
264 gb->memory.mbcType = GB_MBC_NONE;
265 break;
266 case 1:
267 case 2:
268 case 3:
269 gb->memory.mbcType = GB_MBC1;
270 break;
271 case 5:
272 case 6:
273 gb->memory.mbcType = GB_MBC2;
274 break;
275 case 0x0B:
276 case 0x0C:
277 case 0x0D:
278 gb->memory.mbcType = GB_MMM01;
279 break;
280 case 0x0F:
281 case 0x10:
282 gb->memory.mbcType = GB_MBC3_RTC;
283 break;
284 case 0x11:
285 case 0x12:
286 case 0x13:
287 gb->memory.mbcType = GB_MBC3;
288 break;
289 default:
290 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
291 // Fall through
292 case 0x19:
293 case 0x1A:
294 case 0x1B:
295 gb->memory.mbcType = GB_MBC5;
296 break;
297 case 0x1C:
298 case 0x1D:
299 case 0x1E:
300 gb->memory.mbcType = GB_MBC5_RUMBLE;
301 break;
302 case 0x20:
303 gb->memory.mbcType = GB_MBC6;
304 break;
305 case 0x22:
306 gb->memory.mbcType = GB_MBC7;
307 break;
308 case 0xFC:
309 gb->memory.mbcType = GB_POCKETCAM;
310 break;
311 case 0xFD:
312 gb->memory.mbcType = GB_TAMA5;
313 break;
314 case 0xFE:
315 gb->memory.mbcType = GB_HuC3;
316 break;
317 case 0xFF:
318 gb->memory.mbcType = GB_HuC1;
319 break;
320 }
321 }
322 } else {
323 gb->memory.mbcType = GB_MBC_NONE;
324 }
325 gb->memory.mbcRead = NULL;
326 gb->memory.directSramAccess = true;
327 switch (gb->memory.mbcType) {
328 case GB_MBC_NONE:
329 gb->memory.mbcWrite = _GBMBCNone;
330 break;
331 case GB_MBC1:
332 gb->memory.mbcWrite = _GBMBC1;
333 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
334 gb->memory.mbcState.mbc1.multicartStride = 4;
335 } else {
336 gb->memory.mbcState.mbc1.multicartStride = 5;
337 }
338 break;
339 case GB_MBC2:
340 gb->memory.mbcWrite = _GBMBC2;
341 gb->memory.mbcRead = _GBMBC2Read;
342 gb->memory.directSramAccess = false;
343 gb->sramSize = 0x100;
344 break;
345 case GB_MBC3:
346 gb->memory.mbcWrite = _GBMBC3;
347 break;
348 default:
349 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
350 // Fall through
351 case GB_MBC5:
352 gb->memory.mbcWrite = _GBMBC5;
353 break;
354 case GB_MBC6:
355 gb->memory.mbcWrite = _GBMBC6;
356 gb->memory.mbcRead = _GBMBC6Read;
357 gb->memory.directSramAccess = false;
358 gb->sramSize += GB_SIZE_MBC6_FLASH; // Flash is concatenated at the end
359 break;
360 case GB_MBC7:
361 gb->memory.mbcWrite = _GBMBC7;
362 gb->memory.mbcRead = _GBMBC7Read;
363 gb->sramSize = 0x100;
364 break;
365 case GB_MMM01:
366 gb->memory.mbcWrite = _GBMMM01;
367 break;
368 case GB_HuC1:
369 gb->memory.mbcWrite = _GBHuC1;
370 break;
371 case GB_HuC3:
372 gb->memory.mbcWrite = _GBHuC3;
373 break;
374 case GB_TAMA5:
375 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
376 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
377 gb->memory.mbcWrite = _GBTAMA5;
378 gb->memory.mbcRead = _GBTAMA5Read;
379 gb->sramSize = 0x20;
380 break;
381 case GB_MBC3_RTC:
382 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
383 gb->memory.mbcWrite = _GBMBC3;
384 break;
385 case GB_MBC5_RUMBLE:
386 gb->memory.mbcWrite = _GBMBC5;
387 break;
388 case GB_POCKETCAM:
389 gb->memory.mbcWrite = _GBPocketCam;
390 gb->memory.mbcRead = _GBPocketCamRead;
391 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
392 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
393 }
394 break;
395 case GB_UNL_WISDOM_TREE:
396 gb->memory.mbcWrite = _GBWisdomTree;
397 break;
398 case GB_UNL_BBD:
399 gb->memory.mbcWrite = _GBBBD;
400 gb->memory.mbcRead = _GBBBDRead;
401 break;
402 case GB_UNL_HITEK:
403 gb->memory.mbcWrite = _GBHitek;
404 gb->memory.mbcRead = _GBHitekRead;
405 gb->memory.mbcState.bbd.dataSwapMode = 7;
406 gb->memory.mbcState.bbd.bankSwapMode = 7;
407 break;
408 case GB_UNL_PKJD:
409 gb->memory.mbcWrite = _GBPKJD;
410 gb->memory.mbcRead = _GBPKJDRead;
411 break;
412 }
413
414 gb->memory.currentBank = 1;
415 gb->memory.sramCurrentBank = 0;
416 gb->memory.sramAccess = false;
417 gb->memory.rtcAccess = false;
418 gb->memory.activeRtcReg = 0;
419 gb->memory.rtcLatched = false;
420 gb->memory.rtcLastLatch = 0;
421 if (gb->memory.rtc) {
422 if (gb->memory.rtc->sample) {
423 gb->memory.rtc->sample(gb->memory.rtc);
424 }
425 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
426 } else {
427 gb->memory.rtcLastLatch = time(0);
428 }
429 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
430
431 GBResizeSram(gb, gb->sramSize);
432
433 if (gb->memory.mbcType == GB_MBC3_RTC) {
434 GBMBCRTCRead(gb);
435 }
436}
437
438static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
439 time_t t;
440 if (rtc) {
441 if (rtc->sample) {
442 rtc->sample(rtc);
443 }
444 t = rtc->unixTime(rtc);
445 } else {
446 t = time(0);
447 }
448 time_t currentLatch = t;
449 t -= *rtcLastLatch;
450 *rtcLastLatch = currentLatch;
451
452 int64_t diff;
453 diff = rtcRegs[0] + t % 60;
454 if (diff < 0) {
455 diff += 60;
456 t -= 60;
457 }
458 rtcRegs[0] = diff % 60;
459 t /= 60;
460 t += diff / 60;
461
462 diff = rtcRegs[1] + t % 60;
463 if (diff < 0) {
464 diff += 60;
465 t -= 60;
466 }
467 rtcRegs[1] = diff % 60;
468 t /= 60;
469 t += diff / 60;
470
471 diff = rtcRegs[2] + t % 24;
472 if (diff < 0) {
473 diff += 24;
474 t -= 24;
475 }
476 rtcRegs[2] = diff % 24;
477 t /= 24;
478 t += diff / 24;
479
480 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
481 rtcRegs[3] = diff;
482 rtcRegs[4] &= 0xFE;
483 rtcRegs[4] |= (diff >> 8) & 1;
484 if (diff & 0x200) {
485 rtcRegs[4] |= 0x80;
486 }
487}
488
489static void _GBMBC1Update(struct GB* gb) {
490 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
491 int bank = state->bankLo;
492 bank &= (1 << state->multicartStride) - 1;
493 bank |= state->bankHi << state->multicartStride;
494 if (state->mode) {
495 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
496 GBMBCSwitchSramBank(gb, state->bankHi & 3);
497 } else {
498 GBMBCSwitchBank0(gb, 0);
499 GBMBCSwitchSramBank(gb, 0);
500 }
501 if (!(state->bankLo & 0x1F)) {
502 ++state->bankLo;
503 ++bank;
504 }
505 GBMBCSwitchBank(gb, bank);
506}
507
508void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
509 struct GBMemory* memory = &gb->memory;
510 int bank = value & 0x1F;
511 switch (address >> 13) {
512 case 0x0:
513 switch (value & 0xF) {
514 case 0:
515 memory->sramAccess = false;
516 break;
517 case 0xA:
518 memory->sramAccess = true;
519 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
520 break;
521 default:
522 // TODO
523 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
524 break;
525 }
526 break;
527 case 0x1:
528 memory->mbcState.mbc1.bankLo = bank;
529 _GBMBC1Update(gb);
530 break;
531 case 0x2:
532 bank &= 3;
533 memory->mbcState.mbc1.bankHi = bank;
534 _GBMBC1Update(gb);
535 break;
536 case 0x3:
537 memory->mbcState.mbc1.mode = value & 1;
538 _GBMBC1Update(gb);
539 break;
540 default:
541 // TODO
542 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
543 break;
544 }
545}
546
547void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
548 struct GBMemory* memory = &gb->memory;
549 int shift = (address & 1) * 4;
550 int bank = value & 0xF;
551 switch ((address & 0xC100) >> 8) {
552 case 0x0:
553 switch (value & 0x0F) {
554 case 0:
555 memory->sramAccess = false;
556 break;
557 case 0xA:
558 memory->sramAccess = true;
559 break;
560 default:
561 // TODO
562 mLOG(GB_MBC, STUB, "MBC2 unknown value %02X", value);
563 break;
564 }
565 break;
566 case 0x1:
567 if (!bank) {
568 ++bank;
569 }
570 GBMBCSwitchBank(gb, bank);
571 break;
572 case 0x80:
573 case 0x81:
574 case 0x82:
575 case 0x83:
576 if (!memory->sramAccess) {
577 return;
578 }
579 address &= 0x1FF;
580 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
581 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
582 break;
583 default:
584 // TODO
585 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
586 break;
587 }
588}
589
590static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
591 if (!memory->sramAccess) {
592 return 0xFF;
593 }
594 address &= 0x1FF;
595 int shift = (address & 1) * 4;
596 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
597}
598
599void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
600 struct GBMemory* memory = &gb->memory;
601 int bank = value;
602 switch (address >> 13) {
603 case 0x0:
604 switch (value) {
605 case 0:
606 memory->sramAccess = false;
607 break;
608 case 0xA:
609 memory->sramAccess = true;
610 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
611 break;
612 default:
613 // TODO
614 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
615 break;
616 }
617 break;
618 case 0x1:
619 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
620 bank &= 0x7F;
621 }
622 if (!bank) {
623 ++bank;
624 }
625 GBMBCSwitchBank(gb, bank);
626 break;
627 case 0x2:
628 if (value < 8) {
629 GBMBCSwitchSramBank(gb, value);
630 memory->rtcAccess = false;
631 } else if (value <= 0xC) {
632 memory->activeRtcReg = value - 8;
633 memory->rtcAccess = true;
634 }
635 break;
636 case 0x3:
637 if (memory->rtcLatched && value == 0) {
638 memory->rtcLatched = false;
639 } else if (!memory->rtcLatched && value == 1) {
640 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
641 memory->rtcLatched = true;
642 }
643 break;
644 }
645}
646
647void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
648 struct GBMemory* memory = &gb->memory;
649 int bank;
650 switch (address >> 12) {
651 case 0x0:
652 case 0x1:
653 switch (value) {
654 case 0:
655 memory->sramAccess = false;
656 break;
657 case 0xA:
658 memory->sramAccess = true;
659 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
660 break;
661 default:
662 // TODO
663 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
664 break;
665 }
666 break;
667 case 0x2:
668 bank = (memory->currentBank & 0x100) | value;
669 GBMBCSwitchBank(gb, bank);
670 break;
671 case 0x3:
672 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
673 GBMBCSwitchBank(gb, bank);
674 break;
675 case 0x4:
676 case 0x5:
677 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
678 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
679 value &= ~8;
680 }
681 GBMBCSwitchSramBank(gb, value & 0xF);
682 break;
683 default:
684 // TODO
685 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
686 break;
687 }
688}
689
690void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
691 struct GBMemory* memory = &gb->memory;
692 int bank = value;
693 switch (address >> 10) {
694 case 0:
695 switch (value) {
696 case 0:
697 memory->sramAccess = false;
698 break;
699 case 0xA:
700 memory->sramAccess = true;
701 break;
702 default:
703 // TODO
704 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
705 break;
706 }
707 break;
708 case 0x1:
709 GBMBCSwitchSramHalfBank(gb, 0, bank);
710 break;
711 case 0x2:
712 GBMBCSwitchSramHalfBank(gb, 1, bank);
713 break;
714 case 0x3:
715 mLOG(GB_MBC, STUB, "MBC6 unimplemented flash OE write: %04X:%02X", address, value);
716 break;
717 case 0x4:
718 mLOG(GB_MBC, STUB, "MBC6 unimplemented flash WE write: %04X:%02X", address, value);
719 break;
720 case 0x8:
721 case 0x9:
722 GBMBCSwitchHalfBank(gb, 0, bank);
723 break;
724 case 0xA:
725 case 0xB:
726 _GBMBC6MapChip(gb, 0, value);
727 break;
728 case 0xC:
729 case 0xD:
730 GBMBCSwitchHalfBank(gb, 1, bank);
731 break;
732 case 0xE:
733 case 0xF:
734 _GBMBC6MapChip(gb, 1, value);
735 break;
736 case 0x28:
737 case 0x29:
738 case 0x2A:
739 case 0x2B:
740 if (memory->sramAccess) {
741 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
742 }
743 break;
744 case 0x2C:
745 case 0x2D:
746 case 0x2E:
747 case 0x2F:
748 if (memory->sramAccess) {
749 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
750 }
751 break;
752 default:
753 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
754 break;
755 }
756}
757
758uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
759 if (!memory->sramAccess) {
760 return 0xFF;
761 }
762 switch (address >> 12) {
763 case 0xA:
764 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
765 case 0xB:
766 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
767 }
768 return 0xFF;
769}
770
771static void _GBMBC6MapChip(struct GB* gb, int half, uint8_t value) {
772 if (!half) {
773 gb->memory.mbcState.mbc6.flashBank0 = !!(value & 0x08);
774 GBMBCSwitchHalfBank(gb, half, gb->memory.currentBank);
775 } else {
776 gb->memory.mbcState.mbc6.flashBank1 = !!(value & 0x08);
777 GBMBCSwitchHalfBank(gb, half, gb->memory.mbcState.mbc6.currentBank1);
778 }
779}
780
781void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
782 int bank = value & 0x7F;
783 switch (address >> 13) {
784 case 0x0:
785 switch (value) {
786 default:
787 case 0:
788 gb->memory.mbcState.mbc7.access = 0;
789 break;
790 case 0xA:
791 gb->memory.mbcState.mbc7.access |= 1;
792 break;
793 }
794 break;
795 case 0x1:
796 GBMBCSwitchBank(gb, bank);
797 break;
798 case 0x2:
799 if (value == 0x40) {
800 gb->memory.mbcState.mbc7.access |= 2;
801 } else {
802 gb->memory.mbcState.mbc7.access &= ~2;
803 }
804 break;
805 case 0x5:
806 _GBMBC7Write(&gb->memory, address, value);
807 break;
808 default:
809 // TODO
810 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
811 break;
812 }
813}
814
815uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
816 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
817 if (mbc7->access != 3) {
818 return 0xFF;
819 }
820 switch (address & 0xF0) {
821 case 0x20:
822 if (memory->rotation && memory->rotation->readTiltX) {
823 int32_t x = -memory->rotation->readTiltX(memory->rotation);
824 x >>= 21;
825 x += 0x81D0;
826 return x;
827 }
828 return 0xFF;
829 case 0x30:
830 if (memory->rotation && memory->rotation->readTiltX) {
831 int32_t x = -memory->rotation->readTiltX(memory->rotation);
832 x >>= 21;
833 x += 0x81D0;
834 return x >> 8;
835 }
836 return 7;
837 case 0x40:
838 if (memory->rotation && memory->rotation->readTiltY) {
839 int32_t y = -memory->rotation->readTiltY(memory->rotation);
840 y >>= 21;
841 y += 0x81D0;
842 return y;
843 }
844 return 0xFF;
845 case 0x50:
846 if (memory->rotation && memory->rotation->readTiltY) {
847 int32_t y = -memory->rotation->readTiltY(memory->rotation);
848 y >>= 21;
849 y += 0x81D0;
850 return y >> 8;
851 }
852 return 7;
853 case 0x60:
854 return 0;
855 case 0x80:
856 return mbc7->eeprom;
857 default:
858 return 0xFF;
859 }
860}
861
862static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
863 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
864 if (mbc7->access != 3) {
865 return;
866 }
867 switch (address & 0xF0) {
868 case 0x00:
869 mbc7->latch = (value & 0x55) == 0x55;
870 return;
871 case 0x10:
872 mbc7->latch |= (value & 0xAA);
873 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
874 memory->rotation->sample(memory->rotation);
875 }
876 mbc7->latch = 0;
877 return;
878 default:
879 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
880 return;
881 case 0x80:
882 break;
883 }
884 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
885 value = GBMBC7FieldFillDO(value); // Hi-Z
886 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
887 mbc7->state = GBMBC7_STATE_IDLE;
888 }
889 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
890 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
891 mbc7->sr <<= 1;
892 mbc7->sr |= GBMBC7FieldGetDI(value);
893 ++mbc7->srBits;
894 }
895 switch (mbc7->state) {
896 case GBMBC7_STATE_IDLE:
897 if (GBMBC7FieldIsDI(value)) {
898 mbc7->state = GBMBC7_STATE_READ_COMMAND;
899 mbc7->srBits = 0;
900 mbc7->sr = 0;
901 }
902 break;
903 case GBMBC7_STATE_READ_COMMAND:
904 if (mbc7->srBits == 10) {
905 mbc7->state = 0x10 | (mbc7->sr >> 6);
906 if (mbc7->state & 0xC) {
907 mbc7->state &= ~0x3;
908 }
909 mbc7->srBits = 0;
910 mbc7->address = mbc7->sr & 0x7F;
911 }
912 break;
913 case GBMBC7_STATE_DO:
914 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
915 mbc7->sr <<= 1;
916 --mbc7->srBits;
917 if (!mbc7->srBits) {
918 mbc7->state = GBMBC7_STATE_IDLE;
919 }
920 break;
921 default:
922 break;
923 }
924 switch (mbc7->state) {
925 case GBMBC7_STATE_EEPROM_EWEN:
926 mbc7->writable = true;
927 mbc7->state = GBMBC7_STATE_IDLE;
928 break;
929 case GBMBC7_STATE_EEPROM_EWDS:
930 mbc7->writable = false;
931 mbc7->state = GBMBC7_STATE_IDLE;
932 break;
933 case GBMBC7_STATE_EEPROM_WRITE:
934 if (mbc7->srBits == 16) {
935 if (mbc7->writable) {
936 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
937 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
938 }
939 mbc7->state = GBMBC7_STATE_IDLE;
940 }
941 break;
942 case GBMBC7_STATE_EEPROM_ERASE:
943 if (mbc7->writable) {
944 memory->sram[mbc7->address * 2] = 0xFF;
945 memory->sram[mbc7->address * 2 + 1] = 0xFF;
946 }
947 mbc7->state = GBMBC7_STATE_IDLE;
948 break;
949 case GBMBC7_STATE_EEPROM_READ:
950 mbc7->srBits = 16;
951 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
952 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
953 mbc7->state = GBMBC7_STATE_DO;
954 value = GBMBC7FieldClearDO(value);
955 break;
956 case GBMBC7_STATE_EEPROM_WRAL:
957 if (mbc7->srBits == 16) {
958 if (mbc7->writable) {
959 int i;
960 for (i = 0; i < 128; ++i) {
961 memory->sram[i * 2] = mbc7->sr >> 8;
962 memory->sram[i * 2 + 1] = mbc7->sr;
963 }
964 }
965 mbc7->state = GBMBC7_STATE_IDLE;
966 }
967 break;
968 case GBMBC7_STATE_EEPROM_ERAL:
969 if (mbc7->writable) {
970 int i;
971 for (i = 0; i < 128; ++i) {
972 memory->sram[i * 2] = 0xFF;
973 memory->sram[i * 2 + 1] = 0xFF;
974 }
975 }
976 mbc7->state = GBMBC7_STATE_IDLE;
977 break;
978 default:
979 break;
980 }
981 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
982 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
983 }
984 mbc7->eeprom = value;
985}
986
987void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
988 struct GBMemory* memory = &gb->memory;
989 if (!memory->mbcState.mmm01.locked) {
990 switch (address >> 13) {
991 case 0x0:
992 memory->mbcState.mmm01.locked = true;
993 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
994 break;
995 case 0x1:
996 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
997 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
998 break;
999 case 0x2:
1000 memory->mbcState.mmm01.currentBank0 &= ~0x180;
1001 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
1002 break;
1003 default:
1004 // TODO
1005 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
1006 break;
1007 }
1008 return;
1009 }
1010 switch (address >> 13) {
1011 case 0x0:
1012 switch (value) {
1013 case 0xA:
1014 memory->sramAccess = true;
1015 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1016 break;
1017 default:
1018 memory->sramAccess = false;
1019 break;
1020 }
1021 break;
1022 case 0x1:
1023 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
1024 break;
1025 case 0x2:
1026 GBMBCSwitchSramBank(gb, value);
1027 break;
1028 default:
1029 // TODO
1030 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
1031 break;
1032 }
1033}
1034
1035void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
1036 struct GBMemory* memory = &gb->memory;
1037 int bank = value & 0x3F;
1038 switch (address >> 13) {
1039 case 0x0:
1040 switch (value) {
1041 case 0xE:
1042 memory->sramAccess = false;
1043 break;
1044 default:
1045 memory->sramAccess = true;
1046 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1047 break;
1048 }
1049 break;
1050 case 0x1:
1051 GBMBCSwitchBank(gb, bank);
1052 break;
1053 case 0x2:
1054 GBMBCSwitchSramBank(gb, value);
1055 break;
1056 default:
1057 // TODO
1058 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
1059 break;
1060 }
1061}
1062
1063void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
1064 struct GBMemory* memory = &gb->memory;
1065 int bank = value & 0x3F;
1066 if (address & 0x1FFF) {
1067 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
1068 }
1069
1070 switch (address >> 13) {
1071 case 0x0:
1072 switch (value) {
1073 case 0xA:
1074 memory->sramAccess = true;
1075 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1076 break;
1077 default:
1078 memory->sramAccess = false;
1079 break;
1080 }
1081 break;
1082 case 0x1:
1083 GBMBCSwitchBank(gb, bank);
1084 break;
1085 case 0x2:
1086 GBMBCSwitchSramBank(gb, bank);
1087 break;
1088 default:
1089 // TODO
1090 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
1091 break;
1092 }
1093}
1094
1095void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
1096 struct GBMemory* memory = &gb->memory;
1097 int bank = value & 0x3F;
1098 switch (address >> 13) {
1099 case 0x0:
1100 switch (value) {
1101 case 0:
1102 memory->sramAccess = false;
1103 break;
1104 case 0xA:
1105 memory->sramAccess = true;
1106 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1107 break;
1108 default:
1109 // TODO
1110 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1111 break;
1112 }
1113 break;
1114 case 0x1:
1115 GBMBCSwitchBank(gb, bank);
1116 break;
1117 case 0x2:
1118 if (value < 0x10) {
1119 GBMBCSwitchSramBank(gb, value);
1120 memory->mbcState.pocketCam.registersActive = false;
1121 } else {
1122 memory->mbcState.pocketCam.registersActive = true;
1123 }
1124 break;
1125 case 0x5:
1126 address &= 0x7F;
1127 if (address == 0 && value & 1) {
1128 value &= 6; // TODO: Timing
1129 _GBPocketCamCapture(memory);
1130 }
1131 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1132 memory->mbcState.pocketCam.registers[address] = value;
1133 }
1134 break;
1135 default:
1136 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1137 break;
1138 }
1139}
1140
1141uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1142 if (memory->mbcState.pocketCam.registersActive) {
1143 if ((address & 0x7F) == 0) {
1144 return memory->mbcState.pocketCam.registers[0];
1145 }
1146 return 0;
1147 }
1148 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1149}
1150
1151void _GBPocketCamCapture(struct GBMemory* memory) {
1152 if (!memory->cam) {
1153 return;
1154 }
1155 const void* image = NULL;
1156 size_t stride;
1157 enum mColorFormat format;
1158 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1159 if (!image) {
1160 return;
1161 }
1162 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1163 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1164 size_t x, y;
1165 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1166 for (x = 0; x < GBCAM_WIDTH; ++x) {
1167 uint32_t gray;
1168 uint32_t color;
1169 switch (format) {
1170 case mCOLOR_XBGR8:
1171 case mCOLOR_XRGB8:
1172 case mCOLOR_ARGB8:
1173 case mCOLOR_ABGR8:
1174 color = ((const uint32_t*) image)[y * stride + x];
1175 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1176 break;
1177 case mCOLOR_BGRX8:
1178 case mCOLOR_RGBX8:
1179 case mCOLOR_RGBA8:
1180 case mCOLOR_BGRA8:
1181 color = ((const uint32_t*) image)[y * stride + x];
1182 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1183 break;
1184 case mCOLOR_BGR5:
1185 case mCOLOR_RGB5:
1186 case mCOLOR_ARGB5:
1187 case mCOLOR_ABGR5:
1188 color = ((const uint16_t*) image)[y * stride + x];
1189 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1190 break;
1191 case mCOLOR_BGR565:
1192 case mCOLOR_RGB565:
1193 color = ((const uint16_t*) image)[y * stride + x];
1194 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1195 break;
1196 case mCOLOR_BGRA5:
1197 case mCOLOR_RGBA5:
1198 color = ((const uint16_t*) image)[y * stride + x];
1199 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1200 break;
1201 default:
1202 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1203 return;
1204 }
1205 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1206 gray = (gray + 1) * exposure / 0x300;
1207 // TODO: Additional processing
1208 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1209 if (gray < pocketCam->registers[matrixEntry + 6]) {
1210 gray = 0x101;
1211 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1212 gray = 0x100;
1213 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1214 gray = 0x001;
1215 } else {
1216 gray = 0;
1217 }
1218 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1219 uint16_t existing;
1220 LOAD_16LE(existing, coord + 0x100, memory->sram);
1221 existing |= gray << (7 - (x & 7));
1222 STORE_16LE(existing, coord + 0x100, memory->sram);
1223 }
1224 }
1225}
1226
1227void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1228 struct GBMemory* memory = &gb->memory;
1229 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1230 switch (address >> 13) {
1231 case 0x5:
1232 if (address & 1) {
1233 tama5->reg = value;
1234 } else {
1235 value &= 0xF;
1236 if (tama5->reg < GBTAMA5_MAX) {
1237 tama5->registers[tama5->reg] = value;
1238 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1239 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1240 switch (tama5->reg) {
1241 case GBTAMA5_BANK_LO:
1242 case GBTAMA5_BANK_HI:
1243 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1244 break;
1245 case GBTAMA5_WRITE_LO:
1246 case GBTAMA5_WRITE_HI:
1247 case GBTAMA5_CS:
1248 break;
1249 case GBTAMA5_ADDR_LO:
1250 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1251 case 0x0: // RAM write
1252 memory->sram[address] = out;
1253 break;
1254 case 0x1: // RAM read
1255 break;
1256 default:
1257 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1258 }
1259 break;
1260 default:
1261 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1262 break;
1263 }
1264 } else {
1265 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1266 }
1267 }
1268 break;
1269 default:
1270 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1271 }
1272}
1273
1274uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1275 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1276 if ((address & 0x1FFF) > 1) {
1277 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1278 }
1279 if (address & 1) {
1280 return 0xFF;
1281 } else {
1282 uint8_t value = 0xF0;
1283 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1284 switch (tama5->reg) {
1285 case GBTAMA5_ACTIVE:
1286 return 0xF1;
1287 case GBTAMA5_READ_LO:
1288 case GBTAMA5_READ_HI:
1289 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1290 case 1:
1291 value = memory->sram[address];
1292 break;
1293 default:
1294 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1295 break;
1296 }
1297 if (tama5->reg == GBTAMA5_READ_HI) {
1298 value >>= 4;
1299 }
1300 value |= 0xF0;
1301 return value;
1302 default:
1303 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1304 return 0xF1;
1305 }
1306 }
1307}
1308
1309void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1310 UNUSED(value);
1311 int bank = address & 0x3F;
1312 switch (address >> 14) {
1313 case 0x0:
1314 GBMBCSwitchBank0(gb, bank * 2);
1315 GBMBCSwitchBank(gb, bank * 2 + 1);
1316 break;
1317 default:
1318 // TODO
1319 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1320 break;
1321 }
1322}
1323
1324void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value) {
1325 struct GBMemory* memory = &gb->memory;
1326 switch (address >> 13) {
1327 case 0x2:
1328 if (value < 8) {
1329 memory->directSramAccess = true;
1330 memory->activeRtcReg = 0;
1331 } else if (value >= 0xD && value <= 0xF) {
1332 memory->directSramAccess = false;
1333 memory->rtcAccess = false;
1334 memory->activeRtcReg = value - 8;
1335 }
1336 break;
1337 case 0x5:
1338 if (!memory->sramAccess) {
1339 return;
1340 }
1341 switch (memory->activeRtcReg) {
1342 case 0:
1343 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
1344 break;
1345 case 5:
1346 case 6:
1347 memory->mbcState.pkjd.reg[memory->activeRtcReg - 5] = value;
1348 break;
1349 case 7:
1350 switch (value) {
1351 case 0x11:
1352 memory->mbcState.pkjd.reg[0]--;
1353 break;
1354 case 0x12:
1355 memory->mbcState.pkjd.reg[1]--;
1356 break;
1357 case 0x41:
1358 memory->mbcState.pkjd.reg[0] += memory->mbcState.pkjd.reg[1];
1359 break;
1360 case 0x42:
1361 memory->mbcState.pkjd.reg[1] += memory->mbcState.pkjd.reg[0];
1362 break;
1363 case 0x51:
1364 memory->mbcState.pkjd.reg[0]++;
1365 break;
1366 case 0x52:
1367 memory->mbcState.pkjd.reg[1]--;
1368 break;
1369 }
1370 break;
1371 }
1372 return;
1373 }
1374 _GBMBC3(gb, address, value);
1375}
1376
1377static uint8_t _GBPKJDRead(struct GBMemory* memory, uint16_t address) {
1378 if (!memory->sramAccess) {
1379 return 0xFF;
1380 }
1381 switch (memory->activeRtcReg) {
1382 case 0:
1383 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1384 case 5:
1385 case 6:
1386 return memory->mbcState.pkjd.reg[memory->activeRtcReg - 5];
1387 default:
1388 return 0;
1389 }
1390}
1391
1392static uint8_t _reorderBits(uint8_t input, const uint8_t* reorder) {
1393 uint8_t newbyte = 0;
1394 int i;
1395 for(i = 0; i < 8; ++i) {
1396 int oldbit = reorder[i];
1397 int newbit = i;
1398 newbyte += ((input >> oldbit) & 1) << newbit;
1399 }
1400
1401 return newbyte;
1402}
1403
1404static const uint8_t _bbdDataReordering[8][8] = {
1405 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 00 - Normal
1406 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 01 - NOT KNOWN YET
1407 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 02 - NOT KNOWN YET
1408 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 03 - NOT KNOWN YET
1409 { 0, 5, 1, 3, 4, 2, 6, 7 }, // 04 - Garou
1410 { 0, 4, 2, 3, 1, 5, 6, 7 }, // 05 - Harry
1411 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 06 - NOT KNOWN YET
1412 { 0, 1, 5, 3, 4, 2, 6, 7 }, // 07 - Digimon
1413};
1414
1415static const uint8_t _bbdBankReordering[8][8] = {
1416 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 00 - Normal
1417 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 01 - NOT KNOWN YET
1418 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 02 - NOT KNOWN YET
1419 { 3, 4, 2, 0, 1, 5, 6, 7 }, // 03 - 0,1 unconfirmed. Digimon/Garou
1420 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 04 - NOT KNOWN YET
1421 { 1, 2, 3, 4, 0, 5, 6, 7 }, // 05 - 0,1 unconfirmed. Harry
1422 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 06 - NOT KNOWN YET
1423 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 07 - NOT KNOWN YET
1424};
1425
1426void _GBBBD(struct GB* gb, uint16_t address, uint8_t value) {
1427 struct GBMemory* memory = &gb->memory;
1428 switch (address & 0xF0FF) {
1429 case 0x2000:
1430 value = _reorderBits(value, _bbdBankReordering[memory->mbcState.bbd.bankSwapMode]);
1431 break;
1432 case 0x2001:
1433 memory->mbcState.bbd.dataSwapMode = value & 0x07;
1434 if (!(memory->mbcState.bbd.dataSwapMode == 0x07 || memory->mbcState.bbd.dataSwapMode == 0x05 || memory->mbcState.bbd.dataSwapMode == 0x04 || memory->mbcState.bbd.dataSwapMode == 0x00)) {
1435 mLOG(GB_MBC, STUB, "Bitswap mode unsupported: %X", memory->mbcState.bbd.dataSwapMode);
1436 }
1437 break;
1438 case 0x2080:
1439 memory->mbcState.bbd.bankSwapMode = value & 0x07;
1440 if (!(memory->mbcState.bbd.bankSwapMode == 0x03 || memory->mbcState.bbd.bankSwapMode == 0x05 || memory->mbcState.bbd.bankSwapMode == 0x00)) {
1441 mLOG(GB_MBC, STUB, "Bankswap mode unsupported: %X", memory->mbcState.bbd.dataSwapMode);
1442 }
1443 break;
1444 }
1445 _GBMBC5(gb, address, value);
1446}
1447
1448uint8_t _GBBBDRead(struct GBMemory* memory, uint16_t address) {
1449 switch (address >> 14) {
1450 case 0:
1451 default:
1452 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
1453 case 1:
1454 return _reorderBits(memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)], _bbdDataReordering[memory->mbcState.bbd.dataSwapMode]);
1455 }
1456}
1457
1458static const uint8_t _hitekDataReordering[8][8] = {
1459 { 0, 1, 2, 3, 4, 5, 6, 7 },
1460 { 0, 6, 5, 3, 4, 1, 2, 7 },
1461 { 0, 5, 6, 3, 4, 2, 1, 7 },
1462 { 0, 6, 2, 3, 4, 5, 1, 7 },
1463 { 0, 6, 1, 3, 4, 5, 2, 7 },
1464 { 0, 1, 6, 3, 4, 5, 2, 7 },
1465 { 0, 2, 6, 3, 4, 1, 5, 7 },
1466 { 0, 6, 2, 3, 4, 1, 5, 7 },
1467};
1468
1469static const uint8_t _hitekBankReordering[8][8] = {
1470 { 0, 1, 2, 3, 4, 5, 6, 7 },
1471 { 3, 2, 1, 0, 4, 5, 6, 7 },
1472 { 2, 1, 0, 3, 4, 5, 6, 7 },
1473 { 1, 0, 3, 2, 4, 5, 6, 7 },
1474 { 0, 3, 2, 1, 4, 5, 6, 7 },
1475 { 2, 3, 0, 1, 4, 5, 6, 7 },
1476 { 3, 0, 1, 2, 4, 5, 6, 7 },
1477 { 2, 0, 3, 1, 4, 5, 6, 7 },
1478};
1479
1480void _GBHitek(struct GB* gb, uint16_t address, uint8_t value) {
1481 struct GBMemory* memory = &gb->memory;
1482 switch (address & 0xF0FF) {
1483 case 0x2000:
1484 value = _reorderBits(value, _hitekBankReordering[memory->mbcState.bbd.bankSwapMode]);
1485 break;
1486 case 0x2001:
1487 memory->mbcState.bbd.dataSwapMode = value & 0x07;
1488 break;
1489 case 0x2080:
1490 memory->mbcState.bbd.bankSwapMode = value & 0x07;
1491 break;
1492 case 0x300:
1493 // See hhugboy src/memory/mbc/MbcUnlHitek.cpp for commentary on this return
1494 return;
1495 }
1496 _GBMBC5(gb, address, value);
1497}
1498
1499uint8_t _GBHitekRead(struct GBMemory* memory, uint16_t address) {
1500 switch (address >> 14) {
1501 case 0:
1502 default:
1503 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
1504 case 1:
1505 return _reorderBits(memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)], _hitekDataReordering[memory->mbcState.bbd.dataSwapMode]);
1506 }
1507}
1508
1509void GBMBCRTCRead(struct GB* gb) {
1510 struct GBMBCRTCSaveBuffer rtcBuffer;
1511 struct VFile* vf = gb->sramVf;
1512 if (!vf) {
1513 return;
1514 }
1515 vf->seek(vf, gb->sramSize, SEEK_SET);
1516 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1517 return;
1518 }
1519
1520 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1521 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1522 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1523 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1524 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1525 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1526}
1527
1528void GBMBCRTCWrite(struct GB* gb) {
1529 struct VFile* vf = gb->sramVf;
1530 if (!vf) {
1531 return;
1532 }
1533
1534 uint8_t rtcRegs[5];
1535 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1536 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1537 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1538
1539 struct GBMBCRTCSaveBuffer rtcBuffer;
1540 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1541 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1542 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1543 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1544 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1545 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1546 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1547 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1548 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1549 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1550 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1551
1552 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1553 // Writing past the end of the file can invalidate the file mapping
1554 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1555 gb->memory.sram = NULL;
1556 }
1557 vf->seek(vf, gb->sramSize, SEEK_SET);
1558 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1559 if (!gb->memory.sram) {
1560 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1561 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1562 }
1563}