1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_VRAM = 0x8000,
 26	GB_BASE_EXTERNAL_RAM = 0xA000,
 27	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 28	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 29	GB_BASE_OAM = 0xFE00,
 30	GB_BASE_UNUSABLE = 0xFEA0,
 31	GB_BASE_IO = 0xFF00,
 32	GB_BASE_HRAM = 0xFF80,
 33	GB_BASE_IE = 0xFFFF
 34};
 35
 36enum {
 37	GB_REGION_CART_BANK0 = 0x0,
 38	GB_REGION_CART_BANK1 = 0x4,
 39	GB_REGION_VRAM = 0x8,
 40	GB_REGION_EXTERNAL_RAM = 0xA,
 41	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 42	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 43	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 44	GB_REGION_OTHER = 0xF,
 45};
 46
 47enum {
 48	GB_SIZE_CART_BANK0 = 0x4000,
 49	GB_SIZE_CART_MAX = 0x800000,
 50	GB_SIZE_VRAM = 0x4000,
 51	GB_SIZE_VRAM_BANK0 = 0x2000,
 52	GB_SIZE_EXTERNAL_RAM = 0x2000,
 53	GB_SIZE_WORKING_RAM = 0x8000,
 54	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 55	GB_SIZE_OAM = 0xA0,
 56	GB_SIZE_IO = 0x80,
 57	GB_SIZE_HRAM = 0x7F,
 58};
 59
 60enum {
 61	GB_SRAM_DIRT_NEW = 1,
 62	GB_SRAM_DIRT_SEEN = 2
 63};
 64
 65struct GBMemory;
 66typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
 67
 68DECL_BITFIELD(GBMBC7Field, uint8_t);
 69DECL_BIT(GBMBC7Field, SK, 6);
 70DECL_BIT(GBMBC7Field, CS, 7);
 71DECL_BIT(GBMBC7Field, IO, 1);
 72
 73enum GBMBC7MachineState {
 74	GBMBC7_STATE_NULL = -1,
 75	GBMBC7_STATE_IDLE = 0,
 76	GBMBC7_STATE_READ_COMMAND = 1,
 77	GBMBC7_STATE_READ_ADDRESS = 2,
 78	GBMBC7_STATE_COMMAND_0 = 3,
 79	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 80	GBMBC7_STATE_COMMAND_SR_READ = 5,
 81	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 82	GBMBC7_STATE_READ = 7,
 83	GBMBC7_STATE_WRITE = 8,
 84};
 85
 86struct GBMBC1State {
 87	int mode;
 88	int multicartStride;
 89};
 90
 91struct GBMBC7State {
 92	enum GBMBC7MachineState state;
 93	uint32_t sr;
 94	uint8_t address;
 95	bool writable;
 96	int srBits;
 97	int command;
 98	GBMBC7Field field;
 99};
100
101union GBMBCState {
102	struct GBMBC1State mbc1;
103	struct GBMBC7State mbc7;
104};
105
106struct mRotationSource;
107struct GBMemory {
108	uint8_t* rom;
109	uint8_t* romBase;
110	uint8_t* romBank;
111	enum GBMemoryBankControllerType mbcType;
112	GBMemoryBankController mbc;
113	union GBMBCState mbcState;
114	int currentBank;
115
116	uint8_t* wram;
117	uint8_t* wramBank;
118	int wramCurrentBank;
119
120	bool sramAccess;
121	uint8_t* sram;
122	uint8_t* sramBank;
123	int sramCurrentBank;
124
125	uint8_t io[GB_SIZE_IO];
126	bool ime;
127	uint8_t ie;
128
129	uint8_t hram[GB_SIZE_HRAM];
130
131	uint16_t dmaSource;
132	uint16_t dmaDest;
133	int dmaRemaining;
134
135	uint16_t hdmaSource;
136	uint16_t hdmaDest;
137	int hdmaRemaining;
138	bool isHdma;
139
140	struct mTimingEvent dmaEvent;
141	struct mTimingEvent hdmaEvent;
142
143	size_t romSize;
144
145	bool rtcAccess;
146	int activeRtcReg;
147	bool rtcLatched;
148	uint8_t rtcRegs[5];
149	time_t rtcLastLatch;
150	struct mRTCSource* rtc;
151	struct mRotationSource* rotation;
152	struct mRumble* rumble;
153};
154
155struct LR35902Core;
156void GBMemoryInit(struct GB* gb);
157void GBMemoryDeinit(struct GB* gb);
158
159void GBMemoryReset(struct GB* gb);
160void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
161
162uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
163void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
164
165int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
166
167uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
168
169void GBMemoryDMA(struct GB* gb, uint16_t base);
170void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
171
172void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
173
174struct GBSerializedState;
175void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
176void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
177
178CXX_GUARD_END
179
180#endif