src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.hw.p = gba;
54
55 int i;
56 for (i = 0; i < 16; ++i) {
57 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
60 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
61 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
64 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
65 }
66 for (; i < 256; ++i) {
67 gba->memory.waitstatesNonseq16[i] = 0;
68 gba->memory.waitstatesSeq16[i] = 0;
69 gba->memory.waitstatesNonseq32[i] = 0;
70 gba->memory.waitstatesSeq32[i] = 0;
71 }
72
73 gba->memory.activeRegion = -1;
74 cpu->memory.activeRegion = 0;
75 cpu->memory.activeMask = 0;
76 cpu->memory.setActiveRegion = GBASetActiveRegion;
77 cpu->memory.activeSeqCycles32 = 0;
78 cpu->memory.activeSeqCycles16 = 0;
79 cpu->memory.activeNonseqCycles32 = 0;
80 cpu->memory.activeNonseqCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 gba->memory.prefetch = false;
117 gba->memory.lastPrefetchedPc = 0;
118
119 if (!gba->memory.wram || !gba->memory.iwram) {
120 GBAMemoryDeinit(gba);
121 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
122 }
123}
124
125static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
126 struct ARMInstructionInfo info;
127 uint32_t nextAddress = address;
128 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
129 if (cpu->executionMode == MODE_THUMB) {
130 while (true) {
131 uint16_t opcode;
132 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
133 ARMDecodeThumb(opcode, &info);
134 switch (info.branchType) {
135 case ARM_BRANCH_NONE:
136 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
137 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
138 gba->idleDetectionStep = -1;
139 return;
140 }
141 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
142 uint32_t offset = 0;
143 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
144 offset = info.memory.offset.immediate;
145 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
146 int reg = info.memory.offset.reg;
147 if (gba->cachedRegisters[reg]) {
148 gba->idleDetectionStep = -1;
149 return;
150 }
151 offset = gba->cachedRegisters[reg];
152 }
153 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
154 loadAddress -= offset;
155 } else {
156 loadAddress += offset;
157 }
158 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
159 gba->idleDetectionStep = -1;
160 return;
161 }
162 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
163 gba->taintedRegisters[info.op1.reg] = true;
164 } else {
165 switch (info.memory.width) {
166 case 1:
167 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
168 break;
169 case 2:
170 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
171 break;
172 case 4:
173 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
174 break;
175 }
176 }
177 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
178 gba->taintedRegisters[info.op1.reg] = true;
179 }
180 nextAddress += WORD_SIZE_THUMB;
181 break;
182 case ARM_BRANCH:
183 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
184 gba->idleLoop = address;
185 gba->idleOptimization = IDLE_LOOP_REMOVE;
186 }
187 gba->idleDetectionStep = -1;
188 return;
189 default:
190 gba->idleDetectionStep = -1;
191 return;
192 }
193 }
194 } else {
195 gba->idleDetectionStep = -1;
196 }
197}
198
199static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
200 struct GBA* gba = (struct GBA*) cpu->master;
201 struct GBAMemory* memory = &gba->memory;
202
203 int newRegion = address >> BASE_OFFSET;
204 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
205 if (address == gba->idleLoop) {
206 if (gba->haltPending) {
207 gba->haltPending = false;
208 GBAHalt(gba);
209 } else {
210 gba->haltPending = true;
211 }
212 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
213 if (address == gba->lastJump) {
214 switch (gba->idleDetectionStep) {
215 case 0:
216 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
217 ++gba->idleDetectionStep;
218 break;
219 case 1:
220 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
221 gba->idleDetectionStep = -1;
222 ++gba->idleDetectionFailures;
223 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
224 gba->idleOptimization = IDLE_LOOP_IGNORE;
225 }
226 break;
227 }
228 _analyzeForIdleLoop(gba, cpu, address);
229 break;
230 }
231 } else {
232 gba->idleDetectionStep = 0;
233 }
234 }
235 }
236
237 gba->lastJump = address;
238 memory->lastPrefetchedPc = 0;
239 memory->lastPrefetchedLoads = 0;
240 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
241 return;
242 }
243
244 if (memory->activeRegion == REGION_BIOS) {
245 memory->biosPrefetch = cpu->prefetch[1];
246 }
247 memory->activeRegion = newRegion;
248 switch (newRegion) {
249 case REGION_BIOS:
250 cpu->memory.activeRegion = memory->bios;
251 cpu->memory.activeMask = SIZE_BIOS - 1;
252 break;
253 case REGION_WORKING_RAM:
254 cpu->memory.activeRegion = memory->wram;
255 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
256 break;
257 case REGION_WORKING_IRAM:
258 cpu->memory.activeRegion = memory->iwram;
259 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
260 break;
261 case REGION_VRAM:
262 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
263 cpu->memory.activeMask = 0x0000FFFF;
264 break;
265 case REGION_CART0:
266 case REGION_CART0_EX:
267 case REGION_CART1:
268 case REGION_CART1_EX:
269 case REGION_CART2:
270 case REGION_CART2_EX:
271 cpu->memory.activeRegion = memory->rom;
272 cpu->memory.activeMask = SIZE_CART0 - 1;
273 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
274 break;
275 }
276 // Fall through
277 default:
278 memory->activeRegion = -1;
279 cpu->memory.activeRegion = _deadbeef;
280 cpu->memory.activeMask = 0;
281 if (!gba->yankedRomSize) {
282 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
283 }
284 return;
285 }
286 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
287 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
288 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
289 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
290}
291
292#define LOAD_BAD \
293 if (gba->performingDMA) { \
294 value = gba->bus; \
295 } else { \
296 value = cpu->prefetch[1]; \
297 if (cpu->executionMode == MODE_THUMB) { \
298 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
299 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
300 case REGION_BIOS: \
301 case REGION_OAM: \
302 /* This isn't right half the time, but we don't have $+6 handy */ \
303 value <<= 16; \
304 value |= cpu->prefetch[0]; \
305 break; \
306 case REGION_WORKING_IRAM: \
307 /* This doesn't handle prefetch clobbering */ \
308 if (cpu->gprs[ARM_PC] & 2) { \
309 value |= cpu->prefetch[0] << 16; \
310 } else { \
311 value <<= 16; \
312 value |= cpu->prefetch[0]; \
313 } \
314 default: \
315 value |= value << 16; \
316 } \
317 } \
318 }
319
320#define LOAD_BIOS \
321 if (address < SIZE_BIOS) { \
322 if (memory->activeRegion == REGION_BIOS) { \
323 LOAD_32(value, address, memory->bios); \
324 } else { \
325 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
326 value = memory->biosPrefetch; \
327 } \
328 } else { \
329 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
330 LOAD_BAD; \
331 }
332
333#define LOAD_WORKING_RAM \
334 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
335 wait += waitstatesRegion[REGION_WORKING_RAM];
336
337#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
338#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
339
340#define LOAD_PALETTE_RAM \
341 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
342 wait += waitstatesRegion[REGION_PALETTE_RAM];
343
344#define LOAD_VRAM \
345 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
346 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
347 } else { \
348 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
349 } \
350 wait += waitstatesRegion[REGION_VRAM];
351
352#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
353
354#define LOAD_CART \
355 wait += waitstatesRegion[address >> BASE_OFFSET]; \
356 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
357 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
358 } else { \
359 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
360 value = (address >> 1) & 0xFFFF; \
361 value |= ((address + 2) >> 1) << 16; \
362 }
363
364#define LOAD_SRAM \
365 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
366 value = GBALoad8(cpu, address, 0); \
367 value |= value << 8; \
368 value |= value << 16;
369
370uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
371 struct GBA* gba = (struct GBA*) cpu->master;
372 struct GBAMemory* memory = &gba->memory;
373 uint32_t value = 0;
374 int wait = 0;
375 char* waitstatesRegion = memory->waitstatesNonseq32;
376
377 switch (address >> BASE_OFFSET) {
378 case REGION_BIOS:
379 LOAD_BIOS;
380 break;
381 case REGION_WORKING_RAM:
382 LOAD_WORKING_RAM;
383 break;
384 case REGION_WORKING_IRAM:
385 LOAD_WORKING_IRAM;
386 break;
387 case REGION_IO:
388 LOAD_IO;
389 break;
390 case REGION_PALETTE_RAM:
391 LOAD_PALETTE_RAM;
392 break;
393 case REGION_VRAM:
394 LOAD_VRAM;
395 break;
396 case REGION_OAM:
397 LOAD_OAM;
398 break;
399 case REGION_CART0:
400 case REGION_CART0_EX:
401 case REGION_CART1:
402 case REGION_CART1_EX:
403 case REGION_CART2:
404 case REGION_CART2_EX:
405 LOAD_CART;
406 break;
407 case REGION_CART_SRAM:
408 case REGION_CART_SRAM_MIRROR:
409 LOAD_SRAM;
410 break;
411 default:
412 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
413 LOAD_BAD;
414 break;
415 }
416
417 if (cycleCounter) {
418 wait += 2;
419 if (address >> BASE_OFFSET < REGION_CART0) {
420 wait = GBAMemoryStall(cpu, wait);
421 }
422 *cycleCounter += wait;
423 }
424 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
425 int rotate = (address & 3) << 3;
426 return ROR(value, rotate);
427}
428
429uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
430 struct GBA* gba = (struct GBA*) cpu->master;
431 struct GBAMemory* memory = &gba->memory;
432 uint32_t value = 0;
433 int wait = 0;
434
435 switch (address >> BASE_OFFSET) {
436 case REGION_BIOS:
437 if (address < SIZE_BIOS) {
438 if (memory->activeRegion == REGION_BIOS) {
439 LOAD_16(value, address, memory->bios);
440 } else {
441 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
442 LOAD_16(value, address & 2, &memory->biosPrefetch);
443 }
444 } else {
445 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
446 LOAD_BAD;
447 uint32_t v2 = value;
448 LOAD_16(value, address & 2, &v2);
449 }
450 break;
451 case REGION_WORKING_RAM:
452 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
453 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
454 break;
455 case REGION_WORKING_IRAM:
456 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
457 break;
458 case REGION_IO:
459 value = GBAIORead(gba, address & (SIZE_IO - 2));
460 break;
461 case REGION_PALETTE_RAM:
462 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
463 break;
464 case REGION_VRAM:
465 if ((address & 0x0001FFFF) < SIZE_VRAM) {
466 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
467 } else {
468 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
469 }
470 break;
471 case REGION_OAM:
472 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
473 break;
474 case REGION_CART0:
475 case REGION_CART0_EX:
476 case REGION_CART1:
477 case REGION_CART1_EX:
478 case REGION_CART2:
479 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
480 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
481 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
482 } else {
483 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
484 value = (address >> 1) & 0xFFFF; \
485 }
486 break;
487 case REGION_CART2_EX:
488 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
489 if (memory->savedata.type == SAVEDATA_EEPROM) {
490 value = GBASavedataReadEEPROM(&memory->savedata);
491 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
492 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
493 } else {
494 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
495 value = (address >> 1) & 0xFFFF; \
496 }
497 break;
498 case REGION_CART_SRAM:
499 case REGION_CART_SRAM_MIRROR:
500 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
501 value = GBALoad8(cpu, address, 0);
502 value |= value << 8;
503 break;
504 default:
505 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
506 LOAD_BAD;
507 uint32_t v2 = value;
508 LOAD_16(value, address & 2, &v2);
509 break;
510 }
511
512 if (cycleCounter) {
513 wait += 2;
514 if (address >> BASE_OFFSET < REGION_CART0) {
515 wait = GBAMemoryStall(cpu, wait);
516 }
517 *cycleCounter += wait;
518 }
519 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
520 int rotate = (address & 1) << 3;
521 return ROR(value, rotate);
522}
523
524uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
525 struct GBA* gba = (struct GBA*) cpu->master;
526 struct GBAMemory* memory = &gba->memory;
527 uint32_t value = 0;
528 int wait = 0;
529
530 switch (address >> BASE_OFFSET) {
531 case REGION_BIOS:
532 if (address < SIZE_BIOS) {
533 if (memory->activeRegion == REGION_BIOS) {
534 value = ((uint8_t*) memory->bios)[address];
535 } else {
536 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
537 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
538 }
539 } else {
540 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
541 LOAD_BAD;
542 value = ((uint8_t*) &value)[address & 3];
543 }
544 break;
545 case REGION_WORKING_RAM:
546 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
547 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
548 break;
549 case REGION_WORKING_IRAM:
550 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
551 break;
552 case REGION_IO:
553 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
554 break;
555 case REGION_PALETTE_RAM:
556 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
557 break;
558 case REGION_VRAM:
559 if ((address & 0x0001FFFF) < SIZE_VRAM) {
560 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
561 } else {
562 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
563 }
564 break;
565 case REGION_OAM:
566 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
567 break;
568 case REGION_CART0:
569 case REGION_CART0_EX:
570 case REGION_CART1:
571 case REGION_CART1_EX:
572 case REGION_CART2:
573 case REGION_CART2_EX:
574 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
575 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
576 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
577 } else {
578 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
579 value = (address >> 1) & 0xFF; \
580 }
581 break;
582 case REGION_CART_SRAM:
583 case REGION_CART_SRAM_MIRROR:
584 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
585 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
586 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
587 GBASavedataInitSRAM(&memory->savedata);
588 }
589 if (memory->savedata.type == SAVEDATA_SRAM) {
590 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
591 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
592 value = GBASavedataReadFlash(&memory->savedata, address);
593 } else if (memory->hw.devices & HW_TILT) {
594 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
595 } else {
596 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
597 value = 0xFF;
598 }
599 value &= 0xFF;
600 break;
601 default:
602 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
603 LOAD_BAD;
604 value = ((uint8_t*) &value)[address & 3];
605 break;
606 }
607
608 if (cycleCounter) {
609 wait += 2;
610 if (address >> BASE_OFFSET < REGION_CART0) {
611 wait = GBAMemoryStall(cpu, wait);
612 }
613 *cycleCounter += wait;
614 }
615 return value;
616}
617
618#define STORE_WORKING_RAM \
619 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
620 wait += waitstatesRegion[REGION_WORKING_RAM];
621
622#define STORE_WORKING_IRAM \
623 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
624
625#define STORE_IO \
626 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
627
628#define STORE_PALETTE_RAM \
629 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
630 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
631 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
632 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
633
634#define STORE_VRAM \
635 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
636 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
637 } else { \
638 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
639 } \
640 wait += waitstatesRegion[REGION_VRAM];
641
642#define STORE_OAM \
643 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
644 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
645 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
646
647#define STORE_CART \
648 wait += waitstatesRegion[address >> BASE_OFFSET]; \
649 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
650
651#define STORE_SRAM \
652 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
653
654#define STORE_BAD \
655 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
656
657void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
658 struct GBA* gba = (struct GBA*) cpu->master;
659 struct GBAMemory* memory = &gba->memory;
660 int wait = 0;
661 char* waitstatesRegion = memory->waitstatesNonseq32;
662
663 switch (address >> BASE_OFFSET) {
664 case REGION_WORKING_RAM:
665 STORE_WORKING_RAM;
666 break;
667 case REGION_WORKING_IRAM:
668 STORE_WORKING_IRAM
669 break;
670 case REGION_IO:
671 STORE_IO;
672 break;
673 case REGION_PALETTE_RAM:
674 STORE_PALETTE_RAM;
675 break;
676 case REGION_VRAM:
677 STORE_VRAM;
678 break;
679 case REGION_OAM:
680 STORE_OAM;
681 break;
682 case REGION_CART0:
683 case REGION_CART0_EX:
684 case REGION_CART1:
685 case REGION_CART1_EX:
686 case REGION_CART2:
687 case REGION_CART2_EX:
688 STORE_CART;
689 break;
690 case REGION_CART_SRAM:
691 case REGION_CART_SRAM_MIRROR:
692 STORE_SRAM;
693 break;
694 default:
695 STORE_BAD;
696 break;
697 }
698
699 if (cycleCounter) {
700 ++wait;
701 if (address >> BASE_OFFSET < REGION_CART0) {
702 wait = GBAMemoryStall(cpu, wait);
703 }
704 *cycleCounter += wait;
705 }
706}
707
708void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
709 struct GBA* gba = (struct GBA*) cpu->master;
710 struct GBAMemory* memory = &gba->memory;
711 int wait = 0;
712
713 switch (address >> BASE_OFFSET) {
714 case REGION_WORKING_RAM:
715 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
716 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
717 break;
718 case REGION_WORKING_IRAM:
719 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
720 break;
721 case REGION_IO:
722 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
723 break;
724 case REGION_PALETTE_RAM:
725 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
726 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
727 break;
728 case REGION_VRAM:
729 if ((address & 0x0001FFFF) < SIZE_VRAM) {
730 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
731 } else {
732 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
733 }
734 break;
735 case REGION_OAM:
736 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
737 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
738 break;
739 case REGION_CART0:
740 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
741 uint32_t reg = address & 0xFFFFFE;
742 GBAHardwareGPIOWrite(&memory->hw, reg, value);
743 } else {
744 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
745 }
746 break;
747 case REGION_CART2_EX:
748 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
749 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
750 GBASavedataInitEEPROM(&memory->savedata);
751 }
752 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
753 break;
754 case REGION_CART_SRAM:
755 case REGION_CART_SRAM_MIRROR:
756 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
757 break;
758 default:
759 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
760 break;
761 }
762
763 if (cycleCounter) {
764 ++wait;
765 if (address >> BASE_OFFSET < REGION_CART0) {
766 wait = GBAMemoryStall(cpu, wait);
767 }
768 *cycleCounter += wait;
769 }
770}
771
772void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
773 struct GBA* gba = (struct GBA*) cpu->master;
774 struct GBAMemory* memory = &gba->memory;
775 int wait = 0;
776
777 switch (address >> BASE_OFFSET) {
778 case REGION_WORKING_RAM:
779 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
780 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
781 break;
782 case REGION_WORKING_IRAM:
783 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
784 break;
785 case REGION_IO:
786 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
787 break;
788 case REGION_PALETTE_RAM:
789 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
790 break;
791 case REGION_VRAM:
792 if (address >= 0x06018000) {
793 // TODO: check BG mode
794 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
795 break;
796 }
797 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
798 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
799 break;
800 case REGION_OAM:
801 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
802 break;
803 case REGION_CART0:
804 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
805 break;
806 case REGION_CART_SRAM:
807 case REGION_CART_SRAM_MIRROR:
808 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
809 if (address == SAVEDATA_FLASH_BASE) {
810 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
811 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
812 } else {
813 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
814 GBASavedataInitSRAM(&memory->savedata);
815 }
816 }
817 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
818 GBASavedataWriteFlash(&memory->savedata, address, value);
819 } else if (memory->savedata.type == SAVEDATA_SRAM) {
820 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
821 } else if (memory->hw.devices & HW_TILT) {
822 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
823 } else {
824 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
825 }
826 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
827 break;
828 default:
829 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
830 break;
831 }
832
833 if (cycleCounter) {
834 ++wait;
835 if (address >> BASE_OFFSET < REGION_CART0) {
836 wait = GBAMemoryStall(cpu, wait);
837 }
838 *cycleCounter += wait;
839 }
840}
841
842void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
843 struct GBA* gba = (struct GBA*) cpu->master;
844 struct GBAMemory* memory = &gba->memory;
845 int32_t oldValue = -1;
846
847 switch (address >> BASE_OFFSET) {
848 case REGION_WORKING_RAM:
849 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
850 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
851 break;
852 case REGION_WORKING_IRAM:
853 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
854 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
855 break;
856 case REGION_IO:
857 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
858 break;
859 case REGION_PALETTE_RAM:
860 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
861 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
862 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
863 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
864 break;
865 case REGION_VRAM:
866 if ((address & 0x0001FFFF) < SIZE_VRAM) {
867 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
868 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
869 } else {
870 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
871 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
872 }
873 break;
874 case REGION_OAM:
875 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
876 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
877 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
878 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
879 break;
880 case REGION_CART0:
881 case REGION_CART0_EX:
882 case REGION_CART1:
883 case REGION_CART1_EX:
884 case REGION_CART2:
885 case REGION_CART2_EX:
886 _pristineCow(gba);
887 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
888 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
889 }
890 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
891 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
892 break;
893 case REGION_CART_SRAM:
894 case REGION_CART_SRAM_MIRROR:
895 if (memory->savedata.type == SAVEDATA_SRAM) {
896 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
897 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
898 } else {
899 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
900 }
901 break;
902 default:
903 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
904 break;
905 }
906 if (old) {
907 *old = oldValue;
908 }
909}
910
911void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
912 struct GBA* gba = (struct GBA*) cpu->master;
913 struct GBAMemory* memory = &gba->memory;
914 int16_t oldValue = -1;
915
916 switch (address >> BASE_OFFSET) {
917 case REGION_WORKING_RAM:
918 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
919 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
920 break;
921 case REGION_WORKING_IRAM:
922 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
923 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
924 break;
925 case REGION_IO:
926 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
927 break;
928 case REGION_PALETTE_RAM:
929 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
930 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
931 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
932 break;
933 case REGION_VRAM:
934 if ((address & 0x0001FFFF) < SIZE_VRAM) {
935 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
936 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
937 } else {
938 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
939 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
940 }
941 break;
942 case REGION_OAM:
943 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
944 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
945 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
946 break;
947 case REGION_CART0:
948 case REGION_CART0_EX:
949 case REGION_CART1:
950 case REGION_CART1_EX:
951 case REGION_CART2:
952 case REGION_CART2_EX:
953 _pristineCow(gba);
954 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
955 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
956 }
957 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
958 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
959 break;
960 case REGION_CART_SRAM:
961 case REGION_CART_SRAM_MIRROR:
962 if (memory->savedata.type == SAVEDATA_SRAM) {
963 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
964 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
965 } else {
966 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
967 }
968 break;
969 default:
970 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
971 break;
972 }
973 if (old) {
974 *old = oldValue;
975 }
976}
977
978void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
979 struct GBA* gba = (struct GBA*) cpu->master;
980 struct GBAMemory* memory = &gba->memory;
981 int8_t oldValue = -1;
982
983 switch (address >> BASE_OFFSET) {
984 case REGION_WORKING_RAM:
985 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
986 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
987 break;
988 case REGION_WORKING_IRAM:
989 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
990 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
991 break;
992 case REGION_IO:
993 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
994 break;
995 case REGION_PALETTE_RAM:
996 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
997 break;
998 case REGION_VRAM:
999 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1000 break;
1001 case REGION_OAM:
1002 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1003 break;
1004 case REGION_CART0:
1005 case REGION_CART0_EX:
1006 case REGION_CART1:
1007 case REGION_CART1_EX:
1008 case REGION_CART2:
1009 case REGION_CART2_EX:
1010 _pristineCow(gba);
1011 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1012 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1013 }
1014 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1015 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1016 break;
1017 case REGION_CART_SRAM:
1018 case REGION_CART_SRAM_MIRROR:
1019 if (memory->savedata.type == SAVEDATA_SRAM) {
1020 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1021 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1022 } else {
1023 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1024 }
1025 break;
1026 default:
1027 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1028 break;
1029 }
1030 if (old) {
1031 *old = oldValue;
1032 }
1033}
1034
1035#define LDM_LOOP(LDM) \
1036 for (i = 0; i < 16; i += 4) { \
1037 if (UNLIKELY(mask & (1 << i))) { \
1038 LDM; \
1039 waitstatesRegion = memory->waitstatesSeq32; \
1040 cpu->gprs[i] = value; \
1041 ++wait; \
1042 address += 4; \
1043 } \
1044 if (UNLIKELY(mask & (2 << i))) { \
1045 LDM; \
1046 waitstatesRegion = memory->waitstatesSeq32; \
1047 cpu->gprs[i + 1] = value; \
1048 ++wait; \
1049 address += 4; \
1050 } \
1051 if (UNLIKELY(mask & (4 << i))) { \
1052 LDM; \
1053 waitstatesRegion = memory->waitstatesSeq32; \
1054 cpu->gprs[i + 2] = value; \
1055 ++wait; \
1056 address += 4; \
1057 } \
1058 if (UNLIKELY(mask & (8 << i))) { \
1059 LDM; \
1060 waitstatesRegion = memory->waitstatesSeq32; \
1061 cpu->gprs[i + 3] = value; \
1062 ++wait; \
1063 address += 4; \
1064 } \
1065 }
1066
1067uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1068 struct GBA* gba = (struct GBA*) cpu->master;
1069 struct GBAMemory* memory = &gba->memory;
1070 uint32_t value;
1071 int wait = 0;
1072 char* waitstatesRegion = memory->waitstatesNonseq32;
1073
1074 int i;
1075 int offset = 4;
1076 int popcount = 0;
1077 if (direction & LSM_D) {
1078 offset = -4;
1079 popcount = _popcount32(mask);
1080 address -= (popcount << 2) - 4;
1081 }
1082
1083 if (direction & LSM_B) {
1084 address += offset;
1085 }
1086
1087 uint32_t addressMisalign = address & 0x3;
1088 address &= 0xFFFFFFFC;
1089
1090 switch (address >> BASE_OFFSET) {
1091 case REGION_BIOS:
1092 LDM_LOOP(LOAD_BIOS);
1093 break;
1094 case REGION_WORKING_RAM:
1095 LDM_LOOP(LOAD_WORKING_RAM);
1096 break;
1097 case REGION_WORKING_IRAM:
1098 LDM_LOOP(LOAD_WORKING_IRAM);
1099 break;
1100 case REGION_IO:
1101 LDM_LOOP(LOAD_IO);
1102 break;
1103 case REGION_PALETTE_RAM:
1104 LDM_LOOP(LOAD_PALETTE_RAM);
1105 break;
1106 case REGION_VRAM:
1107 LDM_LOOP(LOAD_VRAM);
1108 break;
1109 case REGION_OAM:
1110 LDM_LOOP(LOAD_OAM);
1111 break;
1112 case REGION_CART0:
1113 case REGION_CART0_EX:
1114 case REGION_CART1:
1115 case REGION_CART1_EX:
1116 case REGION_CART2:
1117 case REGION_CART2_EX:
1118 LDM_LOOP(LOAD_CART);
1119 break;
1120 case REGION_CART_SRAM:
1121 case REGION_CART_SRAM_MIRROR:
1122 LDM_LOOP(LOAD_SRAM);
1123 break;
1124 default:
1125 LDM_LOOP(LOAD_BAD);
1126 break;
1127 }
1128
1129 if (cycleCounter) {
1130 ++wait;
1131 if (address >> BASE_OFFSET < REGION_CART0) {
1132 wait = GBAMemoryStall(cpu, wait);
1133 }
1134 *cycleCounter += wait;
1135 }
1136
1137 if (direction & LSM_B) {
1138 address -= offset;
1139 }
1140
1141 if (direction & LSM_D) {
1142 address -= (popcount << 2) + 4;
1143 }
1144
1145 return address | addressMisalign;
1146}
1147
1148#define STM_LOOP(STM) \
1149 for (i = 0; i < 16; i += 4) { \
1150 if (UNLIKELY(mask & (1 << i))) { \
1151 value = cpu->gprs[i]; \
1152 STM; \
1153 waitstatesRegion = memory->waitstatesSeq32; \
1154 ++wait; \
1155 address += 4; \
1156 } \
1157 if (UNLIKELY(mask & (2 << i))) { \
1158 value = cpu->gprs[i + 1]; \
1159 STM; \
1160 waitstatesRegion = memory->waitstatesSeq32; \
1161 ++wait; \
1162 address += 4; \
1163 } \
1164 if (UNLIKELY(mask & (4 << i))) { \
1165 value = cpu->gprs[i + 2]; \
1166 STM; \
1167 waitstatesRegion = memory->waitstatesSeq32; \
1168 ++wait; \
1169 address += 4; \
1170 } \
1171 if (UNLIKELY(mask & (8 << i))) { \
1172 value = cpu->gprs[i + 3]; \
1173 STM; \
1174 waitstatesRegion = memory->waitstatesSeq32; \
1175 ++wait; \
1176 address += 4; \
1177 } \
1178 }
1179
1180uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1181 struct GBA* gba = (struct GBA*) cpu->master;
1182 struct GBAMemory* memory = &gba->memory;
1183 uint32_t value;
1184 int wait = 0;
1185 char* waitstatesRegion = memory->waitstatesNonseq32;
1186
1187 int i;
1188 int offset = 4;
1189 int popcount = 0;
1190 if (direction & LSM_D) {
1191 offset = -4;
1192 popcount = _popcount32(mask);
1193 address -= (popcount << 2) - 4;
1194 }
1195
1196 if (direction & LSM_B) {
1197 address += offset;
1198 }
1199
1200 uint32_t addressMisalign = address & 0x3;
1201 address &= 0xFFFFFFFC;
1202
1203 switch (address >> BASE_OFFSET) {
1204 case REGION_WORKING_RAM:
1205 STM_LOOP(STORE_WORKING_RAM);
1206 break;
1207 case REGION_WORKING_IRAM:
1208 STM_LOOP(STORE_WORKING_IRAM);
1209 break;
1210 case REGION_IO:
1211 STM_LOOP(STORE_IO);
1212 break;
1213 case REGION_PALETTE_RAM:
1214 STM_LOOP(STORE_PALETTE_RAM);
1215 break;
1216 case REGION_VRAM:
1217 STM_LOOP(STORE_VRAM);
1218 break;
1219 case REGION_OAM:
1220 STM_LOOP(STORE_OAM);
1221 break;
1222 case REGION_CART0:
1223 case REGION_CART0_EX:
1224 case REGION_CART1:
1225 case REGION_CART1_EX:
1226 case REGION_CART2:
1227 case REGION_CART2_EX:
1228 STM_LOOP(STORE_CART);
1229 break;
1230 case REGION_CART_SRAM:
1231 case REGION_CART_SRAM_MIRROR:
1232 STM_LOOP(STORE_SRAM);
1233 break;
1234 default:
1235 STM_LOOP(STORE_BAD);
1236 break;
1237 }
1238
1239 if (cycleCounter) {
1240 if (address >> BASE_OFFSET < REGION_CART0) {
1241 wait = GBAMemoryStall(cpu, wait);
1242 }
1243 *cycleCounter += wait;
1244 }
1245
1246 if (direction & LSM_B) {
1247 address -= offset;
1248 }
1249
1250 if (direction & LSM_D) {
1251 address -= (popcount << 2) + 4;
1252 }
1253
1254 return address | addressMisalign;
1255}
1256
1257void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1258 struct GBAMemory* memory = &gba->memory;
1259 struct ARMCore* cpu = gba->cpu;
1260 int sram = parameters & 0x0003;
1261 int ws0 = (parameters & 0x000C) >> 2;
1262 int ws0seq = (parameters & 0x0010) >> 4;
1263 int ws1 = (parameters & 0x0060) >> 5;
1264 int ws1seq = (parameters & 0x0080) >> 7;
1265 int ws2 = (parameters & 0x0300) >> 8;
1266 int ws2seq = (parameters & 0x0400) >> 10;
1267 int prefetch = parameters & 0x4000;
1268
1269 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1270 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1271 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1272 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1273
1274 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1275 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1276 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1277
1278 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1279 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1280 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1281
1282 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1283 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1284 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1285
1286 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1287 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1288 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1289
1290 memory->prefetch = prefetch;
1291
1292 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1293 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1294
1295 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1296 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1297}
1298
1299void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1300 struct GBAMemory* memory = &gba->memory;
1301 memory->dma[dma].source = address & 0x0FFFFFFE;
1302}
1303
1304void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1305 struct GBAMemory* memory = &gba->memory;
1306 memory->dma[dma].dest = address & 0x0FFFFFFE;
1307}
1308
1309void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1310 struct GBAMemory* memory = &gba->memory;
1311 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1312}
1313
1314uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1315 struct GBAMemory* memory = &gba->memory;
1316 struct GBADMA* currentDma = &memory->dma[dma];
1317 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1318 currentDma->reg = control;
1319
1320 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1321 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1322 }
1323
1324 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1325 currentDma->nextSource = currentDma->source;
1326 currentDma->nextDest = currentDma->dest;
1327 currentDma->nextCount = currentDma->count;
1328 GBAMemoryScheduleDMA(gba, dma, currentDma);
1329 }
1330 // If the DMA has already occurred, this value might have changed since the function started
1331 return currentDma->reg;
1332};
1333
1334void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1335 struct ARMCore* cpu = gba->cpu;
1336 switch (GBADMARegisterGetTiming(info->reg)) {
1337 case DMA_TIMING_NOW:
1338 info->nextEvent = cpu->cycles;
1339 GBAMemoryUpdateDMAs(gba, 0);
1340 break;
1341 case DMA_TIMING_HBLANK:
1342 // Handled implicitly
1343 info->nextEvent = INT_MAX;
1344 break;
1345 case DMA_TIMING_VBLANK:
1346 // Handled implicitly
1347 info->nextEvent = INT_MAX;
1348 break;
1349 case DMA_TIMING_CUSTOM:
1350 info->nextEvent = INT_MAX;
1351 switch (number) {
1352 case 0:
1353 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1354 break;
1355 case 1:
1356 case 2:
1357 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1358 break;
1359 case 3:
1360 // GBAVideoScheduleVCaptureDma(dma, info);
1361 break;
1362 }
1363 }
1364}
1365
1366void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1367 struct GBAMemory* memory = &gba->memory;
1368 struct GBADMA* dma;
1369 int i;
1370 for (i = 0; i < 4; ++i) {
1371 dma = &memory->dma[i];
1372 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1373 dma->nextEvent = cycles;
1374 }
1375 }
1376 GBAMemoryUpdateDMAs(gba, 0);
1377}
1378
1379void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1380 struct GBAMemory* memory = &gba->memory;
1381 struct GBADMA* dma;
1382 int i;
1383 for (i = 0; i < 4; ++i) {
1384 dma = &memory->dma[i];
1385 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1386 dma->nextEvent = cycles;
1387 }
1388 }
1389 GBAMemoryUpdateDMAs(gba, 0);
1390}
1391
1392int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1393 struct GBAMemory* memory = &gba->memory;
1394 if (memory->nextDMA == INT_MAX) {
1395 return INT_MAX;
1396 }
1397 memory->nextDMA -= cycles;
1398 memory->eventDiff += cycles;
1399 if (memory->nextDMA <= 0) {
1400 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1401 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1402 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1403 memory->eventDiff = 0;
1404 }
1405 return memory->nextDMA;
1406}
1407
1408void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1409 int i;
1410 struct GBAMemory* memory = &gba->memory;
1411 struct ARMCore* cpu = gba->cpu;
1412 memory->activeDMA = -1;
1413 memory->nextDMA = INT_MAX;
1414 for (i = 3; i >= 0; --i) {
1415 struct GBADMA* dma = &memory->dma[i];
1416 if (dma->nextEvent != INT_MAX) {
1417 dma->nextEvent -= cycles;
1418 if (GBADMARegisterIsEnable(dma->reg)) {
1419 memory->activeDMA = i;
1420 memory->nextDMA = dma->nextEvent;
1421 }
1422 }
1423 }
1424 if (memory->nextDMA < cpu->nextEvent) {
1425 cpu->nextEvent = memory->nextDMA;
1426 }
1427}
1428
1429void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1430 struct GBAMemory* memory = &gba->memory;
1431 struct ARMCore* cpu = gba->cpu;
1432 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1433 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1434 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1435 int32_t wordsRemaining = info->nextCount;
1436 uint32_t source = info->nextSource;
1437 uint32_t dest = info->nextDest;
1438 uint32_t sourceRegion = source >> BASE_OFFSET;
1439 uint32_t destRegion = dest >> BASE_OFFSET;
1440 int32_t cycles = 2;
1441
1442 if (source == info->source) {
1443 // TODO: support 4 cycles for ROM access
1444 cycles += 2;
1445 if (width == 4) {
1446 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1447 source &= 0xFFFFFFFC;
1448 dest &= 0xFFFFFFFC;
1449 } else {
1450 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1451 }
1452 } else {
1453 if (width == 4) {
1454 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1455 } else {
1456 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1457 }
1458 }
1459
1460 gba->performingDMA = true;
1461 int32_t word;
1462 if (width == 4) {
1463 word = cpu->memory.load32(cpu, source, 0);
1464 gba->bus = word;
1465 cpu->memory.store32(cpu, dest, word, 0);
1466 source += sourceOffset;
1467 dest += destOffset;
1468 --wordsRemaining;
1469 } else {
1470 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1471 word = GBASavedataReadEEPROM(&memory->savedata);
1472 gba->bus = word | (word << 16);
1473 cpu->memory.store16(cpu, dest, word, 0);
1474 source += sourceOffset;
1475 dest += destOffset;
1476 --wordsRemaining;
1477 } else if (destRegion == REGION_CART2_EX) {
1478 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1479 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1480 GBASavedataInitEEPROM(&memory->savedata);
1481 }
1482 word = cpu->memory.load16(cpu, source, 0);
1483 gba->bus = word | (word << 16);
1484 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1485 source += sourceOffset;
1486 dest += destOffset;
1487 --wordsRemaining;
1488 } else {
1489 word = cpu->memory.load16(cpu, source, 0);
1490 gba->bus = word | (word << 16);
1491 cpu->memory.store16(cpu, dest, word, 0);
1492 source += sourceOffset;
1493 dest += destOffset;
1494 --wordsRemaining;
1495 }
1496 }
1497 gba->performingDMA = false;
1498
1499 if (!wordsRemaining) {
1500 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1501 info->reg = GBADMARegisterClearEnable(info->reg);
1502 info->nextEvent = INT_MAX;
1503
1504 // Clear the enable bit in memory
1505 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1506 } else {
1507 info->nextCount = info->count;
1508 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1509 info->nextDest = info->dest;
1510 }
1511 GBAMemoryScheduleDMA(gba, number, info);
1512 }
1513 if (GBADMARegisterIsDoIRQ(info->reg)) {
1514 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1515 }
1516 } else {
1517 info->nextDest = dest;
1518 info->nextCount = wordsRemaining;
1519 }
1520 info->nextSource = source;
1521
1522 if (info->nextEvent != INT_MAX) {
1523 info->nextEvent += cycles;
1524 }
1525 cpu->cycles += cycles;
1526}
1527
1528int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1529 struct GBA* gba = (struct GBA*) cpu->master;
1530 struct GBAMemory* memory = &gba->memory;
1531
1532 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1533 // The wait is the stall
1534 return wait;
1535 }
1536
1537 int32_t s = cpu->memory.activeSeqCycles16 + 1;
1538 int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
1539
1540 // Figure out how many sequential loads we can jam in
1541 int32_t stall = s;
1542 int32_t loads = 1;
1543 int32_t previousLoads = 0;
1544
1545 // Don't prefetch too much if we're overlapping with a previous prefetch
1546 uint32_t dist = (memory->lastPrefetchedPc - cpu->gprs[ARM_PC]) >> 1;
1547 if (dist < memory->lastPrefetchedLoads) {
1548 previousLoads = dist;
1549 }
1550 while (stall < wait) {
1551 stall += s;
1552 ++loads;
1553 }
1554 if (loads + previousLoads > 8) {
1555 int diff = (loads + previousLoads) - 8;
1556 loads -= diff;
1557 stall -= s * diff;
1558 } else if (stall > wait && loads == 1) {
1559 // We might need to stall a bit extra if we haven't finished the first S cycle
1560 wait = stall;
1561 }
1562 // This instruction used to have an N, convert it to an S.
1563 wait -= n2s;
1564
1565 // TODO: Invalidate prefetch on branch
1566 memory->lastPrefetchedLoads = loads;
1567 memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * loads;
1568
1569 // The next |loads|S waitstates disappear entirely, so long as they're all in a row
1570 cpu->cycles -= (s - 1) * loads;
1571 return wait;
1572}
1573
1574void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1575 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1576 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1577}
1578
1579void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1580 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1581 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1582}
1583
1584uint32_t _popcount32(unsigned bits) {
1585 bits = bits - ((bits >> 1) & 0x55555555);
1586 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1587 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1588}
1589
1590void _pristineCow(struct GBA* gba) {
1591 if (gba->memory.rom != gba->pristineRom) {
1592 return;
1593 }
1594 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1595 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1596 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1597}