src/arm/decoder-arm.c (view raw)
1#include "decoder.h"
2
3#include "decoder-inlines.h"
4#include "emitter-arm.h"
5#include "isa-inlines.h"
6
7#define ADDR_MODE_1_SHIFT(OP) \
8 info->op3.reg = opcode & 0x0000000F; \
9 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
10 info->op3.shifterImm = (opcode >> 7) & 0x1F; \
11 info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
12 ARM_OPERAND_SHIFT_IMMEDIATE_3;
13
14#define ADDR_MODE_1_SHIFTR(OP) \
15 info->op3.reg = opcode & 0x0000000F; \
16 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
17 info->op3.shifterReg = (opcode >> 8) & 0xF; \
18 ++info->iCycles; \
19 info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
20 ARM_OPERAND_SHIFT_REGISTER_3;
21
22#define ADDR_MODE_1_LSL \
23 ADDR_MODE_1_SHIFT(LSL) \
24 if (!info->op3.shifterImm) { \
25 info->operandFormat &= ~ARM_OPERAND_SHIFT_REGISTER_3; \
26 info->op3.shifterOp = ARM_SHIFT_NONE; \
27 }
28
29#define ADDR_MODE_1_LSR ADDR_MODE_1_SHIFT(LSR)
30#define ADDR_MODE_1_ASR ADDR_MODE_1_SHIFT(ASR)
31#define ADDR_MODE_1_ROR \
32 ADDR_MODE_1_SHIFT(ROR) \
33 if (!info->op3.shifterImm) { \
34 info->op3.shifterOp = ARM_SHIFT_RRX; \
35 }
36
37#define ADDR_MODE_1_LSLR ADDR_MODE_1_SHIFTR(LSL)
38#define ADDR_MODE_1_LSRR ADDR_MODE_1_SHIFTR(LSR)
39#define ADDR_MODE_1_ASRR ADDR_MODE_1_SHIFTR(ASR)
40#define ADDR_MODE_1_RORR ADDR_MODE_1_SHIFTR(ROR)
41
42#define ADDR_MODE_1_IMM \
43 int rotate = (opcode & 0x00000F00) >> 7; \
44 int immediate = opcode & 0x000000FF; \
45 info->op3.immediate = ARM_ROR(immediate, rotate); \
46 info->operandFormat |= ARM_OPERAND_IMMEDIATE_3;
47
48#define ADDR_MODE_2_SHIFT(OP) \
49 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET | ARM_MEMORY_SHIFTED_OFFSET; \
50 info->memory.offset.shifterOp = ARM_SHIFT_ ## OP; \
51 info->memory.offset.shifterImm = (opcode >> 7) & 0x1F; \
52 info->memory.offset.reg = opcode & 0x0000000F;
53
54#define ADDR_MODE_2_LSL \
55 ADDR_MODE_2_SHIFT(LSL) \
56 if (!info->memory.offset.shifterImm) { \
57 info->memory.format &= ~ARM_MEMORY_SHIFTED_OFFSET; \
58 info->memory.offset.shifterOp = ARM_SHIFT_NONE; \
59 }
60
61#define ADDR_MODE_2_LSR ADDR_MODE_2_SHIFT(LSR) \
62 if (!info->memory.offset.shifterImm) { \
63 info->memory.offset.shifterImm = 32; \
64 }
65
66#define ADDR_MODE_2_ASR ADDR_MODE_2_SHIFT(ASR) \
67 if (!info->memory.offset.shifterImm) { \
68 info->memory.offset.shifterImm = 32; \
69 }
70
71#define ADDR_MODE_2_ROR \
72 ADDR_MODE_2_SHIFT(ROR) \
73 if (!info->memory.offset.shifterImm) { \
74 info->memory.offset.shifterOp = ARM_SHIFT_RRX; \
75 }
76
77#define ADDR_MODE_2_IMM \
78 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
79 info->memory.offset.immediate = opcode & 0x00000FFF;
80
81#define ADDR_MODE_3_REG \
82 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET; \
83 info->memory.offset.reg = opcode & 0x0000000F;
84
85#define ADDR_MODE_3_IMM \
86 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
87 info->memory.offset.immediate = (opcode & 0x0000000F) | ((opcode & 0x00000F00) >> 4);
88
89#define DEFINE_DECODER_ARM(NAME, MNEMONIC, BODY) \
90 static void _ARMDecode ## NAME (uint32_t opcode, struct ARMInstructionInfo* info) { \
91 UNUSED(opcode); \
92 info->mnemonic = ARM_MN_ ## MNEMONIC; \
93 BODY; \
94 }
95
96#define DEFINE_ALU_DECODER_EX_ARM(NAME, MNEMONIC, S, SHIFTER, OTHER_AFFECTED, SKIPPED) \
97 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
98 info->op1.reg = (opcode >> 12) & 0xF; \
99 info->op2.reg = (opcode >> 16) & 0xF; \
100 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
101 OTHER_AFFECTED | \
102 ARM_OPERAND_REGISTER_2; \
103 info->affectsCPSR = S; \
104 SHIFTER; \
105 if (SKIPPED == 1) { \
106 info->operandFormat &= ~ARM_OPERAND_1; \
107 } else if (SKIPPED == 2) { \
108 info->operandFormat &= ~ARM_OPERAND_2; \
109 } \
110 if (info->op1.reg == ARM_PC) { \
111 info->branches = 1; \
112 })
113
114#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
115 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
116 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
117 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 0, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
118 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
119 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
120 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
121 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 0, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
122 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
123 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
124 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
125 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 0, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
126 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
127 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
128 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
129 DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 0, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
130 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
131 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
132 DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
133
134#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
135 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
136 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_NONE, 1) \
137 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
138 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_NONE, 1) \
139 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
140 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_NONE, 1) \
141 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
142 DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_NONE, 1) \
143 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
144
145#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
146 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
147 info->op1.reg = (opcode >> 16) & 0xF; \
148 info->op2.reg = opcode & 0xF; \
149 info->op3.reg = (opcode >> 8) & 0xF; \
150 info->op4.reg = (opcode >> 12) & 0xF; \
151 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
152 ARM_OPERAND_AFFECTED_1 | \
153 ARM_OPERAND_REGISTER_2 | \
154 ARM_OPERAND_REGISTER_3 | \
155 OTHER_AFFECTED; \
156 info->affectsCPSR = S; \
157 if (info->op1.reg == ARM_PC) { \
158 info->branches = 1; \
159 })
160
161#define DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S) \
162 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
163 info->op1.reg = (opcode >> 12) & 0xF; \
164 info->op2.reg = (opcode >> 16) & 0xF; \
165 info->op3.reg = opcode & 0xF; \
166 info->op4.reg = (opcode >> 8) & 0xF; \
167 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
168 ARM_OPERAND_AFFECTED_1 | \
169 ARM_OPERAND_REGISTER_2 | \
170 ARM_OPERAND_AFFECTED_2 | \
171 ARM_OPERAND_REGISTER_3 | \
172 ARM_OPERAND_REGISTER_4; \
173 info->affectsCPSR = S; \
174 if (info->op1.reg == ARM_PC) { \
175 info->branches = 1; \
176 })
177
178#define DEFINE_MULTIPLY_DECODER_ARM(NAME, OTHER_AFFECTED) \
179 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0, OTHER_AFFECTED) \
180 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1, OTHER_AFFECTED)
181
182#define DEFINE_LONG_MULTIPLY_DECODER_ARM(NAME) \
183 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0) \
184 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1)
185
186#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE) \
187 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
188 info->op1.reg = (opcode >> 12) & 0xF; \
189 info->memory.baseReg = (opcode >> 16) & 0xF; \
190 info->memory.width = TYPE; \
191 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
192 ARM_OPERAND_AFFECTED_1 | /* TODO: Remove this for STR */ \
193 ARM_OPERAND_MEMORY_2; \
194 info->memory.format = ARM_MEMORY_REGISTER_BASE | ADDRESSING_MODE; \
195 ADDRESSING_DECODING; \
196 CYCLES;)
197
198#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
199 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
200 ARM_MEMORY_POST_INCREMENT | \
201 ARM_MEMORY_WRITEBACK | \
202 ARM_MEMORY_OFFSET_SUBTRACT, \
203 ADDRESSING_MODE, CYCLES, TYPE) \
204 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
205 ARM_MEMORY_POST_INCREMENT | \
206 ARM_MEMORY_WRITEBACK, \
207 ADDRESSING_MODE, CYCLES, TYPE) \
208 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## P, MNEMONIC, \
209 ARM_MEMORY_PRE_INCREMENT | \
210 ARM_MEMORY_OFFSET_SUBTRACT, \
211 ADDRESSING_MODE, CYCLES, TYPE) \
212 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PW, MNEMONIC, \
213 ARM_MEMORY_PRE_INCREMENT | \
214 ARM_MEMORY_WRITEBACK | \
215 ARM_MEMORY_OFFSET_SUBTRACT, \
216 ADDRESSING_MODE, CYCLES, TYPE) \
217 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PU, MNEMONIC, \
218 ARM_MEMORY_PRE_INCREMENT, \
219 ADDRESSING_MODE, CYCLES, TYPE) \
220 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PUW, MNEMONIC, \
221 ARM_MEMORY_PRE_INCREMENT | \
222 ARM_MEMORY_WRITEBACK, \
223 ADDRESSING_MODE, CYCLES, TYPE)
224
225#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
226 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
227 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
228 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
229 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
230 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
231
232#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
233 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, CYCLES, TYPE) \
234 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, CYCLES, TYPE)
235
236#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
237 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
238 ARM_MEMORY_POST_INCREMENT | \
239 ARM_MEMORY_OFFSET_SUBTRACT, \
240 ADDRESSING_MODE, CYCLES, TYPE) \
241 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
242 ARM_MEMORY_POST_INCREMENT, \
243 ADDRESSING_MODE, CYCLES, TYPE)
244
245#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
246 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
247 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
248 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
249 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
250 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
251
252#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME, MNEMONIC, DIRECTION, WRITEBACK) \
253 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
254 info->memory.baseReg = (opcode >> 16) & 0xF; \
255 info->op1.immediate = opcode & 0x0000FFFF; \
256 info->branches = info->op1.immediate & (1 << ARM_PC); \
257 info->operandFormat = ARM_OPERAND_MEMORY_1; \
258 info->memory.format = ARM_MEMORY_REGISTER_BASE | \
259 ARM_MEMORY_WRITEBACK | \
260 ARM_MEMORY_ ## DIRECTION;)
261
262
263#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(NAME) \
264 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DA, NAME, DECREMENT_AFTER, 0) \
265 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
266 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DB, NAME, DECREMENT_BEFORE, 0) \
267 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
268 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IA, NAME, INCREMENT_AFTER, 0) \
269 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
270 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, 0) \
271 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
272 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, 0) \
273 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
274 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, 0) \
275 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
276 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, 0) \
277 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
278 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, 0) \
279 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK)
280
281#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
282 DEFINE_DECODER_ARM(NAME, SWP, \
283 info->memory.baseReg = (opcode >> 16) & 0xF; \
284 info->op1.reg = (opcode >> 12) & 0xF; \
285 info->op2.reg = opcode & 0xF; \
286 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
287 ARM_OPERAND_AFFECTED_1 | \
288 ARM_OPERAND_REGISTER_2 | \
289 ARM_OPERAND_MEMORY_3; \
290 info->memory.format = ARM_MEMORY_REGISTER_BASE; \
291 info->memory.width = TYPE;)
292
293DEFINE_ALU_DECODER_ARM(ADD, 0)
294DEFINE_ALU_DECODER_ARM(ADC, 0)
295DEFINE_ALU_DECODER_ARM(AND, 0)
296DEFINE_ALU_DECODER_ARM(BIC, 0)
297DEFINE_ALU_DECODER_S_ONLY_ARM(CMN)
298DEFINE_ALU_DECODER_S_ONLY_ARM(CMP)
299DEFINE_ALU_DECODER_ARM(EOR, 0)
300DEFINE_ALU_DECODER_ARM(MOV, 2)
301DEFINE_ALU_DECODER_ARM(MVN, 2)
302DEFINE_ALU_DECODER_ARM(ORR, 0)
303DEFINE_ALU_DECODER_ARM(RSB, 0)
304DEFINE_ALU_DECODER_ARM(RSC, 0)
305DEFINE_ALU_DECODER_ARM(SBC, 0)
306DEFINE_ALU_DECODER_ARM(SUB, 0)
307DEFINE_ALU_DECODER_S_ONLY_ARM(TEQ)
308DEFINE_ALU_DECODER_S_ONLY_ARM(TST)
309
310// TOOD: Estimate cycles
311DEFINE_MULTIPLY_DECODER_ARM(MLA, ARM_OPERAND_REGISTER_4)
312DEFINE_MULTIPLY_DECODER_ARM(MUL, ARM_OPERAND_NONE)
313
314DEFINE_LONG_MULTIPLY_DECODER_ARM(SMLAL)
315DEFINE_LONG_MULTIPLY_DECODER_ARM(SMULL)
316DEFINE_LONG_MULTIPLY_DECODER_ARM(UMLAL)
317DEFINE_LONG_MULTIPLY_DECODER_ARM(UMULL)
318
319// Begin load/store definitions
320
321DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
322DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
323DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
324DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
325DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
326DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE_CYCLES, ARM_ACCESS_WORD)
327DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
328DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
329
330DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
331DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
332DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
333DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
334
335DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(LDM)
336DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(STM)
337
338DEFINE_SWP_DECODER_ARM(SWP, ARM_ACCESS_WORD)
339DEFINE_SWP_DECODER_ARM(SWPB, ARM_ACCESS_BYTE)
340
341// End load/store definitions
342
343// Begin branch definitions
344
345DEFINE_DECODER_ARM(B, B,
346 int32_t offset = opcode << 8;
347 info->op1.immediate = offset >> 6;
348 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
349 info->branches = 1;)
350
351DEFINE_DECODER_ARM(BL, BL,
352 int32_t offset = opcode << 8;
353 info->op1.immediate = offset >> 6;
354 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
355 info->branches = 1;)
356
357DEFINE_DECODER_ARM(BX, BX,
358 info->op1.reg = opcode & 0x0000000F;
359 info->operandFormat = ARM_OPERAND_REGISTER_1;
360 info->branches = 1;)
361
362// End branch definitions
363
364// Begin coprocessor definitions
365
366DEFINE_DECODER_ARM(CDP, ILL, info->operandFormat = ARM_OPERAND_NONE;)
367DEFINE_DECODER_ARM(LDC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
368DEFINE_DECODER_ARM(STC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
369DEFINE_DECODER_ARM(MCR, ILL, info->operandFormat = ARM_OPERAND_NONE;)
370DEFINE_DECODER_ARM(MRC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
371
372// Begin miscellaneous definitions
373
374DEFINE_DECODER_ARM(BKPT, BKPT, info->operandFormat = ARM_OPERAND_NONE;) // Not strictly in ARMv4T, but here for convenience
375DEFINE_DECODER_ARM(ILL, ILL, info->operandFormat = ARM_OPERAND_NONE;) // Illegal opcode
376
377DEFINE_DECODER_ARM(MSR, MSR,
378 info->affectsCPSR = 1;
379 info->op1.reg = ARM_CPSR;
380 info->op2.reg = opcode & 0x0000000F;
381 info->operandFormat = ARM_OPERAND_REGISTER_1 |
382 ARM_OPERAND_AFFECTED_1 |
383 ARM_OPERAND_REGISTER_2;)
384
385DEFINE_DECODER_ARM(MSRR, MSR,
386 info->op1.reg = ARM_SPSR;
387 info->op2.reg = opcode & 0x0000000F;
388 info->operandFormat = ARM_OPERAND_REGISTER_1 |
389 ARM_OPERAND_AFFECTED_1 |
390 ARM_OPERAND_REGISTER_2;)
391
392DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
393 info->affectsCPSR = 1;
394 info->op1.reg = (opcode >> 12) & 0xF;
395 info->op2.reg = ARM_CPSR;
396 info->operandFormat = ARM_OPERAND_REGISTER_1 |
397 ARM_OPERAND_AFFECTED_1 |
398 ARM_OPERAND_REGISTER_2;)
399
400DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
401 info->affectsCPSR = 1;
402 info->op1.reg = (opcode >> 12) & 0xF;
403 info->op2.reg = ARM_SPSR;
404 info->operandFormat = ARM_OPERAND_REGISTER_1 |
405 ARM_OPERAND_AFFECTED_1 |
406 ARM_OPERAND_REGISTER_2;)
407
408DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;
409 int rotate = (opcode & 0x00000F00) >> 7;
410 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
411 info->affectsCPSR = 1;
412 info->op1.reg = ARM_CPSR;
413 info->op2.immediate = operand;
414 info->operandFormat = ARM_OPERAND_REGISTER_1 |
415 ARM_OPERAND_AFFECTED_1 |
416 ARM_OPERAND_IMMEDIATE_2;)
417
418DEFINE_DECODER_ARM(MSRRI, MSR, info->affectsCPSR = 1;
419 int rotate = (opcode & 0x00000F00) >> 7;
420 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
421 info->affectsCPSR = 1;
422 info->op1.reg = ARM_SPSR;
423 info->op2.immediate = operand;
424 info->operandFormat = ARM_OPERAND_REGISTER_1 |
425 ARM_OPERAND_AFFECTED_1 |
426 ARM_OPERAND_IMMEDIATE_2;)
427
428DEFINE_DECODER_ARM(SWI, SWI,
429 info->op1.immediate = opcode & 0xFFFFFF;
430 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
431 info->traps = 1;)
432
433typedef void (*ARMDecoder)(uint32_t opcode, struct ARMInstructionInfo* info);
434
435static const ARMDecoder _armDecoderTable[0x1000] = {
436 DECLARE_ARM_EMITTER_BLOCK(_ARMDecode)
437};
438
439void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
440 info->execMode = MODE_ARM;
441 info->opcode = opcode;
442 info->branches = 0;
443 info->traps = 0;
444 info->affectsCPSR = 0;
445 info->condition = opcode >> 28;
446 info->sDataCycles = 0;
447 info->nDataCycles = 0;
448 info->sInstructionCycles = 1;
449 info->nInstructionCycles = 0;
450 info->iCycles = 0;
451 info->cCycles = 0;
452 ARMDecoder decoder = _armDecoderTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
453 decoder(opcode, info);
454}