src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "util/memory.h"
8
9static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
10static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count);
11static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
12
13static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
14static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
17static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
18static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
19static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
20
21void GBAMemoryInit(struct GBA* gba) {
22 struct ARMCore* cpu = gba->cpu;
23 cpu->memory.load32 = GBALoad32;
24 cpu->memory.load16 = GBALoad16;
25 cpu->memory.loadU16 = GBALoadU16;
26 cpu->memory.load8 = GBALoad8;
27 cpu->memory.loadU8 = GBALoadU8;
28 cpu->memory.store32 = GBAStore32;
29 cpu->memory.store16 = GBAStore16;
30 cpu->memory.store8 = GBAStore8;
31
32 gba->memory.bios = (uint32_t*) hleBios;
33 gba->memory.fullBios = 0;
34 gba->memory.wram = 0;
35 gba->memory.iwram = 0;
36 gba->memory.rom = 0;
37 gba->memory.gpio.p = gba;
38
39 int i;
40 for (i = 0; i < 16; ++i) {
41 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
42 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
43 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
44 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
45 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
46 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
47 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
48 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
49 }
50 for (; i < 256; ++i) {
51 gba->memory.waitstatesNonseq16[i] = 0;
52 gba->memory.waitstatesSeq16[i] = 0;
53 gba->memory.waitstatesNonseq32[i] = 0;
54 gba->memory.waitstatesSeq32[i] = 0;
55 }
56
57 gba->memory.activeRegion = -1;
58 cpu->memory.activeRegion = 0;
59 cpu->memory.activeMask = 0;
60 cpu->memory.setActiveRegion = GBASetActiveRegion;
61 cpu->memory.activeSeqCycles32 = 0;
62 cpu->memory.activeSeqCycles16 = 0;
63 cpu->memory.activeNonseqCycles32 = 0;
64 cpu->memory.activeNonseqCycles16 = 0;
65 cpu->memory.activeUncachedCycles32 = 0;
66 cpu->memory.activeUncachedCycles16 = 0;
67 gba->memory.biosPrefetch = 0;
68 cpu->memory.waitMultiple = GBAWaitMultiple;
69}
70
71void GBAMemoryDeinit(struct GBA* gba) {
72 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
73 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
74 if (gba->memory.rom) {
75 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
76 }
77 GBASavedataDeinit(&gba->memory.savedata);
78}
79
80void GBAMemoryReset(struct GBA* gba) {
81 if (gba->memory.wram) {
82 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
83 }
84 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
85
86 if (gba->memory.iwram) {
87 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
88 }
89 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
90
91 memset(gba->memory.io, 0, sizeof(gba->memory.io));
92 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
93 int i;
94 for (i = 0; i < 4; ++i) {
95 gba->memory.dma[i].count = 0x10000;
96 gba->memory.dma[i].nextEvent = INT_MAX;
97 }
98 gba->memory.activeDMA = -1;
99 gba->memory.nextDMA = INT_MAX;
100 gba->memory.eventDiff = 0;
101
102 if (!gba->memory.wram || !gba->memory.iwram) {
103 GBAMemoryDeinit(gba);
104 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
105 }
106}
107
108static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
109 struct GBA* gba = (struct GBA*) cpu->master;
110 struct GBAMemory* memory = &gba->memory;
111
112 int newRegion = address >> BASE_OFFSET;
113 if (newRegion == memory->activeRegion) {
114 return;
115 }
116 if (memory->activeRegion == REGION_BIOS) {
117 memory->biosPrefetch = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
118 }
119 memory->activeRegion = newRegion;
120 switch (address & ~OFFSET_MASK) {
121 case BASE_BIOS:
122 cpu->memory.activeRegion = memory->bios;
123 cpu->memory.activeMask = SIZE_BIOS - 1;
124 break;
125 case BASE_WORKING_RAM:
126 cpu->memory.activeRegion = memory->wram;
127 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
128 break;
129 case BASE_WORKING_IRAM:
130 cpu->memory.activeRegion = memory->iwram;
131 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
132 break;
133 case BASE_CART0:
134 case BASE_CART0_EX:
135 case BASE_CART1:
136 case BASE_CART1_EX:
137 case BASE_CART2:
138 case BASE_CART2_EX:
139 cpu->memory.activeRegion = memory->rom;
140 cpu->memory.activeMask = SIZE_CART0 - 1;
141 break;
142 default:
143 cpu->memory.activeRegion = 0;
144 cpu->memory.activeMask = 0;
145 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
146 break;
147 }
148 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
149 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
150 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
151 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
152 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
153 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
154}
155
156int32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
157 struct GBA* gba = (struct GBA*) cpu->master;
158 struct GBAMemory* memory = &gba->memory;
159 uint32_t value = 0;
160 int wait = 0;
161
162 switch (address & ~OFFSET_MASK) {
163 case BASE_BIOS:
164 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
165 if (address < SIZE_BIOS) {
166 LOAD_32(value, address, memory->bios);
167 } else {
168 value = 0;
169 }
170 } else {
171 value = memory->biosPrefetch;
172 }
173 break;
174 case BASE_WORKING_RAM:
175 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
176 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
177 break;
178 case BASE_WORKING_IRAM:
179 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
180 break;
181 case BASE_IO:
182 value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
183 break;
184 case BASE_PALETTE_RAM:
185 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
186 break;
187 case BASE_VRAM:
188 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
189 break;
190 case BASE_OAM:
191 LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
192 break;
193 case BASE_CART0:
194 case BASE_CART0_EX:
195 case BASE_CART1:
196 case BASE_CART1_EX:
197 case BASE_CART2:
198 case BASE_CART2_EX:
199 wait = memory->waitstatesNonseq32[address >> BASE_OFFSET];
200 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
201 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom);
202 }
203 break;
204 case BASE_CART_SRAM:
205 case BASE_CART_SRAM_MIRROR:
206 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
207 break;
208 default:
209 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
210 if (cpu->executionMode == MODE_ARM) {
211 value = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
212 } else {
213 value = cpu->memory.load16(cpu, cpu->currentPC + WORD_SIZE_THUMB * 2, 0);
214 value |= value << 16;
215 }
216 break;
217 }
218
219
220 if (cycleCounter) {
221 *cycleCounter += 2 + wait;
222 }
223 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
224 int rotate = (address & 3) << 3;
225 return (value >> rotate) | (value << (32 - rotate));
226}
227
228uint16_t GBALoadU16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
229 return GBALoad16(cpu, address, cycleCounter);
230}
231
232int16_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
233 struct GBA* gba = (struct GBA*) cpu->master;
234 struct GBAMemory* memory = &gba->memory;
235 uint16_t value = 0;
236 int wait = 0;
237
238 switch (address & ~OFFSET_MASK) {
239 case BASE_BIOS:
240 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
241 if (address < SIZE_BIOS) {
242 LOAD_16(value, address, memory->bios);
243 } else {
244 value = 0;
245 }
246 } else {
247 value = memory->biosPrefetch;
248 }
249 break;
250 case BASE_WORKING_RAM:
251 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
252 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
253 break;
254 case BASE_WORKING_IRAM:
255 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
256 break;
257 case BASE_IO:
258 value = GBAIORead(gba, address & (SIZE_IO - 1));
259 break;
260 case BASE_PALETTE_RAM:
261 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
262 break;
263 case BASE_VRAM:
264 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
265 break;
266 case BASE_OAM:
267 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
268 break;
269 case BASE_CART0:
270 case BASE_CART0_EX:
271 case BASE_CART1:
272 case BASE_CART1_EX:
273 case BASE_CART2:
274 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
275 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
276 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
277 }
278 break;
279 case BASE_CART2_EX:
280 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
281 if (memory->savedata.type == SAVEDATA_EEPROM) {
282 value = GBASavedataReadEEPROM(&memory->savedata);
283 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
284 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
285 }
286 break;
287 case BASE_CART_SRAM:
288 case BASE_CART_SRAM_MIRROR:
289 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
290 break;
291 default:
292 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
293 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
294 break;
295 }
296
297 if (cycleCounter) {
298 *cycleCounter += 2 + wait;
299 }
300 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
301 int rotate = (address & 1) << 3;
302 return (value >> rotate) | (value << (16 - rotate));
303}
304
305uint8_t GBALoadU8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
306 return GBALoad8(cpu, address, cycleCounter);
307}
308
309int8_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
310 struct GBA* gba = (struct GBA*) cpu->master;
311 struct GBAMemory* memory = &gba->memory;
312 int8_t value = 0;
313 int wait = 0;
314
315 switch (address & ~OFFSET_MASK) {
316 case BASE_BIOS:
317 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
318 if (address < SIZE_BIOS) {
319 value = ((int8_t*) memory->bios)[address];
320 } else {
321 value = 0;
322 }
323 } else {
324 value = memory->biosPrefetch;
325 }
326 break;
327 case BASE_WORKING_RAM:
328 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
329 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
330 break;
331 case BASE_WORKING_IRAM:
332 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
333 break;
334 case BASE_IO:
335 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
336 break;
337 case BASE_PALETTE_RAM:
338 value = ((int8_t*) gba->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
339 break;
340 case BASE_VRAM:
341 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
342 break;
343 case BASE_OAM:
344 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
345 break;
346 case BASE_CART0:
347 case BASE_CART0_EX:
348 case BASE_CART1:
349 case BASE_CART1_EX:
350 case BASE_CART2:
351 case BASE_CART2_EX:
352 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
353 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
354 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
355 }
356 break;
357 case BASE_CART_SRAM:
358 case BASE_CART_SRAM_MIRROR:
359 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
360 if (memory->savedata.type == SAVEDATA_NONE) {
361 GBASavedataInitSRAM(&memory->savedata);
362 }
363 if (memory->savedata.type == SAVEDATA_SRAM) {
364 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
365 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
366 value = GBASavedataReadFlash(&memory->savedata, address);
367 }
368 break;
369 default:
370 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
371 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
372 break;
373 }
374
375 if (cycleCounter) {
376 *cycleCounter += 2 + wait;
377 }
378 return value;
379}
380
381void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
382 struct GBA* gba = (struct GBA*) cpu->master;
383 struct GBAMemory* memory = &gba->memory;
384 int wait = 0;
385
386 switch (address & ~OFFSET_MASK) {
387 case BASE_WORKING_RAM:
388 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
389 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
390 break;
391 case BASE_WORKING_IRAM:
392 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
393 break;
394 case BASE_IO:
395 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
396 break;
397 case BASE_PALETTE_RAM:
398 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
399 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
400 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
401 break;
402 case BASE_VRAM:
403 if ((address & OFFSET_MASK) < SIZE_VRAM) {
404 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
405 } else if ((address & OFFSET_MASK) < 0x00020000) {
406 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
407 }
408 break;
409 case BASE_OAM:
410 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
411 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
412 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
413 break;
414 case BASE_CART0:
415 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
416 break;
417 case BASE_CART_SRAM:
418 case BASE_CART_SRAM_MIRROR:
419 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
420 break;
421 default:
422 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
423 break;
424 }
425
426 if (cycleCounter) {
427 *cycleCounter += 1 + wait;
428 }
429}
430
431void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
432 struct GBA* gba = (struct GBA*) cpu->master;
433 struct GBAMemory* memory = &gba->memory;
434 int wait = 0;
435
436 switch (address & ~OFFSET_MASK) {
437 case BASE_WORKING_RAM:
438 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
439 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
440 break;
441 case BASE_WORKING_IRAM:
442 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
443 break;
444 case BASE_IO:
445 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
446 break;
447 case BASE_PALETTE_RAM:
448 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
449 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
450 break;
451 case BASE_VRAM:
452 if ((address & OFFSET_MASK) < SIZE_VRAM) {
453 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
454 } else if ((address & OFFSET_MASK) < 0x00020000) {
455 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
456 }
457 break;
458 case BASE_OAM:
459 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
460 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
461 break;
462 case BASE_CART0:
463 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
464 uint32_t reg = address & 0xFFFFFF;
465 GBAGPIOWrite(&memory->gpio, reg, value);
466 } else {
467 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
468 }
469 break;
470 case BASE_CART2_EX:
471 if (memory->savedata.type == SAVEDATA_NONE) {
472 GBASavedataInitEEPROM(&memory->savedata);
473 }
474 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
475 break;
476 case BASE_CART_SRAM:
477 case BASE_CART_SRAM_MIRROR:
478 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
479 break;
480 default:
481 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
482 break;
483 }
484
485 if (cycleCounter) {
486 *cycleCounter += 1 + wait;
487 }
488}
489
490void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
491 struct GBA* gba = (struct GBA*) cpu->master;
492 struct GBAMemory* memory = &gba->memory;
493 int wait = 0;
494
495 switch (address & ~OFFSET_MASK) {
496 case BASE_WORKING_RAM:
497 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
498 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
499 break;
500 case BASE_WORKING_IRAM:
501 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
502 break;
503 case BASE_IO:
504 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
505 break;
506 case BASE_PALETTE_RAM:
507 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
508 break;
509 case BASE_VRAM:
510 if (address >= 0x06018000) {
511 // TODO: check BG mode
512 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
513 break;
514 }
515 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
516 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
517 break;
518 case BASE_OAM:
519 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
520 break;
521 case BASE_CART0:
522 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
523 break;
524 case BASE_CART_SRAM:
525 case BASE_CART_SRAM_MIRROR:
526 if (memory->savedata.type == SAVEDATA_NONE) {
527 if (address == SAVEDATA_FLASH_BASE) {
528 GBASavedataInitFlash(&memory->savedata);
529 } else {
530 GBASavedataInitSRAM(&memory->savedata);
531 }
532 }
533 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
534 GBASavedataWriteFlash(&memory->savedata, address, value);
535 } else if (memory->savedata.type == SAVEDATA_SRAM) {
536 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
537 }
538 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
539 break;
540 default:
541 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
542 break;
543 }
544
545 if (cycleCounter) {
546 *cycleCounter += 1 + wait;
547 }
548}
549
550static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count) {
551 struct GBA* gba = (struct GBA*) cpu->master;
552 struct GBAMemory* memory = &gba->memory;
553 int wait = 1 + memory->waitstatesNonseq32[startAddress >> BASE_OFFSET];
554 wait += (1 + memory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
555 return wait;
556}
557
558void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
559 struct GBAMemory* memory = &gba->memory;
560 struct ARMCore* cpu = gba->cpu;
561 int sram = parameters & 0x0003;
562 int ws0 = (parameters & 0x000C) >> 2;
563 int ws0seq = (parameters & 0x0010) >> 4;
564 int ws1 = (parameters & 0x0060) >> 5;
565 int ws1seq = (parameters & 0x0080) >> 7;
566 int ws2 = (parameters & 0x0300) >> 8;
567 int ws2seq = (parameters & 0x0400) >> 10;
568 int prefetch = parameters & 0x4000;
569
570 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
571 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
572 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
573 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
574
575 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
576 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
577 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
578
579 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
580 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
581 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
582
583 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
584 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
585 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
586
587 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
588 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
589 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
590
591 if (!prefetch) {
592 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
593 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
594 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
595
596 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
597 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
598 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
599
600 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
601 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
602 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
603
604 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
605 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
606 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
607 } else {
608 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
609 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
610 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
611
612 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
613 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
614 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
615
616 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
617 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
618 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
619
620 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
621 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
622 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
623 }
624
625 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
626 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
627
628 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
629 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
630
631 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
632 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
633}
634
635void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
636 struct GBAMemory* memory = &gba->memory;
637 memory->dma[dma].source = address & 0xFFFFFFFE;
638}
639
640void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
641 struct GBAMemory* memory = &gba->memory;
642 memory->dma[dma].dest = address & 0xFFFFFFFE;
643}
644
645void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
646 struct GBAMemory* memory = &gba->memory;
647 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
648}
649
650uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
651 struct GBAMemory* memory = &gba->memory;
652 struct GBADMA* currentDma = &memory->dma[dma];
653 int wasEnabled = currentDma->enable;
654 currentDma->packed = control;
655
656 if (currentDma->drq) {
657 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
658 }
659
660 if (!wasEnabled && currentDma->enable) {
661 currentDma->nextSource = currentDma->source;
662 currentDma->nextDest = currentDma->dest;
663 currentDma->nextCount = currentDma->count;
664 GBAMemoryScheduleDMA(gba, dma, currentDma);
665 }
666 // If the DMA has already occurred, this value might have changed since the function started
667 return currentDma->packed;
668};
669
670void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
671 struct ARMCore* cpu = gba->cpu;
672 switch (info->timing) {
673 case DMA_TIMING_NOW:
674 info->nextEvent = cpu->cycles;
675 GBAMemoryUpdateDMAs(gba, 0);
676 break;
677 case DMA_TIMING_HBLANK:
678 // Handled implicitly
679 info->nextEvent = INT_MAX;
680 break;
681 case DMA_TIMING_VBLANK:
682 // Handled implicitly
683 info->nextEvent = INT_MAX;
684 break;
685 case DMA_TIMING_CUSTOM:
686 info->nextEvent = INT_MAX;
687 switch (number) {
688 case 0:
689 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
690 break;
691 case 1:
692 case 2:
693 GBAAudioScheduleFifoDma(&gba->audio, number, info);
694 break;
695 case 3:
696 // GBAVideoScheduleVCaptureDma(dma, info);
697 break;
698 }
699 }
700}
701
702void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
703 struct GBAMemory* memory = &gba->memory;
704 struct GBADMA* dma;
705 int i;
706 for (i = 0; i < 4; ++i) {
707 dma = &memory->dma[i];
708 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
709 dma->nextEvent = cycles;
710 }
711 }
712 GBAMemoryUpdateDMAs(gba, 0);
713}
714
715void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
716 struct GBAMemory* memory = &gba->memory;
717 struct GBADMA* dma;
718 int i;
719 for (i = 0; i < 4; ++i) {
720 dma = &memory->dma[i];
721 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
722 dma->nextEvent = cycles;
723 }
724 }
725 GBAMemoryUpdateDMAs(gba, 0);
726}
727
728int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
729 struct GBAMemory* memory = &gba->memory;
730 if (memory->nextDMA == INT_MAX) {
731 return INT_MAX;
732 }
733 memory->nextDMA -= cycles;
734 memory->eventDiff += cycles;
735 if (memory->nextDMA <= 0) {
736 struct GBADMA* dma = &memory->dma[memory->activeDMA];
737 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
738 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
739 memory->eventDiff = 0;
740 }
741 return memory->nextDMA;
742}
743
744void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
745 int i;
746 struct GBAMemory* memory = &gba->memory;
747 struct ARMCore* cpu = gba->cpu;
748 memory->activeDMA = -1;
749 memory->nextDMA = INT_MAX;
750 for (i = 3; i >= 0; --i) {
751 struct GBADMA* dma = &memory->dma[i];
752 if (dma->nextEvent != INT_MAX) {
753 dma->nextEvent -= cycles;
754 if (dma->enable) {
755 memory->activeDMA = i;
756 memory->nextDMA = dma->nextEvent;
757 }
758 }
759 }
760 if (memory->nextDMA < cpu->nextEvent) {
761 cpu->nextEvent = memory->nextDMA;
762 }
763}
764
765void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
766 struct GBAMemory* memory = &gba->memory;
767 struct ARMCore* cpu = gba->cpu;
768 uint32_t width = info->width ? 4 : 2;
769 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
770 int destOffset = DMA_OFFSET[info->dstControl] * width;
771 int32_t wordsRemaining = info->nextCount;
772 uint32_t source = info->nextSource;
773 uint32_t dest = info->nextDest;
774 uint32_t sourceRegion = source >> BASE_OFFSET;
775 uint32_t destRegion = dest >> BASE_OFFSET;
776 int32_t cycles = 0;
777
778 if (source == info->source) {
779 // TODO: support 4 cycles for ROM access
780 cycles += 2;
781 if (width == 4) {
782 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
783 source &= 0xFFFFFFFC;
784 dest &= 0xFFFFFFFC;
785 } else {
786 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
787 }
788 } else {
789 if (width == 4) {
790 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
791 } else {
792 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
793 }
794 }
795
796 if (width == 4) {
797 int32_t word;
798 word = cpu->memory.load32(cpu, source, 0);
799 cpu->memory.store32(cpu, dest, word, 0);
800 source += sourceOffset;
801 dest += destOffset;
802 --wordsRemaining;
803 } else {
804 uint16_t word;
805 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
806 word = GBASavedataReadEEPROM(&memory->savedata);
807 cpu->memory.store16(cpu, dest, word, 0);
808 source += sourceOffset;
809 dest += destOffset;
810 --wordsRemaining;
811 } else if (destRegion == REGION_CART2_EX) {
812 if (memory->savedata.type == SAVEDATA_NONE) {
813 GBASavedataInitEEPROM(&memory->savedata);
814 }
815 word = cpu->memory.load16(cpu, source, 0);
816 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
817 source += sourceOffset;
818 dest += destOffset;
819 --wordsRemaining;
820 } else {
821 word = cpu->memory.load16(cpu, source, 0);
822 cpu->memory.store16(cpu, dest, word, 0);
823 source += sourceOffset;
824 dest += destOffset;
825 --wordsRemaining;
826 }
827 }
828
829 if (!wordsRemaining) {
830 if (!info->repeat) {
831 info->enable = 0;
832 info->nextEvent = INT_MAX;
833
834 // Clear the enable bit in memory
835 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
836 } else {
837 info->nextCount = info->count;
838 if (info->dstControl == DMA_INCREMENT_RELOAD) {
839 info->nextDest = info->dest;
840 }
841 GBAMemoryScheduleDMA(gba, number, info);
842 }
843 if (info->doIrq) {
844 GBARaiseIRQ(gba, IRQ_DMA0 + number);
845 }
846 } else {
847 info->nextDest = dest;
848 info->nextCount = wordsRemaining;
849 }
850 info->nextSource = source;
851
852 int i;
853 for (i = 0; i < 4; ++i) {
854 if (memory->dma[i].nextEvent != INT_MAX) {
855 memory->dma[i].nextEvent += cycles;
856 }
857 }
858 cpu->cycles += cycles;
859}
860
861void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
862 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
863 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
864}
865
866void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
867 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
868 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
869}