1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/emulator-only/mbc1_rom_4banks.gb".
  3
  4[labels]
  50001:4bf3 print_load_font
  60001:4c00 print_string
  70001:4c0a print_a
  80001:4c14 print_newline
  90001:4c1f print_digit
 100001:4c2c print_regs
 110001:4c35 _print_sl_data0
 120001:4c3b _print_sl_out0
 130001:4c48 _print_sl_data1
 140001:4c4e _print_sl_out1
 150001:4c60 _print_sl_data2
 160001:4c66 _print_sl_out2
 170001:4c73 _print_sl_data3
 180001:4c79 _print_sl_out3
 190001:4c8b _print_sl_data4
 200001:4c91 _print_sl_out4
 210001:4c9e _print_sl_data5
 220001:4ca4 _print_sl_out5
 230001:4cb6 _print_sl_data6
 240001:4cbc _print_sl_out6
 250001:4cc9 _print_sl_data7
 260001:4ccf _print_sl_out7
 270001:4001 font
 280000:c000 regs_save
 290000:c000 regs_save.f
 300000:c001 regs_save.a
 310000:c002 regs_save.c
 320000:c003 regs_save.b
 330000:c004 regs_save.e
 340000:c005 regs_save.d
 350000:c006 regs_save.l
 360000:c007 regs_save.h
 370000:c008 regs_flags
 380000:c009 regs_assert
 390000:c009 regs_assert.f
 400000:c00a regs_assert.a
 410000:c00b regs_assert.c
 420000:c00c regs_assert.b
 430000:c00d regs_assert.e
 440000:c00e regs_assert.d
 450000:c00f regs_assert.l
 460000:c010 regs_assert.h
 470000:c011 memdump_len
 480000:c012 memdump_addr
 490001:47f1 memcpy
 500001:47fa memset
 510001:4803 clear_vram
 520001:480e reset_screen
 530001:481b process_results
 540001:4820 _wait_ly_0
 550001:4826 _wait_ly_1
 560001:4842 _wait_ly_2
 570001:4848 _wait_ly_3
 580001:4861 _process_results_cb
 590001:486c _print_sl_data8
 600001:4876 _print_sl_out8
 610001:4890 _print_sl_data9
 620001:489b _print_sl_out9
 630001:48b3 _print_sl_data10
 640001:48bf _print_sl_out10
 650001:48c0 dump_mem
 660001:48d0 _wait_ly_4
 670001:48d6 _wait_ly_5
 680001:48f2 _dump_mem_line
 690001:491c _check_asserts
 700001:492a _print_sl_data11
 710001:492d _print_sl_out11
 720001:4939 _print_sl_data12
 730001:493b _print_sl_out12
 740001:4943 _print_sl_data13
 750001:4946 _print_sl_out13
 760001:4950 __check_assert_fail0
 770001:495b _print_sl_data14
 780001:495e _print_sl_out14
 790001:4961 __check_assert_ok0
 800001:4969 _print_sl_data15
 810001:496e _print_sl_out15
 820001:4970 __check_assert_skip0
 830001:4978 _print_sl_data16
 840001:4980 _print_sl_out16
 850001:4980 __check_assert_out0
 860001:498c _print_sl_data17
 870001:498e _print_sl_out17
 880001:4996 _print_sl_data18
 890001:4999 _print_sl_out18
 900001:49a3 __check_assert_fail1
 910001:49ae _print_sl_data19
 920001:49b1 _print_sl_out19
 930001:49b4 __check_assert_ok1
 940001:49bc _print_sl_data20
 950001:49c1 _print_sl_out20
 960001:49c3 __check_assert_skip1
 970001:49cb _print_sl_data21
 980001:49d3 _print_sl_out21
 990001:49d3 __check_assert_out1
1000001:49de _print_sl_data22
1010001:49e1 _print_sl_out22
1020001:49ed _print_sl_data23
1030001:49ef _print_sl_out23
1040001:49f7 _print_sl_data24
1050001:49fa _print_sl_out24
1060001:4a04 __check_assert_fail2
1070001:4a0f _print_sl_data25
1080001:4a12 _print_sl_out25
1090001:4a15 __check_assert_ok2
1100001:4a1d _print_sl_data26
1110001:4a22 _print_sl_out26
1120001:4a24 __check_assert_skip2
1130001:4a2c _print_sl_data27
1140001:4a34 _print_sl_out27
1150001:4a34 __check_assert_out2
1160001:4a40 _print_sl_data28
1170001:4a42 _print_sl_out28
1180001:4a4a _print_sl_data29
1190001:4a4d _print_sl_out29
1200001:4a57 __check_assert_fail3
1210001:4a62 _print_sl_data30
1220001:4a65 _print_sl_out30
1230001:4a68 __check_assert_ok3
1240001:4a70 _print_sl_data31
1250001:4a75 _print_sl_out31
1260001:4a77 __check_assert_skip3
1270001:4a7f _print_sl_data32
1280001:4a87 _print_sl_out32
1290001:4a87 __check_assert_out3
1300001:4a92 _print_sl_data33
1310001:4a95 _print_sl_out33
1320001:4aa1 _print_sl_data34
1330001:4aa3 _print_sl_out34
1340001:4aab _print_sl_data35
1350001:4aae _print_sl_out35
1360001:4ab8 __check_assert_fail4
1370001:4ac3 _print_sl_data36
1380001:4ac6 _print_sl_out36
1390001:4ac9 __check_assert_ok4
1400001:4ad1 _print_sl_data37
1410001:4ad6 _print_sl_out37
1420001:4ad8 __check_assert_skip4
1430001:4ae0 _print_sl_data38
1440001:4ae8 _print_sl_out38
1450001:4ae8 __check_assert_out4
1460001:4af4 _print_sl_data39
1470001:4af6 _print_sl_out39
1480001:4afe _print_sl_data40
1490001:4b01 _print_sl_out40
1500001:4b0b __check_assert_fail5
1510001:4b16 _print_sl_data41
1520001:4b19 _print_sl_out41
1530001:4b1c __check_assert_ok5
1540001:4b24 _print_sl_data42
1550001:4b29 _print_sl_out42
1560001:4b2b __check_assert_skip5
1570001:4b33 _print_sl_data43
1580001:4b3b _print_sl_out43
1590001:4b3b __check_assert_out5
1600001:4b46 _print_sl_data44
1610001:4b49 _print_sl_out44
1620001:4b55 _print_sl_data45
1630001:4b57 _print_sl_out45
1640001:4b5f _print_sl_data46
1650001:4b62 _print_sl_out46
1660001:4b6c __check_assert_fail6
1670001:4b77 _print_sl_data47
1680001:4b7a _print_sl_out47
1690001:4b7d __check_assert_ok6
1700001:4b85 _print_sl_data48
1710001:4b8a _print_sl_out48
1720001:4b8c __check_assert_skip6
1730001:4b94 _print_sl_data49
1740001:4b9c _print_sl_out49
1750001:4b9c __check_assert_out6
1760001:4ba8 _print_sl_data50
1770001:4baa _print_sl_out50
1780001:4bb2 _print_sl_data51
1790001:4bb5 _print_sl_out51
1800001:4bbf __check_assert_fail7
1810001:4bca _print_sl_data52
1820001:4bcd _print_sl_out52
1830001:4bd0 __check_assert_ok7
1840001:4bd8 _print_sl_data53
1850001:4bdd _print_sl_out53
1860001:4bdf __check_assert_skip7
1870001:4be7 _print_sl_data54
1880001:4bef _print_sl_out54
1890001:4bef __check_assert_out7
1900000:01c8 _wait_ly_6
1910000:01ce _wait_ly_7
1920000:01ea _wait_ly_8
1930000:01f0 _wait_ly_9
1940000:0209 _test_ok_cb_0
1950000:0211 _print_sl_data55
1960000:0219 _print_sl_out55
1970000:021c switch_bank
1980000:0225 test_mbc
1990000:0236 _wait_ly_10
2000000:023c _wait_ly_11
2010000:0258 _wait_ly_12
2020000:025e _wait_ly_13
2030000:0277 _test_failure_cb_0
2040000:027f _print_sl_data56
2050000:028b _print_sl_out56