1#ifndef ARM_H
  2#define ARM_H
  3
  4#include <stdint.h>
  5
  6enum {
  7	ARM_SP = 13,
  8	ARM_LR = 14,
  9	ARM_PC = 15
 10};
 11
 12enum ExecutionMode {
 13	MODE_ARM = 0,
 14	MODE_THUMB = 1
 15};
 16
 17enum PrivilegeMode {
 18	MODE_USER = 0x10,
 19	MODE_FIQ = 0x11,
 20	MODE_IRQ = 0x12,
 21	MODE_SUPERVISOR = 0x13,
 22	MODE_ABORT = 0x17,
 23	MODE_UNDEFINED = 0x1B,
 24	MODE_SYSTEM = 0x1F
 25};
 26
 27enum WordSize {
 28	WORD_SIZE_ARM = 4,
 29	WORD_SIZE_THUMB = 2
 30};
 31
 32enum ExecutionVector {
 33	BASE_RESET = 0x00000000,
 34	BASE_UNDEF = 0x00000004,
 35	BASE_SWI = 0x00000008,
 36	BASE_PABT = 0x0000000C,
 37	BASE_DABT = 0x00000010,
 38	BASE_IRQ = 0x00000018,
 39	BASE_FIQ = 0x0000001C
 40};
 41
 42enum RegisterBank {
 43	BANK_NONE = 0,
 44	BANK_FIQ = 1,
 45	BANK_IRQ = 2,
 46	BANK_SUPERVISOR = 3,
 47	BANK_ABORT = 4,
 48	BANK_UNDEFINED = 5
 49};
 50
 51struct ARMCore;
 52
 53union PSR {
 54	struct {
 55		enum PrivilegeMode priv : 5;
 56		enum ExecutionMode t : 1;
 57		unsigned f : 1;
 58		unsigned i : 1;
 59		unsigned : 20;
 60		unsigned v : 1;
 61		unsigned c : 1;
 62		unsigned z : 1;
 63		unsigned n : 1;
 64	};
 65
 66	int32_t packed;
 67};
 68
 69struct ARMMemory {
 70	int32_t (*load32)(struct ARMMemory*, uint32_t address, int* cycleCounter);
 71	int16_t (*load16)(struct ARMMemory*, uint32_t address, int* cycleCounter);
 72	uint16_t (*loadU16)(struct ARMMemory*, uint32_t address, int* cycleCounter);
 73	int8_t (*load8)(struct ARMMemory*, uint32_t address, int* cycleCounter);
 74	uint8_t (*loadU8)(struct ARMMemory*, uint32_t address, int* cycleCounter);
 75
 76	void (*store32)(struct ARMMemory*, uint32_t address, int32_t value, int* cycleCounter);
 77	void (*store16)(struct ARMMemory*, uint32_t address, int16_t value, int* cycleCounter);
 78	void (*store8)(struct ARMMemory*, uint32_t address, int8_t value, int* cycleCounter);
 79
 80	uint32_t* activeRegion;
 81	uint32_t activeMask;
 82	uint32_t activePrefetchCycles32;
 83	uint32_t activePrefetchCycles16;
 84	uint32_t activeNonseqCycles32;
 85	uint32_t activeNonseqCycles16;
 86	void (*setActiveRegion)(struct ARMMemory*, uint32_t address);
 87	int (*waitMultiple)(struct ARMMemory*, uint32_t startAddress, int count);
 88};
 89
 90struct ARMBoard {
 91	struct ARMCore* cpu;
 92	void (*reset)(struct ARMBoard* board);
 93	void (*processEvents)(struct ARMBoard* board);
 94	void (*swi16)(struct ARMBoard* board, int immediate);
 95	void (*swi32)(struct ARMBoard* board, int immediate);
 96	void (*readCPSR)(struct ARMBoard* board);
 97
 98	void (*hitStub)(struct ARMBoard* board, uint32_t opcode);
 99};
100
101struct ARMCore {
102	int32_t gprs[16];
103	union PSR cpsr;
104	union PSR spsr;
105
106	int32_t cycles;
107	int32_t nextEvent;
108
109	int32_t bankedRegisters[6][7];
110	int32_t bankedSPSRs[6];
111
112	int32_t shifterOperand;
113	int32_t shifterCarryOut;
114
115	uint32_t currentPC;
116	enum ExecutionMode executionMode;
117	enum PrivilegeMode privilegeMode;
118
119	struct ARMMemory* memory;
120	struct ARMBoard* board;
121
122	int64_t absoluteCycles;
123	int32_t lastCycles;
124};
125
126void ARMInit(struct ARMCore* cpu);
127void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory);
128void ARMAssociateBoard(struct ARMCore* cpu, struct ARMBoard* board);
129
130void ARMReset(struct ARMCore* cpu);
131void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
132void ARMRaiseIRQ(struct ARMCore*);
133void ARMRaiseSWI(struct ARMCore*);
134
135void ARMRun(struct ARMCore* cpu);
136
137#endif