src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "core/interface.h"
9#include "gb/gb.h"
10#include "gb/io.h"
11
12#include "util/memory.h"
13
14#include <time.h>
15
16mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC");
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
18
19static void _GBMBCNone(struct GBMemory* memory, uint16_t address, uint8_t value) {
20 UNUSED(memory);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GBMemory*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GBMemory*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GBMemory*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GBMemory*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GBMemory*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static void _GBMBC7Write(struct GBMemory*, uint16_t address, uint8_t value);
35
36static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
37 if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
38 cpu->memory.setActiveRegion(cpu, address);
39 return cpu->memory.cpuLoad8(cpu, address);
40 }
41 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
42}
43
44static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
45 struct GB* gb = (struct GB*) cpu->master;
46 struct GBMemory* memory = &gb->memory;
47 switch (address >> 12) {
48 case GB_REGION_CART_BANK0:
49 case GB_REGION_CART_BANK0 + 1:
50 case GB_REGION_CART_BANK0 + 2:
51 case GB_REGION_CART_BANK0 + 3:
52 cpu->memory.cpuLoad8 = GBFastLoad8;
53 cpu->memory.activeRegion = memory->rom;
54 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
55 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
56 break;
57 case GB_REGION_CART_BANK1:
58 case GB_REGION_CART_BANK1 + 1:
59 case GB_REGION_CART_BANK1 + 2:
60 case GB_REGION_CART_BANK1 + 3:
61 cpu->memory.cpuLoad8 = GBFastLoad8;
62 cpu->memory.activeRegion = memory->romBank;
63 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
64 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
65 break;
66 default:
67 cpu->memory.cpuLoad8 = GBLoad8;
68 break;
69 }
70}
71
72static void _GBMemoryDMAService(struct GB* gb);
73static void _GBMemoryHDMAService(struct GB* gb);
74
75void GBMemoryInit(struct GB* gb) {
76 struct LR35902Core* cpu = gb->cpu;
77 cpu->memory.cpuLoad8 = GBLoad8;
78 cpu->memory.load8 = GBLoad8;
79 cpu->memory.store8 = GBStore8;
80 cpu->memory.setActiveRegion = GBSetActiveRegion;
81
82 gb->memory.wram = 0;
83 gb->memory.wramBank = 0;
84 gb->memory.rom = 0;
85 gb->memory.romBank = 0;
86 gb->memory.romSize = 0;
87 gb->memory.sram = 0;
88 gb->memory.mbcType = GB_MBC_NONE;
89 gb->memory.mbc = 0;
90
91 gb->memory.rtc = NULL;
92
93 GBIOInit(gb);
94}
95
96void GBMemoryDeinit(struct GB* gb) {
97 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
98 if (gb->memory.rom) {
99 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
100 }
101}
102
103void GBMemoryReset(struct GB* gb) {
104 if (gb->memory.wram) {
105 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
106 }
107 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
108 GBMemorySwitchWramBank(&gb->memory, 1);
109 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
110 gb->memory.currentBank = 1;
111 if (!gb->memory.sram) {
112 gb->memory.sram = anonymousMemoryMap(0x20000);
113 }
114 gb->memory.sramCurrentBank = 0;
115 gb->memory.sramBank = gb->memory.sram;
116
117 gb->memory.ime = false;
118 gb->memory.ie = 0;
119
120 gb->memory.dmaNext = INT_MAX;
121 gb->memory.dmaRemaining = 0;
122 gb->memory.dmaSource = 0;
123 gb->memory.dmaDest = 0;
124 gb->memory.hdmaNext = INT_MAX;
125 gb->memory.hdmaRemaining = 0;
126 gb->memory.hdmaSource = 0;
127 gb->memory.hdmaDest = 0;
128 gb->memory.isHdma = false;
129
130 gb->memory.sramAccess = false;
131 gb->memory.rtcAccess = false;
132 gb->memory.activeRtcReg = 0;
133 gb->memory.rtcLatched = 0;
134 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
135
136 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
137
138 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
139 switch (cart->type) {
140 case 0:
141 case 8:
142 case 9:
143 gb->memory.mbc = _GBMBCNone;
144 gb->memory.mbcType = GB_MBC_NONE;
145 break;
146 case 1:
147 case 2:
148 case 3:
149 gb->memory.mbc = _GBMBC1;
150 gb->memory.mbcType = GB_MBC1;
151 break;
152 case 5:
153 case 6:
154 gb->memory.mbc = _GBMBC2;
155 gb->memory.mbcType = GB_MBC2;
156 break;
157 case 0x0F:
158 case 0x10:
159 case 0x11:
160 case 0x12:
161 case 0x13:
162 gb->memory.mbc = _GBMBC3;
163 gb->memory.mbcType = GB_MBC3;
164 break;
165 default:
166 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
167 case 0x19:
168 case 0x1A:
169 case 0x1B:
170 gb->memory.mbc = _GBMBC5;
171 gb->memory.mbcType = GB_MBC5;
172 break;
173 case 0x1C:
174 case 0x1D:
175 case 0x1E:
176 gb->memory.mbc = _GBMBC5;
177 gb->memory.mbcType = GB_MBC5_RUMBLE;
178 break;
179 case 0x20:
180 gb->memory.mbc = _GBMBC6;
181 gb->memory.mbcType = GB_MBC6;
182 break;
183 case 0x22:
184 gb->memory.mbc = _GBMBC7;
185 gb->memory.mbcType = GB_MBC7;
186 memset(&gb->memory.mbcState.mbc7, 0, sizeof(gb->memory.mbcState.mbc7));
187 break;
188 }
189
190 if (!gb->memory.wram) {
191 GBMemoryDeinit(gb);
192 }
193}
194
195void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
196 bank &= 7;
197 if (!bank) {
198 bank = 1;
199 }
200 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
201 memory->wramCurrentBank = bank;
202}
203
204uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
205 struct GB* gb = (struct GB*) cpu->master;
206 struct GBMemory* memory = &gb->memory;
207 switch (address >> 12) {
208 case GB_REGION_CART_BANK0:
209 case GB_REGION_CART_BANK0 + 1:
210 case GB_REGION_CART_BANK0 + 2:
211 case GB_REGION_CART_BANK0 + 3:
212 return memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
213 case GB_REGION_CART_BANK1:
214 case GB_REGION_CART_BANK1 + 1:
215 case GB_REGION_CART_BANK1 + 2:
216 case GB_REGION_CART_BANK1 + 3:
217 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
218 case GB_REGION_VRAM:
219 case GB_REGION_VRAM + 1:
220 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
221 case GB_REGION_EXTERNAL_RAM:
222 case GB_REGION_EXTERNAL_RAM + 1:
223 if (memory->rtcAccess) {
224 return gb->memory.rtcRegs[memory->activeRtcReg];
225 } else if (memory->sramAccess) {
226 return gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
227 } else if (memory->mbcType == GB_MBC7) {
228 return _GBMBC7Read(memory, address);
229 }
230 return 0xFF;
231 case GB_REGION_WORKING_RAM_BANK0:
232 case GB_REGION_WORKING_RAM_BANK0 + 2:
233 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
234 case GB_REGION_WORKING_RAM_BANK1:
235 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
236 default:
237 if (address < GB_BASE_OAM) {
238 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
239 }
240 if (address < GB_BASE_UNUSABLE) {
241 if (gb->video.mode < 2) {
242 return gb->video.oam.raw[address & 0xFF];
243 }
244 return 0xFF;
245 }
246 if (address < GB_BASE_IO) {
247 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
248 return 0xFF;
249 }
250 if (address < GB_BASE_HRAM) {
251 return GBIORead(gb, address & (GB_SIZE_IO - 1));
252 }
253 if (address < GB_BASE_IE) {
254 return memory->hram[address & GB_SIZE_HRAM];
255 }
256 return GBIORead(gb, REG_IE);
257 }
258}
259
260void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
261 struct GB* gb = (struct GB*) cpu->master;
262 struct GBMemory* memory = &gb->memory;
263 switch (address >> 12) {
264 case GB_REGION_CART_BANK0:
265 case GB_REGION_CART_BANK0 + 1:
266 case GB_REGION_CART_BANK0 + 2:
267 case GB_REGION_CART_BANK0 + 3:
268 case GB_REGION_CART_BANK1:
269 case GB_REGION_CART_BANK1 + 1:
270 case GB_REGION_CART_BANK1 + 2:
271 case GB_REGION_CART_BANK1 + 3:
272 memory->mbc(memory, address, value);
273 cpu->memory.setActiveRegion(cpu, cpu->pc);
274 return;
275 case GB_REGION_VRAM:
276 case GB_REGION_VRAM + 1:
277 // TODO: Block access in wrong modes
278 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
279 return;
280 case GB_REGION_EXTERNAL_RAM:
281 case GB_REGION_EXTERNAL_RAM + 1:
282 if (memory->rtcAccess) {
283 gb->memory.rtcRegs[memory->activeRtcReg] = value;
284 } else if (memory->sramAccess) {
285 gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
286 } else if (gb->memory.mbcType == GB_MBC7) {
287 _GBMBC7Write(&gb->memory, address, value);
288 }
289 return;
290 case GB_REGION_WORKING_RAM_BANK0:
291 case GB_REGION_WORKING_RAM_BANK0 + 2:
292 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
293 return;
294 case GB_REGION_WORKING_RAM_BANK1:
295 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
296 return;
297 default:
298 if (address < GB_BASE_OAM) {
299 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
300 } else if (address < GB_BASE_UNUSABLE) {
301 if (gb->video.mode < 2) {
302 gb->video.oam.raw[address & 0xFF] = value;
303 }
304 } else if (address < GB_BASE_IO) {
305 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
306 } else if (address < GB_BASE_HRAM) {
307 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
308 } else if (address < GB_BASE_IE) {
309 memory->hram[address & GB_SIZE_HRAM] = value;
310 } else {
311 GBIOWrite(gb, REG_IE, value);
312 }
313 }
314}
315
316int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
317 int nextEvent = INT_MAX;
318 if (gb->memory.dmaRemaining) {
319 gb->memory.dmaNext -= cycles;
320 if (gb->memory.dmaNext <= 0) {
321 _GBMemoryDMAService(gb);
322 }
323 nextEvent = gb->memory.dmaNext;
324 }
325 if (gb->memory.hdmaRemaining) {
326 gb->memory.hdmaNext -= cycles;
327 if (gb->memory.hdmaNext <= 0) {
328 _GBMemoryHDMAService(gb);
329 }
330 if (gb->memory.hdmaNext < nextEvent) {
331 nextEvent = gb->memory.hdmaNext;
332 }
333 }
334 return nextEvent;
335}
336
337void GBMemoryDMA(struct GB* gb, uint16_t base) {
338 if (base > 0xF100) {
339 return;
340 }
341 gb->cpu->memory.store8 = GBDMAStore8;
342 gb->cpu->memory.load8 = GBDMALoad8;
343 gb->cpu->memory.cpuLoad8 = GBDMALoad8;
344 gb->memory.dmaNext = gb->cpu->cycles + 8;
345 if (gb->memory.dmaNext < gb->cpu->nextEvent) {
346 gb->cpu->nextEvent = gb->memory.dmaNext;
347 }
348 gb->memory.dmaSource = base;
349 gb->memory.dmaDest = 0;
350 gb->memory.dmaRemaining = 0xA0;
351}
352
353void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
354 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
355 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
356 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
357 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
358 gb->memory.hdmaSource &= 0xFFF0;
359 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
360 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
361 return;
362 }
363 gb->memory.hdmaDest &= 0x1FF0;
364 gb->memory.hdmaDest |= 0x8000;
365 bool wasHdma = gb->memory.isHdma;
366 gb->memory.isHdma = value & 0x80;
367 if (!wasHdma && !gb->memory.isHdma) {
368 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
369 gb->memory.hdmaNext = gb->cpu->cycles;
370 gb->cpu->nextEvent = gb->cpu->cycles;
371 }
372}
373
374void _GBMemoryDMAService(struct GB* gb) {
375 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
376 // TODO: Can DMA write OAM during modes 2-3?
377 gb->video.oam.raw[gb->memory.dmaDest] = b;
378 ++gb->memory.dmaSource;
379 ++gb->memory.dmaDest;
380 --gb->memory.dmaRemaining;
381 if (gb->memory.dmaRemaining) {
382 gb->memory.dmaNext += 4;
383 } else {
384 gb->memory.dmaNext = INT_MAX;
385 gb->cpu->memory.store8 = GBStore8;
386 gb->cpu->memory.load8 = GBLoad8;
387 }
388}
389
390void _GBMemoryHDMAService(struct GB* gb) {
391 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
392 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
393 ++gb->memory.hdmaSource;
394 ++gb->memory.hdmaDest;
395 --gb->memory.hdmaRemaining;
396 gb->cpu->cycles += 2;
397 if (gb->memory.hdmaRemaining) {
398 gb->memory.hdmaNext += 2;
399 } else {
400 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
401 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
402 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
403 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
404 if (gb->memory.isHdma) {
405 --gb->memory.io[REG_HDMA5];
406 if (gb->memory.io[REG_HDMA5] == 0xFF) {
407 gb->memory.isHdma = false;
408 }
409 } else {
410 gb->memory.io[REG_HDMA5] |= 0x80;
411 }
412 }
413}
414
415struct OAMBlock {
416 uint16_t low;
417 uint16_t high;
418};
419
420static const struct OAMBlock _oamBlockDMG[] = {
421 { 0xA000, 0xFE00 },
422 { 0xA000, 0xFE00 },
423 { 0xA000, 0xFE00 },
424 { 0xA000, 0xFE00 },
425 { 0x8000, 0xA000 },
426 { 0xA000, 0xFE00 },
427 { 0xA000, 0xFE00 },
428 { 0xA000, 0xFE00 },
429};
430
431static const struct OAMBlock _oamBlockCGB[] = {
432 { 0xA000, 0xC000 },
433 { 0xA000, 0xC000 },
434 { 0xA000, 0xC000 },
435 { 0xA000, 0xC000 },
436 { 0x8000, 0xA000 },
437 { 0xA000, 0xC000 },
438 { 0xC000, 0xFE00 },
439 { 0xA000, 0xC000 },
440};
441
442uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
443 struct GB* gb = (struct GB*) cpu->master;
444 struct GBMemory* memory = &gb->memory;
445 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
446 block = &block[memory->dmaSource >> 13];
447 if (address >= block->low && address < block->high) {
448 return 0xFF;
449 }
450 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
451 return 0xFF;
452 }
453 return GBLoad8(cpu, address);
454}
455
456void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
457 struct GB* gb = (struct GB*) cpu->master;
458 struct GBMemory* memory = &gb->memory;
459 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
460 block = &block[memory->dmaSource >> 13];
461 if (address >= block->low && address < block->high) {
462 return;
463 }
464 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
465 return;
466 }
467 GBStore8(cpu, address, value);
468}
469
470uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
471
472void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
473
474static void _switchBank(struct GBMemory* memory, int bank) {
475 size_t bankStart = bank * GB_SIZE_CART_BANK0;
476 if (bankStart + GB_SIZE_CART_BANK0 > memory->romSize) {
477 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
478 bankStart &= (memory->romSize - 1);
479 bank = bankStart / GB_SIZE_CART_BANK0;
480 }
481 memory->romBank = &memory->rom[bankStart];
482 memory->currentBank = bank;
483}
484
485static void _switchSramBank(struct GBMemory* memory, int bank) {
486 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
487 memory->sramBank = &memory->sram[bankStart];
488 memory->sramCurrentBank = bank;
489}
490
491static void _latchRtc(struct GBMemory* memory) {
492 time_t t;
493 struct mRTCSource* rtc = memory->rtc;
494 if (rtc) {
495 if (rtc->sample) {
496 rtc->sample(rtc);
497 }
498 t = rtc->unixTime(rtc);
499 } else {
500 t = time(0);
501 }
502 struct tm date;
503 localtime_r(&t, &date);
504 memory->rtcRegs[0] = date.tm_sec;
505 memory->rtcRegs[1] = date.tm_min;
506 memory->rtcRegs[2] = date.tm_hour;
507 memory->rtcRegs[3] = date.tm_yday; // TODO: Persist day counter
508 memory->rtcRegs[4] &= 0xF0;
509 memory->rtcRegs[4] |= date.tm_yday >> 8;
510}
511
512void _GBMBC1(struct GBMemory* memory, uint16_t address, uint8_t value) {
513 int bank = value & 0x1F;
514 switch (address >> 13) {
515 case 0x0:
516 switch (value) {
517 case 0:
518 memory->sramAccess = false;
519 break;
520 case 0xA:
521 memory->sramAccess = true;
522 _switchSramBank(memory, memory->sramCurrentBank);
523 break;
524 default:
525 // TODO
526 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
527 break;
528 }
529 break;
530 case 0x1:
531 if (!bank) {
532 ++bank;
533 }
534 _switchBank(memory, bank | (memory->currentBank & 0x60));
535 break;
536 case 0x2:
537 bank &= 3;
538 if (!memory->mbcState.mbc1.mode) {
539 _switchBank(memory, (bank << 5) | (memory->currentBank & 0x1F));
540 } else {
541 _switchSramBank(memory, bank);
542 }
543 break;
544 case 0x3:
545 memory->mbcState.mbc1.mode = value & 1;
546 if (memory->mbcState.mbc1.mode) {
547 _switchBank(memory, memory->currentBank & 0x1F);
548 } else {
549 _switchSramBank(memory, 0);
550 }
551 break;
552 default:
553 // TODO
554 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
555 break;
556 }
557}
558
559void _GBMBC2(struct GBMemory* memory, uint16_t address, uint8_t value) {
560 int bank = value & 0xF;
561 switch (address >> 13) {
562 case 0x0:
563 switch (value) {
564 case 0:
565 memory->sramAccess = false;
566 break;
567 case 0xA:
568 memory->sramAccess = true;
569 _switchSramBank(memory, memory->sramCurrentBank);
570 break;
571 default:
572 // TODO
573 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
574 break;
575 }
576 break;
577 case 0x1:
578 if (!bank) {
579 ++bank;
580 }
581 _switchBank(memory, bank);
582 break;
583 default:
584 // TODO
585 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
586 break;
587 }}
588
589void _GBMBC3(struct GBMemory* memory, uint16_t address, uint8_t value) {
590 int bank = value & 0x7F;
591 switch (address >> 13) {
592 case 0x0:
593 switch (value) {
594 case 0:
595 memory->sramAccess = false;
596 break;
597 case 0xA:
598 memory->sramAccess = true;
599 _switchSramBank(memory, memory->sramCurrentBank);
600 break;
601 default:
602 // TODO
603 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
604 break;
605 }
606 break;
607 case 0x1:
608 if (!bank) {
609 ++bank;
610 }
611 _switchBank(memory, bank);
612 break;
613 case 0x2:
614 if (value < 4) {
615 _switchSramBank(memory, value);
616 memory->rtcAccess = false;
617 } else if (value >= 8 && value <= 0xC) {
618 memory->activeRtcReg = value - 8;
619 memory->rtcAccess = true;
620 }
621 break;
622 case 0x3:
623 if (memory->rtcLatched && value == 0) {
624 memory->rtcLatched = value;
625 } else if (!memory->rtcLatched && value == 1) {
626 _latchRtc(memory);
627 }
628 break;
629 }
630}
631
632void _GBMBC5(struct GBMemory* memory, uint16_t address, uint8_t value) {
633 int bank;
634 switch (address >> 12) {
635 case 0x0:
636 case 0x1:
637 switch (value) {
638 case 0:
639 memory->sramAccess = false;
640 break;
641 case 0xA:
642 memory->sramAccess = true;
643 _switchSramBank(memory, memory->sramCurrentBank);
644 break;
645 default:
646 // TODO
647 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
648 break;
649 }
650 break;
651 case 0x2:
652 bank = (memory->currentBank & 0x100) | value;
653 _switchBank(memory, bank);
654 break;
655 case 0x3:
656 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
657 _switchBank(memory, bank);
658 break;
659 case 0x4:
660 case 0x5:
661 if (memory->mbcType == GB_MBC5_RUMBLE) {
662 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
663 value &= ~8;
664 }
665 _switchSramBank(memory, value & 0xF);
666 break;
667 default:
668 // TODO
669 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
670 break;
671 }
672}
673
674void _GBMBC6(struct GBMemory* memory, uint16_t address, uint8_t value) {
675 // TODO
676 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
677}
678
679void _GBMBC7(struct GBMemory* memory, uint16_t address, uint8_t value) {
680 int bank = value & 0x7F;
681 switch (address >> 13) {
682 case 0x1:
683 _switchBank(memory, bank);
684 break;
685 case 0x2:
686 if (value < 0x10) {
687 _switchSramBank(memory, value);
688 }
689 break;
690 default:
691 // TODO
692 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
693 break;
694 }
695}
696
697uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
698 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
699 switch (address & 0xF0) {
700 case 0x00:
701 case 0x10:
702 case 0x60:
703 case 0x70:
704 return 0;
705 case 0x20:
706 if (memory->rotation && memory->rotation->readTiltX) {
707 int32_t x = -memory->rotation->readTiltX(memory->rotation);
708 x >>= 21;
709 x += 2047;
710 return x;
711 }
712 return 0xFF;
713 case 0x30:
714 if (memory->rotation && memory->rotation->readTiltX) {
715 int32_t x = -memory->rotation->readTiltX(memory->rotation);
716 x >>= 21;
717 x += 2047;
718 return x >> 8;
719 }
720 return 7;
721 case 0x40:
722 if (memory->rotation && memory->rotation->readTiltY) {
723 int32_t y = -memory->rotation->readTiltY(memory->rotation);
724 y >>= 21;
725 y += 2047;
726 return y;
727 }
728 return 0xFF;
729 case 0x50:
730 if (memory->rotation && memory->rotation->readTiltY) {
731 int32_t y = -memory->rotation->readTiltY(memory->rotation);
732 y >>= 21;
733 y += 2047;
734 return y >> 8;
735 }
736 return 7;
737 case 0x80:
738 return (mbc7->sr >> 16) & 1;
739 default:
740 return 0xFF;
741 }
742}
743
744void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
745 if ((address & 0xF0) != 0x80) {
746 return;
747 }
748 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
749 GBMBC7Field old = memory->mbcState.mbc7.field;
750 mbc7->field = GBMBC7FieldClearIO(value);
751 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
752 if (mbc7->state == GBMBC7_STATE_WRITE) {
753 if (mbc7->writable) {
754 memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
755 memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
756 }
757 mbc7->sr = 0x1FFFF;
758 mbc7->state = GBMBC7_STATE_NULL;
759 } else {
760 mbc7->state = GBMBC7_STATE_IDLE;
761 }
762 }
763 if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
764 if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
765 mbc7->sr <<= 1;
766 mbc7->sr |= GBMBC7FieldGetIO(value);
767 ++mbc7->srBits;
768 }
769 switch (mbc7->state) {
770 case GBMBC7_STATE_IDLE:
771 if (GBMBC7FieldIsIO(value)) {
772 mbc7->state = GBMBC7_STATE_READ_COMMAND;
773 mbc7->srBits = 0;
774 mbc7->sr = 0;
775 }
776 break;
777 case GBMBC7_STATE_READ_COMMAND:
778 if (mbc7->srBits == 2) {
779 mbc7->state = GBMBC7_STATE_READ_ADDRESS;
780 mbc7->srBits = 0;
781 mbc7->command = mbc7->sr;
782 }
783 break;
784 case GBMBC7_STATE_READ_ADDRESS:
785 if (mbc7->srBits == 8) {
786 mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
787 mbc7->srBits = 0;
788 mbc7->address = mbc7->sr;
789 if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
790 switch (mbc7->address >> 6) {
791 case 0:
792 mbc7->writable = false;
793 mbc7->state = GBMBC7_STATE_NULL;
794 break;
795 case 3:
796 mbc7->writable = true;
797 mbc7->state = GBMBC7_STATE_NULL;
798 break;
799 }
800 }
801 }
802 break;
803 case GBMBC7_STATE_COMMAND_0:
804 if (mbc7->srBits == 16) {
805 switch (mbc7->address >> 6) {
806 case 0:
807 mbc7->writable = false;
808 mbc7->state = GBMBC7_STATE_NULL;
809 break;
810 case 1:
811 mbc7->state = GBMBC7_STATE_WRITE;
812 if (mbc7->writable) {
813 int i;
814 for (i = 0; i < 256; ++i) {
815 memory->sramBank[i * 2] = mbc7->sr >> 8;
816 memory->sramBank[i * 2 + 1] = mbc7->sr;
817 }
818 }
819 break;
820 case 2:
821 mbc7->state = GBMBC7_STATE_WRITE;
822 if (mbc7->writable) {
823 int i;
824 for (i = 0; i < 256; ++i) {
825 memory->sramBank[i * 2] = 0xFF;
826 memory->sramBank[i * 2 + 1] = 0xFF;
827 }
828 }
829 break;
830 case 3:
831 mbc7->writable = true;
832 mbc7->state = GBMBC7_STATE_NULL;
833 break;
834 }
835 }
836 break;
837 case GBMBC7_STATE_COMMAND_SR_WRITE:
838 if (mbc7->srBits == 16) {
839 mbc7->srBits = 0;
840 mbc7->state = GBMBC7_STATE_WRITE;
841 }
842 break;
843 case GBMBC7_STATE_COMMAND_SR_READ:
844 if (mbc7->srBits == 1) {
845 mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
846 mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
847 mbc7->srBits = 0;
848 mbc7->state = GBMBC7_STATE_READ;
849 }
850 break;
851 case GBMBC7_STATE_COMMAND_SR_FILL:
852 if (mbc7->srBits == 16) {
853 mbc7->sr = 0xFFFF;
854 mbc7->srBits = 0;
855 mbc7->state = GBMBC7_STATE_WRITE;
856 }
857 break;
858 default:
859 break;
860 }
861 } else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
862 if (mbc7->state == GBMBC7_STATE_READ) {
863 mbc7->sr <<= 1;
864 ++mbc7->srBits;
865 if (mbc7->srBits == 16) {
866 mbc7->srBits = 0;
867 mbc7->state = GBMBC7_STATE_NULL;
868 }
869 }
870 }
871}