src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-arm.h"
7
8#include "arm.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 int immediate = (opcode & 0x00000F80) >> 7;
20 if (!immediate) {
21 cpu->shifterOperand = cpu->gprs[rm];
22 cpu->shifterCarryOut = cpu->cpsr.c;
23 } else {
24 cpu->shifterOperand = cpu->gprs[rm] << immediate;
25 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
26 }
27}
28
29static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
30 int rm = opcode & 0x0000000F;
31 int rs = (opcode >> 8) & 0x0000000F;
32 ++cpu->cycles;
33 int shift = cpu->gprs[rs];
34 if (rs == ARM_PC) {
35 shift += 4;
36 }
37 shift &= 0xFF;
38 int32_t shiftVal = cpu->gprs[rm];
39 if (rm == ARM_PC) {
40 shiftVal += 4;
41 }
42 if (!shift) {
43 cpu->shifterOperand = shiftVal;
44 cpu->shifterCarryOut = cpu->cpsr.c;
45 } else if (shift < 32) {
46 cpu->shifterOperand = shiftVal << shift;
47 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
48 } else if (shift == 32) {
49 cpu->shifterOperand = 0;
50 cpu->shifterCarryOut = shiftVal & 1;
51 } else {
52 cpu->shifterOperand = 0;
53 cpu->shifterCarryOut = 0;
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 int immediate = (opcode & 0x00000F80) >> 7;
60 if (immediate) {
61 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
62 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
63 } else {
64 cpu->shifterOperand = 0;
65 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
66 }
67}
68
69static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
70 int rm = opcode & 0x0000000F;
71 int rs = (opcode >> 8) & 0x0000000F;
72 ++cpu->cycles;
73 int shift = cpu->gprs[rs];
74 if (rs == ARM_PC) {
75 shift += 4;
76 }
77 shift &= 0xFF;
78 uint32_t shiftVal = cpu->gprs[rm];
79 if (rm == ARM_PC) {
80 shiftVal += 4;
81 }
82 if (!shift) {
83 cpu->shifterOperand = shiftVal;
84 cpu->shifterCarryOut = cpu->cpsr.c;
85 } else if (shift < 32) {
86 cpu->shifterOperand = shiftVal >> shift;
87 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
88 } else if (shift == 32) {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = shiftVal >> 31;
91 } else {
92 cpu->shifterOperand = 0;
93 cpu->shifterCarryOut = 0;
94 }
95}
96
97static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
98 int rm = opcode & 0x0000000F;
99 int immediate = (opcode & 0x00000F80) >> 7;
100 if (immediate) {
101 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
102 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
103 } else {
104 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
105 cpu->shifterOperand = cpu->shifterCarryOut;
106 }
107}
108
109static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
110 int rm = opcode & 0x0000000F;
111 int rs = (opcode >> 8) & 0x0000000F;
112 ++cpu->cycles;
113 int shift = cpu->gprs[rs];
114 if (rs == ARM_PC) {
115 shift += 4;
116 }
117 shift &= 0xFF;
118 int shiftVal = cpu->gprs[rm];
119 if (rm == ARM_PC) {
120 shiftVal += 4;
121 }
122 if (!shift) {
123 cpu->shifterOperand = shiftVal;
124 cpu->shifterCarryOut = cpu->cpsr.c;
125 } else if (shift < 32) {
126 cpu->shifterOperand = shiftVal >> shift;
127 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
128 } else if (cpu->gprs[rm] >> 31) {
129 cpu->shifterOperand = 0xFFFFFFFF;
130 cpu->shifterCarryOut = 1;
131 } else {
132 cpu->shifterOperand = 0;
133 cpu->shifterCarryOut = 0;
134 }
135}
136
137static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
138 int rm = opcode & 0x0000000F;
139 int immediate = (opcode & 0x00000F80) >> 7;
140 if (immediate) {
141 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
142 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
143 } else {
144 // RRX
145 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
146 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
147 }
148}
149
150static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
151 int rm = opcode & 0x0000000F;
152 int rs = (opcode >> 8) & 0x0000000F;
153 ++cpu->cycles;
154 int shift = cpu->gprs[rs];
155 if (rs == ARM_PC) {
156 shift += 4;
157 }
158 shift &= 0xFF;
159 int shiftVal = cpu->gprs[rm];
160 if (rm == ARM_PC) {
161 shiftVal += 4;
162 }
163 int rotate = shift & 0x1F;
164 if (!shift) {
165 cpu->shifterOperand = shiftVal;
166 cpu->shifterCarryOut = cpu->cpsr.c;
167 } else if (rotate) {
168 cpu->shifterOperand = ROR(shiftVal, rotate);
169 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
170 } else {
171 cpu->shifterOperand = shiftVal;
172 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
173 }
174}
175
176static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
177 int rotate = (opcode & 0x00000F00) >> 7;
178 int immediate = opcode & 0x000000FF;
179 if (!rotate) {
180 cpu->shifterOperand = immediate;
181 cpu->shifterCarryOut = cpu->cpsr.c;
182 } else {
183 cpu->shifterOperand = ROR(immediate, rotate);
184 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
185 }
186}
187
188// Instruction definitions
189// Beware pre-processor antics
190
191#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
192
193#define ARM_ADDITION_S(M, N, D) \
194 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
195 cpu->cpsr = cpu->spsr; \
196 _ARMReadCPSR(cpu); \
197 } else { \
198 cpu->cpsr.n = ARM_SIGN(D); \
199 cpu->cpsr.z = !(D); \
200 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
201 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
202 }
203
204#define ARM_SUBTRACTION_S(M, N, D) \
205 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
206 cpu->cpsr = cpu->spsr; \
207 _ARMReadCPSR(cpu); \
208 } else { \
209 cpu->cpsr.n = ARM_SIGN(D); \
210 cpu->cpsr.z = !(D); \
211 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
212 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
213 }
214
215#define ARM_NEUTRAL_S(M, N, D) \
216 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
217 cpu->cpsr = cpu->spsr; \
218 _ARMReadCPSR(cpu); \
219 } else { \
220 cpu->cpsr.n = ARM_SIGN(D); \
221 cpu->cpsr.z = !(D); \
222 cpu->cpsr.c = cpu->shifterCarryOut; \
223 }
224
225#define ARM_NEUTRAL_HI_S(DLO, DHI) \
226 cpu->cpsr.n = ARM_SIGN(DHI); \
227 cpu->cpsr.z = !((DHI) | (DLO));
228
229#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
230#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
231#define ADDR_MODE_2_ADDRESS (address)
232#define ADDR_MODE_2_RN (cpu->gprs[rn])
233#define ADDR_MODE_2_RM (cpu->gprs[rm])
234#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
235#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
236#define ADDR_MODE_2_WRITEBACK(ADDR) \
237 cpu->gprs[rn] = ADDR; \
238 if (UNLIKELY(rn == ARM_PC)) { \
239 ARM_WRITE_PC; \
240 }
241
242#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
243#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
244#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
245#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
246
247#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
248#define ADDR_MODE_3_RN ADDR_MODE_2_RN
249#define ADDR_MODE_3_RM ADDR_MODE_2_RM
250#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
251#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
252#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
253
254#define ADDR_MODE_4_WRITEBACK_LDM \
255 if (!((1 << rn) & rs)) { \
256 cpu->gprs[rn] = address; \
257 }
258
259#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
260
261#define ARM_LOAD_POST_BODY \
262 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
263 if (rd == ARM_PC) { \
264 ARM_WRITE_PC; \
265 }
266
267#define ARM_STORE_POST_BODY \
268 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
269
270#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
271 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
272 int currentCycles = ARM_PREFETCH_CYCLES; \
273 BODY; \
274 cpu->cycles += currentCycles; \
275 }
276
277#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
278 DEFINE_INSTRUCTION_ARM(NAME, \
279 int rd = (opcode >> 12) & 0xF; \
280 int rn = (opcode >> 16) & 0xF; \
281 UNUSED(rn); \
282 SHIFTER(cpu, opcode); \
283 BODY; \
284 S_BODY; \
285 if (rd == ARM_PC) { \
286 if (cpu->executionMode == MODE_ARM) { \
287 ARM_WRITE_PC; \
288 } else { \
289 THUMB_WRITE_PC; \
290 } \
291 })
292
293#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
312
313#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
323
324#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
325 DEFINE_INSTRUCTION_ARM(NAME, \
326 int rd = (opcode >> 12) & 0xF; \
327 int rdHi = (opcode >> 16) & 0xF; \
328 int rs = (opcode >> 8) & 0xF; \
329 int rm = opcode & 0xF; \
330 if (rdHi == ARM_PC || rd == ARM_PC) { \
331 return; \
332 } \
333 ARM_WAIT_MUL(cpu->gprs[rs]); \
334 BODY; \
335 S_BODY; \
336 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
337
338#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
339 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
340 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
341
342#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
343 DEFINE_INSTRUCTION_ARM(NAME, \
344 uint32_t address; \
345 int rn = (opcode >> 16) & 0xF; \
346 int rd = (opcode >> 12) & 0xF; \
347 int rm = opcode & 0xF; \
348 UNUSED(rm); \
349 address = ADDRESS; \
350 WRITEBACK; \
351 BODY;)
352
353#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
360
361#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
372
373#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
386
387#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
390
391#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
392 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
393 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
394 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
395 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
398
399#define ARM_MS_PRE \
400 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
401 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
402
403#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
404
405#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
406 DEFINE_INSTRUCTION_ARM(NAME, \
407 int rn = (opcode >> 16) & 0xF; \
408 int rs = opcode & 0x0000FFFF; \
409 uint32_t address = cpu->gprs[rn]; \
410 S_PRE; \
411 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
412 S_POST; \
413 POST_BODY; \
414 WRITEBACK;)
415
416
417#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
419 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
420 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
421 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
422 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
423 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
424 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
425 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
426 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
427 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
428 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
429 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
430 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
431 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
432 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
433 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
434
435// Begin ALU definitions
436
437DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
438 int32_t n = cpu->gprs[rn];
439 cpu->gprs[rd] = n + cpu->shifterOperand;)
440
441DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
442 int32_t n = cpu->gprs[rn];
443 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
444
445DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
446 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
447
448DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
449 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
450
451DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
452 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
453
454DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
455 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
456
457DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
458 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
459
460DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
461 cpu->gprs[rd] = cpu->shifterOperand;)
462
463DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
464 cpu->gprs[rd] = ~cpu->shifterOperand;)
465
466DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
467 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
468
469DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
470 int32_t n = cpu->gprs[rn];
471 cpu->gprs[rd] = cpu->shifterOperand - n;)
472
473DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
474 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
475 cpu->gprs[rd] = cpu->shifterOperand - n;)
476
477DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
478 int32_t n = cpu->gprs[rn];
479 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
480 cpu->gprs[rd] = n - shifterOperand;)
481
482DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
483 int32_t n = cpu->gprs[rn];
484 cpu->gprs[rd] = n - cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
487 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
490 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
491
492// End ALU definitions
493
494// Begin multiply definitions
495
496DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
497DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
498
499DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
500 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
501 int32_t dm = cpu->gprs[rd];
502 int32_t dn = d;
503 cpu->gprs[rd] = dm + dn;
504 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
505 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
506
507DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
508 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
509 cpu->gprs[rd] = d;
510 cpu->gprs[rdHi] = d >> 32;,
511 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
512
513DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
514 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
515 int32_t dm = cpu->gprs[rd];
516 int32_t dn = d;
517 cpu->gprs[rd] = dm + dn;
518 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
519 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
520
521DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
522 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
523 cpu->gprs[rd] = d;
524 cpu->gprs[rdHi] = d >> 32;,
525 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
526
527// End multiply definitions
528
529// Begin load/store definitions
530
531DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
532DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
533DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
534DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
535DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
536DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
537DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
538DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
539
540DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
541 enum PrivilegeMode priv = cpu->privilegeMode;
542 ARMSetPrivilegeMode(cpu, MODE_USER);
543 cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles);
544 ARMSetPrivilegeMode(cpu, priv);
545 ARM_LOAD_POST_BODY;)
546
547DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
548 enum PrivilegeMode priv = cpu->privilegeMode;
549 ARMSetPrivilegeMode(cpu, MODE_USER);
550 cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles);
551 ARMSetPrivilegeMode(cpu, priv);
552 ARM_LOAD_POST_BODY;)
553
554DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
555 enum PrivilegeMode priv = cpu->privilegeMode;
556 ARMSetPrivilegeMode(cpu, MODE_USER);
557 cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles);
558 ARMSetPrivilegeMode(cpu, priv);
559 ARM_STORE_POST_BODY;)
560
561DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
562 enum PrivilegeMode priv = cpu->privilegeMode;
563 ARMSetPrivilegeMode(cpu, MODE_USER);
564 cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles);
565 ARMSetPrivilegeMode(cpu, priv);
566 ARM_STORE_POST_BODY;)
567
568DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
569 load,
570 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
571 if (rs & 0x8000) {
572 ARM_WRITE_PC;
573 })
574
575DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
576 store,
577 ARM_STORE_POST_BODY;)
578
579DEFINE_INSTRUCTION_ARM(SWP,
580 int rm = opcode & 0xF;
581 int rd = (opcode >> 12) & 0xF;
582 int rn = (opcode >> 16) & 0xF;
583 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
584 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
585 cpu->gprs[rd] = d;)
586
587DEFINE_INSTRUCTION_ARM(SWPB,
588 int rm = opcode & 0xF;
589 int rd = (opcode >> 12) & 0xF;
590 int rn = (opcode >> 16) & 0xF;
591 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
592 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
593 cpu->gprs[rd] = d;)
594
595// End load/store definitions
596
597// Begin branch definitions
598
599DEFINE_INSTRUCTION_ARM(B,
600 int32_t offset = opcode << 8;
601 offset >>= 6;
602 cpu->gprs[ARM_PC] += offset;
603 ARM_WRITE_PC;)
604
605DEFINE_INSTRUCTION_ARM(BL,
606 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
607 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
608 cpu->gprs[ARM_PC] += immediate >> 6;
609 ARM_WRITE_PC;)
610
611DEFINE_INSTRUCTION_ARM(BX,
612 int rm = opcode & 0x0000000F;
613 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
614 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
615 if (cpu->executionMode == MODE_THUMB) {
616 THUMB_WRITE_PC;
617 } else {
618 ARM_WRITE_PC;
619 })
620
621// End branch definitions
622
623// Begin coprocessor definitions
624
625DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
626DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
627DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
628DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
629DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
630
631// Begin miscellaneous definitions
632
633DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
634DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
635
636DEFINE_INSTRUCTION_ARM(MSR,
637 int c = opcode & 0x00010000;
638 int f = opcode & 0x00080000;
639 int32_t operand = cpu->gprs[opcode & 0x0000000F];
640 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
641 if (mask & PSR_USER_MASK) {
642 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
643 }
644 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
645 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
646 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
647 }
648 _ARMReadCPSR(cpu);)
649
650DEFINE_INSTRUCTION_ARM(MSRR,
651 int c = opcode & 0x00010000;
652 int f = opcode & 0x00080000;
653 int32_t operand = cpu->gprs[opcode & 0x0000000F];
654 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
655 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
656 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
657
658DEFINE_INSTRUCTION_ARM(MRS, \
659 int rd = (opcode >> 12) & 0xF; \
660 cpu->gprs[rd] = cpu->cpsr.packed;)
661
662DEFINE_INSTRUCTION_ARM(MRSR, \
663 int rd = (opcode >> 12) & 0xF; \
664 cpu->gprs[rd] = cpu->spsr.packed;)
665
666DEFINE_INSTRUCTION_ARM(MSRI,
667 int c = opcode & 0x00010000;
668 int f = opcode & 0x00080000;
669 int rotate = (opcode & 0x00000F00) >> 7;
670 int32_t operand = ROR(opcode & 0x000000FF, rotate);
671 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
672 if (mask & PSR_USER_MASK) {
673 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
674 }
675 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
676 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
677 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
678 }
679 _ARMReadCPSR(cpu);)
680
681DEFINE_INSTRUCTION_ARM(MSRRI,
682 int c = opcode & 0x00010000;
683 int f = opcode & 0x00080000;
684 int rotate = (opcode & 0x00000F00) >> 7;
685 int32_t operand = ROR(opcode & 0x000000FF, rotate);
686 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
687 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
688 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
689
690DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
691
692const ARMInstruction _armTable[0x1000] = {
693 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
694};