src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259
260#define ADDR_MODE_4_WRITEBACK_LDM \
261 if (!((1 << rn) & rs)) { \
262 cpu->gprs[rn] = address; \
263 }
264
265#define ADDR_MODE_4_WRITEBACK_LDMv5 \
266 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
267 cpu->gprs[rn] = address; \
268 }
269
270#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
271
272#define ARM_LOAD_POST_BODY \
273 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
274 if (rd == ARM_PC) { \
275 ARM_WRITE_PC; \
276 }
277
278#define ARM_STORE_POST_BODY \
279 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
280
281#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
282 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
283 int currentCycles = ARM_PREFETCH_CYCLES; \
284 BODY; \
285 cpu->cycles += currentCycles; \
286 }
287
288#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
289 DEFINE_INSTRUCTION_ARM(NAME, \
290 int rd = (opcode >> 12) & 0xF; \
291 int rn = (opcode >> 16) & 0xF; \
292 UNUSED(rn); \
293 SHIFTER(cpu, opcode); \
294 BODY; \
295 S_BODY; \
296 if (rd == ARM_PC) { \
297 if (cpu->executionMode == MODE_ARM) { \
298 ARM_WRITE_PC; \
299 } else { \
300 THUMB_WRITE_PC; \
301 } \
302 })
303
304#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
315
316#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
322
323#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
324 DEFINE_INSTRUCTION_ARM(NAME, \
325 int rd = (opcode >> 16) & 0xF; \
326 int rs = (opcode >> 8) & 0xF; \
327 int rm = opcode & 0xF; \
328 if (rd == ARM_PC) { \
329 return; \
330 } \
331 ARM_WAIT_MUL(cpu->gprs[rs]); \
332 BODY; \
333 S_BODY; \
334 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
335
336#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
337 DEFINE_INSTRUCTION_ARM(NAME, \
338 int rd = (opcode >> 12) & 0xF; \
339 int rdHi = (opcode >> 16) & 0xF; \
340 int rs = (opcode >> 8) & 0xF; \
341 int rm = opcode & 0xF; \
342 if (rdHi == ARM_PC || rd == ARM_PC) { \
343 return; \
344 } \
345 currentCycles += cpu->memory.stall(cpu, WAIT); \
346 BODY; \
347 S_BODY; \
348 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
349
350#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
351 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
352 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
353
354#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
355 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
356 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
357
358#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
359 DEFINE_INSTRUCTION_ARM(NAME, \
360 int rd = (opcode >> 16) & 0xF; \
361 int rs = (opcode >> 8) & 0xF; \
362 int rn = (opcode >> 12) & 0xF; \
363 int rm = opcode & 0xF; \
364 UNUSED(rn); \
365 if (rd == ARM_PC) { \
366 return; \
367 } \
368 /* TODO: Timing */ \
369 int32_t x; \
370 int32_t y; \
371 BODY; \
372 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
373
374#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
375 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
376 x = ARM_SXT_16(cpu->gprs[rm]); \
377 y = ARM_SXT_16(cpu->gprs[rs]); \
378 BODY) \
379 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
380 x = ARM_SXT_16(cpu->gprs[rm]); \
381 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
382 BODY) \
383 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
384 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
385 y = ARM_SXT_16(cpu->gprs[rs]); \
386 BODY) \
387 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
388 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
389 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
390 BODY)
391
392#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
393 DEFINE_INSTRUCTION_ARM(NAME, \
394 uint32_t address; \
395 int rn = (opcode >> 16) & 0xF; \
396 int rd = (opcode >> 12) & 0xF; \
397 int rm = opcode & 0xF; \
398 UNUSED(rm); \
399 address = ADDRESS; \
400 WRITEBACK; \
401 BODY;)
402
403#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
410
411#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
422
423#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
424 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
425 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
428 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
429 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
430 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
431 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
433 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
434 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
435 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
436
437#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
438 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
439 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
440
441#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
442 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
443 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
444 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
445 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
446 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
447 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
448
449#define ARM_MS_PRE \
450 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
451 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
452
453#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
454
455#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
456 DEFINE_INSTRUCTION_ARM(NAME, \
457 int rn = (opcode >> 16) & 0xF; \
458 int rs = opcode & 0x0000FFFF; \
459 uint32_t address = cpu->gprs[rn]; \
460 S_PRE; \
461 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
462 S_POST; \
463 POST_BODY; \
464 WRITEBACK;)
465
466
467#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
469 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
470 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
471 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
472 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
473 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
474 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
475 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
476
477#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
478 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
479 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
480 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
481 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
482 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
483 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
484 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
485 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
486 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
487
488// Begin ALU definitions
489
490DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
491 int32_t n = cpu->gprs[rn];
492 cpu->gprs[rd] = n + cpu->shifterOperand;)
493
494DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
495 int32_t n = cpu->gprs[rn];
496 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
497
498DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
502 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
505 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
506
507DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
508 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
509
510DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
511 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
512
513DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
514 cpu->gprs[rd] = cpu->shifterOperand;)
515
516DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
517 cpu->gprs[rd] = ~cpu->shifterOperand;)
518
519DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
520 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
521
522DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
523 int32_t n = cpu->gprs[rn];
524 cpu->gprs[rd] = cpu->shifterOperand - n;)
525
526DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
527 int32_t n = cpu->gprs[rn];
528 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
529
530DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
531 int32_t n = cpu->gprs[rn];
532 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
533
534DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
535 int32_t n = cpu->gprs[rn];
536 cpu->gprs[rd] = n - cpu->shifterOperand;)
537
538DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
539 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
540
541DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
542 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
543
544// End ALU definitions
545
546// Begin multiply definitions
547
548DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
549DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
550
551DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
552 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
553 int32_t dm = cpu->gprs[rd];
554 int32_t dn = d;
555 cpu->gprs[rd] = dm + dn;
556 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
557 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
558
559DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
560 int32_t dn = cpu->gprs[rn]; \
561 int32_t d = x * y; \
562 cpu->gprs[rd] = d + dn; \
563 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
564
565DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
566
567DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
568 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
569 cpu->gprs[rd] = d;
570 cpu->gprs[rdHi] = d >> 32;,
571 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
572
573DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
574 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
575 int32_t dm = cpu->gprs[rd];
576 int32_t dn = d;
577 cpu->gprs[rd] = dm + dn;
578 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
579 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
580
581DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
582 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
583 cpu->gprs[rd] = d;
584 cpu->gprs[rdHi] = d >> 32;,
585 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
586
587// End multiply definitions
588
589// Begin load/store definitions
590
591DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
592DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
593DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
594DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
595DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
596DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
597DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
598DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
599
600DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
601 enum PrivilegeMode priv = cpu->privilegeMode;
602 ARMSetPrivilegeMode(cpu, MODE_USER);
603 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
604 ARMSetPrivilegeMode(cpu, priv);
605 cpu->gprs[rd] = r;
606 ARM_LOAD_POST_BODY;)
607
608DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
609 enum PrivilegeMode priv = cpu->privilegeMode;
610 ARMSetPrivilegeMode(cpu, MODE_USER);
611 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
612 ARMSetPrivilegeMode(cpu, priv);
613 cpu->gprs[rd] = r;
614 ARM_LOAD_POST_BODY;)
615
616DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
617 enum PrivilegeMode priv = cpu->privilegeMode;
618 int32_t r = cpu->gprs[rd];
619 ARMSetPrivilegeMode(cpu, MODE_USER);
620 cpu->memory.store8(cpu, address, r, ¤tCycles);
621 ARMSetPrivilegeMode(cpu, priv);
622 ARM_STORE_POST_BODY;)
623
624DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
625 enum PrivilegeMode priv = cpu->privilegeMode;
626 int32_t r = cpu->gprs[rd];
627 ARMSetPrivilegeMode(cpu, MODE_USER);
628 cpu->memory.store32(cpu, address, r, ¤tCycles);
629 ARMSetPrivilegeMode(cpu, priv);
630 ARM_STORE_POST_BODY;)
631
632DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
633 load,
634 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
635 if (rs & 0x8000) {
636 ARM_WRITE_PC;
637 })
638
639DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
640 load,
641 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
642 if (rs & 0x8000) {
643 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
644 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
645 if (cpu->executionMode == MODE_THUMB) {
646 THUMB_WRITE_PC;
647 } else {
648 ARM_WRITE_PC;
649
650 }
651 })
652
653DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
654 store,
655 ARM_STORE_POST_BODY;)
656
657DEFINE_INSTRUCTION_ARM(SWP,
658 int rm = opcode & 0xF;
659 int rd = (opcode >> 12) & 0xF;
660 int rn = (opcode >> 16) & 0xF;
661 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
662 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
663 cpu->gprs[rd] = d;)
664
665DEFINE_INSTRUCTION_ARM(SWPB,
666 int rm = opcode & 0xF;
667 int rd = (opcode >> 12) & 0xF;
668 int rn = (opcode >> 16) & 0xF;
669 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
670 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
671 cpu->gprs[rd] = d;)
672
673// End load/store definitions
674
675// Begin branch definitions
676
677DEFINE_INSTRUCTION_ARM(B,
678 int32_t offset = opcode << 8;
679 offset >>= 6;
680 cpu->gprs[ARM_PC] += offset;
681 ARM_WRITE_PC;)
682
683DEFINE_INSTRUCTION_ARM(BL,
684 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
685 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
686 cpu->gprs[ARM_PC] += immediate >> 6;
687 ARM_WRITE_PC;)
688
689DEFINE_INSTRUCTION_ARM(BX,
690 int rm = opcode & 0x0000000F;
691 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
692 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
693 if (cpu->executionMode == MODE_THUMB) {
694 THUMB_WRITE_PC;
695 } else {
696 ARM_WRITE_PC;
697
698 })
699
700DEFINE_INSTRUCTION_ARM(BLX,
701 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
702 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
703 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
704 _ARMSetMode(cpu, MODE_THUMB);
705 THUMB_WRITE_PC;)
706
707DEFINE_INSTRUCTION_ARM(BLX2,
708 int rm = opcode & 0x0000000F;
709 int address = cpu->gprs[rm];
710 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
711 _ARMSetMode(cpu, address & 0x00000001);
712 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
713 if (cpu->executionMode == MODE_THUMB) {
714 THUMB_WRITE_PC;
715 } else {
716 ARM_WRITE_PC;
717 })
718
719// End branch definitions
720
721// Begin coprocessor definitions
722
723#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
724 DEFINE_INSTRUCTION_ARM(NAME, \
725 int op1 = (opcode >> 21) & 7; \
726 int op2 = (opcode >> 5) & 7; \
727 int rd = (opcode >> 12) & 0xF; \
728 int cp = (opcode >> 8) & 0xF; \
729 int crn = (opcode >> 16) & 0xF; \
730 int crm = opcode & 0xF; \
731 UNUSED(op1); \
732 UNUSED(op2); \
733 UNUSED(rd); \
734 UNUSED(crn); \
735 UNUSED(crm); \
736 BODY;)
737
738DEFINE_COPROCESSOR_INSTRUCTION(MRC,
739 if (cp == 15 && cpu->irqh.readCP15) {
740 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
741 } else {
742 ARM_STUB;
743 })
744
745DEFINE_COPROCESSOR_INSTRUCTION(MCR,
746 if (cp == 15 && cpu->irqh.writeCP15) {
747 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
748 } else {
749 ARM_STUB;
750 })
751
752DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
753DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
754DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
755
756// Begin miscellaneous definitions
757
758DEFINE_INSTRUCTION_ARM(CLZ,
759 int rm = opcode & 0xF;
760 int rd = (opcode >> 12) & 0xF;
761 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
762
763DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
764DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
765
766DEFINE_INSTRUCTION_ARM(MSR,
767 int c = opcode & 0x00010000;
768 int f = opcode & 0x00080000;
769 int32_t operand = cpu->gprs[opcode & 0x0000000F];
770 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
771 if (mask & PSR_USER_MASK) {
772 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
773 }
774 if (mask & PSR_STATE_MASK) {
775 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
776 }
777 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
778 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
779 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
780 }
781 _ARMReadCPSR(cpu);
782 if (cpu->executionMode == MODE_THUMB) {
783 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
784 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
785 } else {
786 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
787 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
788 })
789
790DEFINE_INSTRUCTION_ARM(MSRR,
791 int c = opcode & 0x00010000;
792 int f = opcode & 0x00080000;
793 int32_t operand = cpu->gprs[opcode & 0x0000000F];
794 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
795 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
796 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
797
798DEFINE_INSTRUCTION_ARM(MRS, \
799 int rd = (opcode >> 12) & 0xF; \
800 cpu->gprs[rd] = cpu->cpsr.packed;)
801
802DEFINE_INSTRUCTION_ARM(MRSR, \
803 int rd = (opcode >> 12) & 0xF; \
804 cpu->gprs[rd] = cpu->spsr.packed;)
805
806DEFINE_INSTRUCTION_ARM(MSRI,
807 int c = opcode & 0x00010000;
808 int f = opcode & 0x00080000;
809 int rotate = (opcode & 0x00000F00) >> 7;
810 int32_t operand = ROR(opcode & 0x000000FF, rotate);
811 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
812 if (mask & PSR_USER_MASK) {
813 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
814 }
815 if (mask & PSR_STATE_MASK) {
816 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
817 }
818 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
819 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
820 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
821 }
822 _ARMReadCPSR(cpu);
823 if (cpu->executionMode == MODE_THUMB) {
824 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
825 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
826 } else {
827 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
828 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
829 })
830
831DEFINE_INSTRUCTION_ARM(MSRRI,
832 int c = opcode & 0x00010000;
833 int f = opcode & 0x00080000;
834 int rotate = (opcode & 0x00000F00) >> 7;
835 int32_t operand = ROR(opcode & 0x000000FF, rotate);
836 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
837 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
838 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
839
840DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
841
842const ARMInstruction _armv4Table[0x1000] = {
843 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
844};
845
846const ARMInstruction _armv5Table[0x1000] = {
847 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
848};
849
850const ARMInstruction _armv4FTable[0x1000] = {
851 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
852};
853
854const ARMInstruction _armv5FTable[0x1000] = {
855 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
856};