1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12#include "gb/interface.h"
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_CART_MAX = 0x800000,
 48	GB_SIZE_VRAM = 0x4000,
 49	GB_SIZE_VRAM_BANK0 = 0x2000,
 50	GB_SIZE_EXTERNAL_RAM = 0x2000,
 51	GB_SIZE_WORKING_RAM = 0x8000,
 52	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 53	GB_SIZE_OAM = 0xA0,
 54	GB_SIZE_IO = 0x80,
 55	GB_SIZE_HRAM = 0x7F,
 56};
 57
 58enum {
 59	GB_SRAM_DIRT_NEW = 1,
 60	GB_SRAM_DIRT_SEEN = 2
 61};
 62
 63struct GBMemory;
 64typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
 65
 66DECL_BITFIELD(GBMBC7Field, uint8_t);
 67DECL_BIT(GBMBC7Field, SK, 6);
 68DECL_BIT(GBMBC7Field, CS, 7);
 69DECL_BIT(GBMBC7Field, IO, 1);
 70
 71enum GBMBC7MachineState {
 72	GBMBC7_STATE_NULL = -1,
 73	GBMBC7_STATE_IDLE = 0,
 74	GBMBC7_STATE_READ_COMMAND = 1,
 75	GBMBC7_STATE_READ_ADDRESS = 2,
 76	GBMBC7_STATE_COMMAND_0 = 3,
 77	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 78	GBMBC7_STATE_COMMAND_SR_READ = 5,
 79	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 80	GBMBC7_STATE_READ = 7,
 81	GBMBC7_STATE_WRITE = 8,
 82};
 83
 84struct GBMBC1State {
 85	int mode;
 86};
 87
 88struct GBMBC7State {
 89	enum GBMBC7MachineState state;
 90	uint32_t sr;
 91	uint8_t address;
 92	bool writable;
 93	int srBits;
 94	int command;
 95	GBMBC7Field field;
 96};
 97
 98union GBMBCState {
 99	struct GBMBC1State mbc1;
100	struct GBMBC7State mbc7;
101};
102
103struct mRotationSource;
104struct GBMemory {
105	uint8_t* rom;
106	uint8_t* romBase;
107	uint8_t* romBank;
108	enum GBMemoryBankControllerType mbcType;
109	GBMemoryBankController mbc;
110	union GBMBCState mbcState;
111	int currentBank;
112
113	uint8_t* wram;
114	uint8_t* wramBank;
115	int wramCurrentBank;
116
117	bool sramAccess;
118	uint8_t* sram;
119	uint8_t* sramBank;
120	int sramCurrentBank;
121
122	uint8_t io[GB_SIZE_IO];
123	bool ime;
124	uint8_t ie;
125
126	uint8_t hram[GB_SIZE_HRAM];
127
128	int32_t dmaNext;
129	uint16_t dmaSource;
130	uint16_t dmaDest;
131	int dmaRemaining;
132
133	int32_t hdmaNext;
134	uint16_t hdmaSource;
135	uint16_t hdmaDest;
136	int hdmaRemaining;
137	bool isHdma;
138
139	size_t romSize;
140
141	bool rtcAccess;
142	int activeRtcReg;
143	bool rtcLatched;
144	uint8_t rtcRegs[5];
145	time_t rtcLastLatch;
146	struct mRTCSource* rtc;
147	struct mRotationSource* rotation;
148	struct mRumble* rumble;
149};
150
151void GBMemoryInit(struct GB* gb);
152void GBMemoryDeinit(struct GB* gb);
153
154void GBMemoryReset(struct GB* gb);
155void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
156
157uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
158void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
159
160uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
161
162int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
163void GBMemoryDMA(struct GB* gb, uint16_t base);
164void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
165
166uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
167void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
168
169void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
170
171struct GBSerializedState;
172void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
173void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
174
175#endif