src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38
39static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
40static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
42static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
43
44static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
45
46static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
47static void _GBPocketCamCapture(struct GBMemory*);
48
49void GBMBCSwitchBank(struct GB* gb, int bank) {
50 size_t bankStart = bank * GB_SIZE_CART_BANK0;
51 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
52 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
53 bankStart &= (gb->memory.romSize - 1);
54 bank = bankStart / GB_SIZE_CART_BANK0;
55 }
56 gb->memory.romBank = &gb->memory.rom[bankStart];
57 gb->memory.currentBank = bank;
58 if (gb->cpu->pc < GB_BASE_VRAM) {
59 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
60 }
61}
62
63void GBMBCSwitchBank0(struct GB* gb, int bank) {
64 size_t bankStart = bank * GB_SIZE_CART_BANK0;
65 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
66 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
67 bankStart &= (gb->memory.romSize - 1);
68 }
69 gb->memory.romBase = &gb->memory.rom[bankStart];
70 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
71 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
72 }
73}
74
75void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
76 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
77 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
78 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
79 bankStart &= (gb->memory.romSize - 1);
80 bank = bankStart / GB_SIZE_CART_HALFBANK;
81 if (!bank) {
82 ++bank;
83 }
84 }
85 if (!half) {
86 gb->memory.romBank = &gb->memory.rom[bankStart];
87 gb->memory.currentBank = bank;
88 } else {
89 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
90 gb->memory.mbcState.mbc6.currentBank1 = bank;
91 }
92 if (gb->cpu->pc < GB_BASE_VRAM) {
93 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
94 }
95}
96
97static bool _isMulticart(const uint8_t* mem) {
98 bool success;
99 struct VFile* vf;
100
101 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
102 success = GBIsROM(vf);
103 vf->close(vf);
104
105 if (!success) {
106 return false;
107 }
108
109 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
110 success = GBIsROM(vf);
111 vf->close(vf);
112
113 if (!success) {
114 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
115 success = GBIsROM(vf);
116 vf->close(vf);
117 }
118
119 return success;
120}
121
122void GBMBCSwitchSramBank(struct GB* gb, int bank) {
123 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
124 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
125 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
126 bankStart &= (gb->sramSize - 1);
127 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
128 }
129 gb->memory.sramBank = &gb->memory.sram[bankStart];
130 gb->memory.sramCurrentBank = bank;
131}
132
133void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
134 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
135 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
136 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
137 bankStart &= (gb->sramSize - 1);
138 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
139 }
140 if (!half) {
141 gb->memory.sramBank = &gb->memory.sram[bankStart];
142 gb->memory.sramCurrentBank = bank;
143 } else {
144 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
145 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
146 }
147}
148
149void GBMBCInit(struct GB* gb) {
150 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
151 if (gb->memory.rom) {
152 if (gb->memory.romSize >= 0x8000) {
153 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
154 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
155 cart = cartFooter;
156 }
157 }
158 switch (cart->ramSize) {
159 case 0:
160 gb->sramSize = 0;
161 break;
162 case 1:
163 gb->sramSize = 0x800;
164 break;
165 default:
166 case 2:
167 gb->sramSize = 0x2000;
168 break;
169 case 3:
170 gb->sramSize = 0x8000;
171 break;
172 case 4:
173 gb->sramSize = 0x20000;
174 break;
175 case 5:
176 gb->sramSize = 0x10000;
177 break;
178 }
179
180 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
181 switch (cart->type) {
182 case 0:
183 case 8:
184 case 9:
185 gb->memory.mbcType = GB_MBC_NONE;
186 break;
187 case 1:
188 case 2:
189 case 3:
190 gb->memory.mbcType = GB_MBC1;
191 break;
192 case 5:
193 case 6:
194 gb->memory.mbcType = GB_MBC2;
195 break;
196 case 0x0B:
197 case 0x0C:
198 case 0x0D:
199 gb->memory.mbcType = GB_MMM01;
200 break;
201 case 0x0F:
202 case 0x10:
203 gb->memory.mbcType = GB_MBC3_RTC;
204 break;
205 case 0x11:
206 case 0x12:
207 case 0x13:
208 gb->memory.mbcType = GB_MBC3;
209 break;
210 default:
211 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
212 // Fall through
213 case 0x19:
214 case 0x1A:
215 case 0x1B:
216 gb->memory.mbcType = GB_MBC5;
217 break;
218 case 0x1C:
219 case 0x1D:
220 case 0x1E:
221 gb->memory.mbcType = GB_MBC5_RUMBLE;
222 break;
223 case 0x20:
224 gb->memory.mbcType = GB_MBC6;
225 break;
226 case 0x22:
227 gb->memory.mbcType = GB_MBC7;
228 break;
229 case 0xFC:
230 gb->memory.mbcType = GB_POCKETCAM;
231 break;
232 case 0xFD:
233 gb->memory.mbcType = GB_TAMA5;
234 break;
235 case 0xFE:
236 gb->memory.mbcType = GB_HuC3;
237 break;
238 case 0xFF:
239 gb->memory.mbcType = GB_HuC1;
240 break;
241 }
242 }
243 } else {
244 gb->memory.mbcType = GB_MBC_NONE;
245 }
246 gb->memory.mbcRead = NULL;
247 switch (gb->memory.mbcType) {
248 case GB_MBC_NONE:
249 gb->memory.mbcWrite = _GBMBCNone;
250 break;
251 case GB_MBC1:
252 gb->memory.mbcWrite = _GBMBC1;
253 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
254 gb->memory.mbcState.mbc1.multicartStride = 4;
255 } else {
256 gb->memory.mbcState.mbc1.multicartStride = 5;
257 }
258 break;
259 case GB_MBC2:
260 gb->memory.mbcWrite = _GBMBC2;
261 gb->memory.mbcRead = _GBMBC2Read;
262 gb->sramSize = 0x100;
263 break;
264 case GB_MBC3:
265 gb->memory.mbcWrite = _GBMBC3;
266 break;
267 default:
268 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
269 // Fall through
270 case GB_MBC5:
271 gb->memory.mbcWrite = _GBMBC5;
272 break;
273 case GB_MBC6:
274 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
275 gb->memory.mbcWrite = _GBMBC6;
276 gb->memory.mbcRead = _GBMBC6Read;
277 break;
278 case GB_MBC7:
279 gb->memory.mbcWrite = _GBMBC7;
280 gb->memory.mbcRead = _GBMBC7Read;
281 gb->sramSize = 0x100;
282 break;
283 case GB_MMM01:
284 gb->memory.mbcWrite = _GBMMM01;
285 break;
286 case GB_HuC1:
287 gb->memory.mbcWrite = _GBHuC1;
288 break;
289 case GB_HuC3:
290 gb->memory.mbcWrite = _GBHuC3;
291 break;
292 case GB_TAMA5:
293 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
294 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
295 gb->memory.mbcWrite = _GBTAMA5;
296 gb->memory.mbcRead = _GBTAMA5Read;
297 gb->sramSize = 0x20;
298 break;
299 case GB_MBC3_RTC:
300 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
301 gb->memory.mbcWrite = _GBMBC3;
302 break;
303 case GB_MBC5_RUMBLE:
304 gb->memory.mbcWrite = _GBMBC5;
305 break;
306 case GB_POCKETCAM:
307 gb->memory.mbcWrite = _GBPocketCam;
308 gb->memory.mbcRead = _GBPocketCamRead;
309 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
310 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
311 }
312 break;
313 }
314
315 gb->memory.currentBank = 1;
316 gb->memory.sramCurrentBank = 0;
317 gb->memory.sramAccess = false;
318 gb->memory.rtcAccess = false;
319 gb->memory.activeRtcReg = 0;
320 gb->memory.rtcLatched = false;
321 gb->memory.rtcLastLatch = 0;
322 if (gb->memory.rtc) {
323 if (gb->memory.rtc->sample) {
324 gb->memory.rtc->sample(gb->memory.rtc);
325 }
326 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
327 } else {
328 gb->memory.rtcLastLatch = time(0);
329 }
330 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
331
332 GBResizeSram(gb, gb->sramSize);
333
334 if (gb->memory.mbcType == GB_MBC3_RTC) {
335 GBMBCRTCRead(gb);
336 }
337}
338
339static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
340 time_t t;
341 if (rtc) {
342 if (rtc->sample) {
343 rtc->sample(rtc);
344 }
345 t = rtc->unixTime(rtc);
346 } else {
347 t = time(0);
348 }
349 time_t currentLatch = t;
350 t -= *rtcLastLatch;
351 *rtcLastLatch = currentLatch;
352
353 int64_t diff;
354 diff = rtcRegs[0] + t % 60;
355 if (diff < 0) {
356 diff += 60;
357 t -= 60;
358 }
359 rtcRegs[0] = diff % 60;
360 t /= 60;
361 t += diff / 60;
362
363 diff = rtcRegs[1] + t % 60;
364 if (diff < 0) {
365 diff += 60;
366 t -= 60;
367 }
368 rtcRegs[1] = diff % 60;
369 t /= 60;
370 t += diff / 60;
371
372 diff = rtcRegs[2] + t % 24;
373 if (diff < 0) {
374 diff += 24;
375 t -= 24;
376 }
377 rtcRegs[2] = diff % 24;
378 t /= 24;
379 t += diff / 24;
380
381 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
382 rtcRegs[3] = diff;
383 rtcRegs[4] &= 0xFE;
384 rtcRegs[4] |= (diff >> 8) & 1;
385 if (diff & 0x200) {
386 rtcRegs[4] |= 0x80;
387 }
388}
389
390void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
391 struct GBMemory* memory = &gb->memory;
392 int bank = value & 0x1F;
393 int stride = 1 << memory->mbcState.mbc1.multicartStride;
394 switch (address >> 13) {
395 case 0x0:
396 switch (value) {
397 case 0:
398 memory->sramAccess = false;
399 break;
400 case 0xA:
401 memory->sramAccess = true;
402 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
403 break;
404 default:
405 // TODO
406 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
407 break;
408 }
409 break;
410 case 0x1:
411 if (!bank) {
412 ++bank;
413 }
414 bank &= stride - 1;
415 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
416 break;
417 case 0x2:
418 bank &= 3;
419 if (memory->mbcState.mbc1.mode) {
420 GBMBCSwitchBank0(gb, bank << gb->memory.mbcState.mbc1.multicartStride);
421 GBMBCSwitchSramBank(gb, bank);
422 }
423 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
424 break;
425 case 0x3:
426 memory->mbcState.mbc1.mode = value & 1;
427 if (memory->mbcState.mbc1.mode) {
428 GBMBCSwitchBank0(gb, memory->currentBank & ~((1 << memory->mbcState.mbc1.multicartStride) - 1));
429 } else {
430 GBMBCSwitchBank0(gb, 0);
431 GBMBCSwitchSramBank(gb, 0);
432 }
433 break;
434 default:
435 // TODO
436 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
437 break;
438 }
439}
440
441void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
442 struct GBMemory* memory = &gb->memory;
443 int shift = (address & 1) * 4;
444 int bank = value & 0xF;
445 switch (address >> 13) {
446 case 0x0:
447 switch (value) {
448 case 0:
449 memory->sramAccess = false;
450 break;
451 case 0xA:
452 memory->sramAccess = true;
453 break;
454 default:
455 // TODO
456 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
457 break;
458 }
459 break;
460 case 0x1:
461 if (!bank) {
462 ++bank;
463 }
464 GBMBCSwitchBank(gb, bank);
465 break;
466 case 0x5:
467 if (!memory->sramAccess) {
468 return;
469 }
470 address &= 0x1FF;
471 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
472 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
473 break;
474 default:
475 // TODO
476 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
477 break;
478 }
479}
480
481static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
482 address &= 0x1FF;
483 int shift = (address & 1) * 4;
484 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
485}
486
487void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
488 struct GBMemory* memory = &gb->memory;
489 int bank = value & 0x7F;
490 switch (address >> 13) {
491 case 0x0:
492 switch (value) {
493 case 0:
494 memory->sramAccess = false;
495 break;
496 case 0xA:
497 memory->sramAccess = true;
498 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
499 break;
500 default:
501 // TODO
502 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
503 break;
504 }
505 break;
506 case 0x1:
507 if (!bank) {
508 ++bank;
509 }
510 GBMBCSwitchBank(gb, bank);
511 break;
512 case 0x2:
513 if (value < 4) {
514 GBMBCSwitchSramBank(gb, value);
515 memory->rtcAccess = false;
516 } else if (value >= 8 && value <= 0xC) {
517 memory->activeRtcReg = value - 8;
518 memory->rtcAccess = true;
519 }
520 break;
521 case 0x3:
522 if (memory->rtcLatched && value == 0) {
523 memory->rtcLatched = false;
524 } else if (!memory->rtcLatched && value == 1) {
525 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
526 memory->rtcLatched = true;
527 }
528 break;
529 }
530}
531
532void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
533 struct GBMemory* memory = &gb->memory;
534 int bank;
535 switch (address >> 12) {
536 case 0x0:
537 case 0x1:
538 switch (value) {
539 case 0:
540 memory->sramAccess = false;
541 break;
542 case 0xA:
543 memory->sramAccess = true;
544 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
545 break;
546 default:
547 // TODO
548 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
549 break;
550 }
551 break;
552 case 0x2:
553 bank = (memory->currentBank & 0x100) | value;
554 GBMBCSwitchBank(gb, bank);
555 break;
556 case 0x3:
557 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
558 GBMBCSwitchBank(gb, bank);
559 break;
560 case 0x4:
561 case 0x5:
562 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
563 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
564 value &= ~8;
565 }
566 GBMBCSwitchSramBank(gb, value & 0xF);
567 break;
568 default:
569 // TODO
570 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
571 break;
572 }
573}
574
575void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
576 struct GBMemory* memory = &gb->memory;
577 int bank = value;
578 switch (address >> 10) {
579 case 0:
580 switch (value) {
581 case 0:
582 memory->mbcState.mbc6.sramAccess = false;
583 break;
584 case 0xA:
585 memory->mbcState.mbc6.sramAccess = true;
586 break;
587 default:
588 // TODO
589 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
590 break;
591 }
592 break;
593 case 0x1:
594 GBMBCSwitchSramHalfBank(gb, 0, bank);
595 break;
596 case 0x2:
597 GBMBCSwitchSramHalfBank(gb, 1, bank);
598 break;
599 case 0x8:
600 case 0x9:
601 GBMBCSwitchHalfBank(gb, 0, bank);
602 break;
603 case 0xC:
604 case 0xD:
605 GBMBCSwitchHalfBank(gb, 1, bank);
606 break;
607 case 0x28:
608 case 0x29:
609 case 0x2A:
610 case 0x2B:
611 if (memory->mbcState.mbc6.sramAccess) {
612 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
613 }
614 break;
615 case 0x2C:
616 case 0x2D:
617 case 0x2E:
618 case 0x2F:
619 if (memory->mbcState.mbc6.sramAccess) {
620 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
621 }
622 break;
623 default:
624 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
625 break;
626 }
627}
628
629uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
630 if (!memory->mbcState.mbc6.sramAccess) {
631 return 0xFF;
632 }
633 switch (address >> 12) {
634 case 0xA:
635 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
636 case 0xB:
637 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
638 }
639 return 0xFF;
640}
641
642void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
643 int bank = value & 0x7F;
644 switch (address >> 13) {
645 case 0x0:
646 switch (value) {
647 default:
648 case 0:
649 gb->memory.mbcState.mbc7.access = 0;
650 break;
651 case 0xA:
652 gb->memory.mbcState.mbc7.access |= 1;
653 break;
654 }
655 break;
656 case 0x1:
657 GBMBCSwitchBank(gb, bank);
658 break;
659 case 0x2:
660 if (value == 0x40) {
661 gb->memory.mbcState.mbc7.access |= 2;
662 } else {
663 gb->memory.mbcState.mbc7.access &= ~2;
664 }
665 break;
666 case 0x5:
667 _GBMBC7Write(&gb->memory, address, value);
668 break;
669 default:
670 // TODO
671 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
672 break;
673 }
674}
675
676uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
677 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
678 if (mbc7->access != 3) {
679 return 0xFF;
680 }
681 switch (address & 0xF0) {
682 case 0x20:
683 if (memory->rotation && memory->rotation->readTiltX) {
684 int32_t x = -memory->rotation->readTiltX(memory->rotation);
685 x >>= 21;
686 x += 0x81D0;
687 return x;
688 }
689 return 0xFF;
690 case 0x30:
691 if (memory->rotation && memory->rotation->readTiltX) {
692 int32_t x = -memory->rotation->readTiltX(memory->rotation);
693 x >>= 21;
694 x += 0x81D0;
695 return x >> 8;
696 }
697 return 7;
698 case 0x40:
699 if (memory->rotation && memory->rotation->readTiltY) {
700 int32_t y = -memory->rotation->readTiltY(memory->rotation);
701 y >>= 21;
702 y += 0x81D0;
703 return y;
704 }
705 return 0xFF;
706 case 0x50:
707 if (memory->rotation && memory->rotation->readTiltY) {
708 int32_t y = -memory->rotation->readTiltY(memory->rotation);
709 y >>= 21;
710 y += 0x81D0;
711 return y >> 8;
712 }
713 return 7;
714 case 0x60:
715 return 0;
716 case 0x80:
717 return mbc7->eeprom;
718 default:
719 return 0xFF;
720 }
721}
722
723static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
724 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
725 if (mbc7->access != 3) {
726 return;
727 }
728 switch (address & 0xF0) {
729 case 0x00:
730 mbc7->latch = (value & 0x55) == 0x55;
731 return;
732 case 0x10:
733 mbc7->latch |= (value & 0xAA);
734 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
735 memory->rotation->sample(memory->rotation);
736 }
737 mbc7->latch = 0;
738 return;
739 default:
740 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
741 return;
742 case 0x80:
743 break;
744 }
745 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
746 value = GBMBC7FieldFillDO(value); // Hi-Z
747 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
748 mbc7->state = GBMBC7_STATE_IDLE;
749 }
750 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
751 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
752 mbc7->sr <<= 1;
753 mbc7->sr |= GBMBC7FieldGetDI(value);
754 ++mbc7->srBits;
755 }
756 switch (mbc7->state) {
757 case GBMBC7_STATE_IDLE:
758 if (GBMBC7FieldIsDI(value)) {
759 mbc7->state = GBMBC7_STATE_READ_COMMAND;
760 mbc7->srBits = 0;
761 mbc7->sr = 0;
762 }
763 break;
764 case GBMBC7_STATE_READ_COMMAND:
765 if (mbc7->srBits == 10) {
766 mbc7->state = 0x10 | (mbc7->sr >> 6);
767 if (mbc7->state & 0xC) {
768 mbc7->state &= ~0x3;
769 }
770 mbc7->srBits = 0;
771 mbc7->address = mbc7->sr & 0x7F;
772 }
773 break;
774 case GBMBC7_STATE_DO:
775 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
776 mbc7->sr <<= 1;
777 --mbc7->srBits;
778 if (!mbc7->srBits) {
779 mbc7->state = GBMBC7_STATE_IDLE;
780 }
781 break;
782 default:
783 break;
784 }
785 switch (mbc7->state) {
786 case GBMBC7_STATE_EEPROM_EWEN:
787 mbc7->writable = true;
788 mbc7->state = GBMBC7_STATE_IDLE;
789 break;
790 case GBMBC7_STATE_EEPROM_EWDS:
791 mbc7->writable = false;
792 mbc7->state = GBMBC7_STATE_IDLE;
793 break;
794 case GBMBC7_STATE_EEPROM_WRITE:
795 if (mbc7->srBits == 16) {
796 if (mbc7->writable) {
797 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
798 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
799 }
800 mbc7->state = GBMBC7_STATE_IDLE;
801 }
802 break;
803 case GBMBC7_STATE_EEPROM_ERASE:
804 if (mbc7->writable) {
805 memory->sram[mbc7->address * 2] = 0xFF;
806 memory->sram[mbc7->address * 2 + 1] = 0xFF;
807 }
808 mbc7->state = GBMBC7_STATE_IDLE;
809 break;
810 case GBMBC7_STATE_EEPROM_READ:
811 mbc7->srBits = 16;
812 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
813 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
814 mbc7->state = GBMBC7_STATE_DO;
815 value = GBMBC7FieldClearDO(value);
816 break;
817 case GBMBC7_STATE_EEPROM_WRAL:
818 if (mbc7->srBits == 16) {
819 if (mbc7->writable) {
820 int i;
821 for (i = 0; i < 128; ++i) {
822 memory->sram[i * 2] = mbc7->sr >> 8;
823 memory->sram[i * 2 + 1] = mbc7->sr;
824 }
825 }
826 mbc7->state = GBMBC7_STATE_IDLE;
827 }
828 break;
829 case GBMBC7_STATE_EEPROM_ERAL:
830 if (mbc7->writable) {
831 int i;
832 for (i = 0; i < 128; ++i) {
833 memory->sram[i * 2] = 0xFF;
834 memory->sram[i * 2 + 1] = 0xFF;
835 }
836 }
837 mbc7->state = GBMBC7_STATE_IDLE;
838 break;
839 default:
840 break;
841 }
842 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
843 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
844 }
845 mbc7->eeprom = value;
846}
847
848void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
849 struct GBMemory* memory = &gb->memory;
850 if (!memory->mbcState.mmm01.locked) {
851 switch (address >> 13) {
852 case 0x0:
853 memory->mbcState.mmm01.locked = true;
854 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
855 break;
856 case 0x1:
857 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
858 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
859 break;
860 case 0x2:
861 memory->mbcState.mmm01.currentBank0 &= ~0x180;
862 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
863 break;
864 default:
865 // TODO
866 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
867 break;
868 }
869 return;
870 }
871 switch (address >> 13) {
872 case 0x0:
873 switch (value) {
874 case 0xA:
875 memory->sramAccess = true;
876 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
877 break;
878 default:
879 memory->sramAccess = false;
880 break;
881 }
882 break;
883 case 0x1:
884 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
885 break;
886 case 0x2:
887 GBMBCSwitchSramBank(gb, value);
888 break;
889 default:
890 // TODO
891 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
892 break;
893 }
894}
895
896void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
897 struct GBMemory* memory = &gb->memory;
898 int bank = value & 0x3F;
899 switch (address >> 13) {
900 case 0x0:
901 switch (value) {
902 case 0xE:
903 memory->sramAccess = false;
904 break;
905 default:
906 memory->sramAccess = true;
907 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
908 break;
909 }
910 break;
911 case 0x1:
912 GBMBCSwitchBank(gb, bank);
913 break;
914 case 0x2:
915 GBMBCSwitchSramBank(gb, value);
916 break;
917 default:
918 // TODO
919 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
920 break;
921 }
922}
923
924void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
925 struct GBMemory* memory = &gb->memory;
926 int bank = value & 0x3F;
927 if (address & 0x1FFF) {
928 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
929 }
930
931 switch (address >> 13) {
932 case 0x0:
933 switch (value) {
934 case 0xA:
935 memory->sramAccess = true;
936 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
937 break;
938 default:
939 memory->sramAccess = false;
940 break;
941 }
942 break;
943 case 0x1:
944 GBMBCSwitchBank(gb, bank);
945 break;
946 case 0x2:
947 GBMBCSwitchSramBank(gb, bank);
948 break;
949 default:
950 // TODO
951 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
952 break;
953 }
954}
955
956void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
957 struct GBMemory* memory = &gb->memory;
958 int bank = value & 0x3F;
959 switch (address >> 13) {
960 case 0x0:
961 switch (value) {
962 case 0:
963 memory->sramAccess = false;
964 break;
965 case 0xA:
966 memory->sramAccess = true;
967 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
968 break;
969 default:
970 // TODO
971 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
972 break;
973 }
974 break;
975 case 0x1:
976 GBMBCSwitchBank(gb, bank);
977 break;
978 case 0x2:
979 if (value < 0x10) {
980 GBMBCSwitchSramBank(gb, value);
981 memory->mbcState.pocketCam.registersActive = false;
982 } else {
983 memory->mbcState.pocketCam.registersActive = true;
984 }
985 break;
986 case 0x5:
987 address &= 0x7F;
988 if (address == 0 && value & 1) {
989 value &= 6; // TODO: Timing
990 _GBPocketCamCapture(memory);
991 }
992 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
993 memory->mbcState.pocketCam.registers[address] = value;
994 }
995 break;
996 default:
997 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
998 break;
999 }
1000}
1001
1002uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1003 if (memory->mbcState.pocketCam.registersActive) {
1004 if ((address & 0x7F) == 0) {
1005 return memory->mbcState.pocketCam.registers[0];
1006 }
1007 return 0;
1008 }
1009 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1010}
1011
1012void _GBPocketCamCapture(struct GBMemory* memory) {
1013 if (!memory->cam) {
1014 return;
1015 }
1016 const void* image = NULL;
1017 size_t stride;
1018 enum mColorFormat format;
1019 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1020 if (!image) {
1021 return;
1022 }
1023 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1024 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1025 size_t x, y;
1026 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1027 for (x = 0; x < GBCAM_WIDTH; ++x) {
1028 uint32_t gray;
1029 uint32_t color;
1030 switch (format) {
1031 case mCOLOR_XBGR8:
1032 case mCOLOR_XRGB8:
1033 case mCOLOR_ARGB8:
1034 case mCOLOR_ABGR8:
1035 color = ((const uint32_t*) image)[y * stride + x];
1036 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1037 break;
1038 case mCOLOR_BGRX8:
1039 case mCOLOR_RGBX8:
1040 case mCOLOR_RGBA8:
1041 case mCOLOR_BGRA8:
1042 color = ((const uint32_t*) image)[y * stride + x];
1043 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1044 break;
1045 case mCOLOR_BGR5:
1046 case mCOLOR_RGB5:
1047 case mCOLOR_ARGB5:
1048 case mCOLOR_ABGR5:
1049 color = ((const uint16_t*) image)[y * stride + x];
1050 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1051 break;
1052 case mCOLOR_BGR565:
1053 case mCOLOR_RGB565:
1054 color = ((const uint16_t*) image)[y * stride + x];
1055 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1056 break;
1057 case mCOLOR_BGRA5:
1058 case mCOLOR_RGBA5:
1059 color = ((const uint16_t*) image)[y * stride + x];
1060 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1061 break;
1062 default:
1063 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1064 return;
1065 }
1066 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1067 gray = (gray + 1) * exposure / 0x300;
1068 // TODO: Additional processing
1069 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1070 if (gray < pocketCam->registers[matrixEntry + 6]) {
1071 gray = 0x101;
1072 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1073 gray = 0x100;
1074 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1075 gray = 0x001;
1076 } else {
1077 gray = 0;
1078 }
1079 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1080 uint16_t existing;
1081 LOAD_16LE(existing, coord + 0x100, memory->sram);
1082 existing |= gray << (7 - (x & 7));
1083 STORE_16LE(existing, coord + 0x100, memory->sram);
1084 }
1085 }
1086}
1087
1088void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1089 struct GBMemory* memory = &gb->memory;
1090 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1091 switch (address >> 13) {
1092 case 0x5:
1093 if (address & 1) {
1094 tama5->reg = value;
1095 } else {
1096 value &= 0xF;
1097 if (tama5->reg < GBTAMA5_MAX) {
1098 tama5->registers[tama5->reg] = value;
1099 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1100 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1101 switch (tama5->reg) {
1102 case GBTAMA5_BANK_LO:
1103 case GBTAMA5_BANK_HI:
1104 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1105 break;
1106 case GBTAMA5_WRITE_LO:
1107 case GBTAMA5_WRITE_HI:
1108 case GBTAMA5_CS:
1109 break;
1110 case GBTAMA5_ADDR_LO:
1111 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1112 case 0x0: // RAM write
1113 memory->sram[address] = out;
1114 break;
1115 case 0x1: // RAM read
1116 break;
1117 default:
1118 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1119 }
1120 break;
1121 default:
1122 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1123 break;
1124 }
1125 } else {
1126 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1127 }
1128 }
1129 break;
1130 default:
1131 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1132 }
1133}
1134
1135uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1136 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1137 if ((address & 0x1FFF) > 1) {
1138 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1139 }
1140 if (address & 1) {
1141 return 0xFF;
1142 } else {
1143 uint8_t value = 0xF0;
1144 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1145 switch (tama5->reg) {
1146 case GBTAMA5_ACTIVE:
1147 return 0xF1;
1148 case GBTAMA5_READ_LO:
1149 case GBTAMA5_READ_HI:
1150 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1151 case 1:
1152 value = memory->sram[address];
1153 break;
1154 default:
1155 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1156 break;
1157 }
1158 if (tama5->reg == GBTAMA5_READ_HI) {
1159 value >>= 4;
1160 }
1161 value |= 0xF0;
1162 return value;
1163 default:
1164 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1165 return 0xF1;
1166 }
1167 }
1168}
1169
1170void GBMBCRTCRead(struct GB* gb) {
1171 struct GBMBCRTCSaveBuffer rtcBuffer;
1172 struct VFile* vf = gb->sramVf;
1173 if (!vf) {
1174 return;
1175 }
1176 vf->seek(vf, gb->sramSize, SEEK_SET);
1177 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1178 return;
1179 }
1180
1181 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1182 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1183 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1184 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1185 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1186 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1187}
1188
1189void GBMBCRTCWrite(struct GB* gb) {
1190 struct VFile* vf = gb->sramVf;
1191 if (!vf) {
1192 return;
1193 }
1194
1195 uint8_t rtcRegs[5];
1196 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1197 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1198 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1199
1200 struct GBMBCRTCSaveBuffer rtcBuffer;
1201 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1202 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1203 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1204 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1205 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1206 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1207 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1208 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1209 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1210 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1211 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1212
1213 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1214 // Writing past the end of the file can invalidate the file mapping
1215 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1216 gb->memory.sram = NULL;
1217 }
1218 vf->seek(vf, gb->sramSize, SEEK_SET);
1219 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1220 if (!gb->memory.sram) {
1221 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1222 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1223 }
1224}