src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77 ds->earlyExit = true;
78}
79
80static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
81 UNUSED(timing);
82 UNUSED(cyclesLate);
83 struct DS* ds = context;
84 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
85 int64_t numerator;
86 int64_t denominator;
87 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
88 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
89 bool max = false;
90 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
91 case 0:
92 denominator &= 0xFFFFFFFFLL;
93 case 1:
94 case 3:
95 numerator &= 0xFFFFFFFFLL;
96 if (numerator == INT32_MIN) {
97 max = true;
98 }
99 break;
100 }
101 if (numerator == INT64_MIN) {
102 max = true;
103 }
104 if (!denominator) {
105 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
106 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
107 numerator >>= 63LL;
108 numerator = -numerator;
109 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
110 return;
111 }
112 if (denominator == -1LL && max) {
113 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
114 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
115 return;
116 }
117 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
118 int64_t result = numerator / denominator;
119 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
120 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
121 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
122}
123
124 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
125 UNUSED(timing);
126 UNUSED(cyclesLate);
127 struct DS* ds = context;
128 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
129 uint64_t param;
130 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
131 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
132 param &= 0xFFFFFFFFULL;
133 }
134
135 uint64_t result = 0;
136 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
137
138 // "bit" starts at the highest power of four <= the argument.
139 while (bit > param) {
140 bit >>= 2;
141 }
142
143 while (bit != 0) {
144 if (param >= param + bit) {
145 param -= param + bit;
146 param = (result >> 1) + bit;
147 } else {
148 param >>= 1;
149 }
150 bit >>= 2;
151 }
152 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
153}
154
155void DSCreate(struct DS* ds) {
156 ds->d.id = DS_COMPONENT_MAGIC;
157 ds->d.init = DSInit;
158 ds->d.deinit = NULL;
159 ds->ds7.p = ds;
160 ds->ds9.p = ds;
161 ds->ds7.cpu = NULL;
162 ds->ds9.cpu = NULL;
163 ds->ds7.ipc = &ds->ds9;
164 ds->ds9.ipc = &ds->ds7;
165}
166
167static void DSInit(void* cpu, struct mCPUComponent* component) {
168 struct DS* ds = (struct DS*) component;
169 struct ARMCore* core = cpu;
170 if (!ds->ds7.cpu) {
171 // The ARM7 must get initialized first
172 ds->ds7.cpu = core;
173 ds->debugger = 0;
174 ds->sync = 0;
175 return;
176 }
177 ds->ds9.cpu = cpu;
178 ds->activeCpu = NULL;
179
180 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
181
182 ds->slice.name = "DS CPU Time Slicing";
183 ds->slice.callback = _slice;
184 ds->slice.context = ds;
185 ds->slice.priority = UINT_MAX;
186
187 CircleBufferInit(&ds->ds7.fifo, 64);
188 CircleBufferInit(&ds->ds9.fifo, 64);
189
190 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
191 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
192 DSMemoryInit(ds);
193 DSDMAInit(ds);
194
195 DSVideoInit(&ds->video);
196 ds->video.p = ds;
197
198 ds->ds7.springIRQ = 0;
199 ds->ds9.springIRQ = 0;
200 DSTimerInit(ds);
201 ds->keySource = NULL;
202 ds->rtcSource = NULL;
203 ds->rumble = NULL;
204
205 ds->romVf = NULL;
206
207 ds->keyCallback = NULL;
208
209 ds->divEvent.name = "DS Hardware Divide";
210 ds->divEvent.callback = _divide;
211 ds->divEvent.context = ds;
212 ds->divEvent.priority = 0x50;
213
214 ds->sqrtEvent.name = "DS Hardware Sqrt";
215 ds->sqrtEvent.callback = _sqrt;
216 ds->sqrtEvent.context = ds;
217 ds->sqrtEvent.priority = 0x51;
218
219 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
220 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
221}
222
223void DSUnloadROM(struct DS* ds) {
224 if (ds->romVf) {
225 ds->romVf->close(ds->romVf);
226 ds->romVf = NULL;
227 }
228}
229
230void DSDestroy(struct DS* ds) {
231 CircleBufferDeinit(&ds->ds7.fifo);
232 CircleBufferDeinit(&ds->ds9.fifo);
233 DSUnloadROM(ds);
234 DSMemoryDeinit(ds);
235 mTimingDeinit(&ds->ds7.timing);
236 mTimingDeinit(&ds->ds9.timing);
237}
238
239void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
240 irqh->reset = DS7Reset;
241 irqh->processEvents = DS7ProcessEvents;
242 irqh->swi16 = DS7Swi16;
243 irqh->swi32 = DS7Swi32;
244 irqh->hitIllegal = DSIllegal;
245 irqh->readCPSR = DS7TestIRQ;
246 irqh->writeCP15 = NULL;
247 irqh->readCP15 = NULL;
248 irqh->hitStub = DSHitStub;
249 irqh->bkpt16 = DSBreakpoint;
250 irqh->bkpt32 = DSBreakpoint;
251}
252
253void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
254 irqh->reset = DS9Reset;
255 irqh->processEvents = DS9ProcessEvents;
256 irqh->swi16 = DS9Swi16;
257 irqh->swi32 = DS9Swi32;
258 irqh->hitIllegal = DSIllegal;
259 irqh->readCPSR = DS9TestIRQ;
260 irqh->writeCP15 = DS9WriteCP15;
261 irqh->readCP15 = DS9ReadCP15;
262 irqh->hitStub = DSHitStub;
263 irqh->bkpt16 = DSBreakpoint;
264 irqh->bkpt32 = DSBreakpoint;
265}
266
267void DS7Reset(struct ARMCore* cpu) {
268 ARMSetPrivilegeMode(cpu, MODE_IRQ);
269 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
270 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
271 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
272 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
273 cpu->gprs[ARM_SP] = DS7_SP_BASE;
274
275 struct DS* ds = (struct DS*) cpu->master;
276 mTimingClear(&ds->ds7.timing);
277 CircleBufferInit(&ds->ds7.fifo, 64);
278 DSMemoryReset(ds);
279 DSDMAReset(&ds->ds7);
280 DS7IOInit(ds);
281
282 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
283 if (header) {
284 // TODO: Error check
285 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
286 uint32_t base = header->arm7Base - DS_BASE_RAM;
287 uint32_t* basePointer = &ds->memory.ram[base >> 2];
288 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
289 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
290 }
291 cpu->gprs[12] = header->arm7Entry;
292 cpu->gprs[ARM_LR] = header->arm7Entry;
293 cpu->gprs[ARM_PC] = header->arm7Entry;
294 int currentCycles = 0;
295 ARM_WRITE_PC;
296
297 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
298 }
299}
300
301void DS9Reset(struct ARMCore* cpu) {
302 ARMSetPrivilegeMode(cpu, MODE_IRQ);
303 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
304 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
305 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
306 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
307 cpu->gprs[ARM_SP] = DS9_SP_BASE;
308
309 struct DS* ds = (struct DS*) cpu->master;
310 mTimingClear(&ds->ds9.timing);
311 CircleBufferInit(&ds->ds9.fifo, 64);
312 DSVideoReset(&ds->video);
313 DSDMAReset(&ds->ds9);
314 DS9IOInit(ds);
315
316 ds->activeCpu = cpu;
317 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
318 ds->cycleDrift = 0;
319 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
320
321 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
322 if (header) {
323 // TODO: Error check
324 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
325 uint32_t base = header->arm9Base - DS_BASE_RAM;
326 uint32_t* basePointer = &ds->memory.ram[base >> 2];
327 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
328 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
329 }
330 cpu->gprs[12] = header->arm9Entry;
331 cpu->gprs[ARM_LR] = header->arm9Entry;
332 cpu->gprs[ARM_PC] = header->arm9Entry;
333 int currentCycles = 0;
334 ARM_WRITE_PC;
335
336 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
337 }
338}
339
340static void DS7ProcessEvents(struct ARMCore* cpu) {
341 struct DS* ds = (struct DS*) cpu->master;
342 DSProcessEvents(&ds->ds7);
343}
344
345static void DS9ProcessEvents(struct ARMCore* cpu) {
346 struct DS* ds = (struct DS*) cpu->master;
347 DSProcessEvents(&ds->ds9);
348}
349
350static void DSProcessEvents(struct DSCommon* dscore) {
351 struct ARMCore* cpu = dscore->cpu;
352 struct DS* ds = dscore->p;
353 if (dscore->springIRQ && !cpu->cpsr.i) {
354 ARMRaiseIRQ(cpu);
355 dscore->springIRQ = 0;
356 }
357
358 int32_t nextEvent = cpu->nextEvent;
359 while (cpu->cycles >= nextEvent) {
360 int32_t cycles = cpu->cycles;
361
362 cpu->cycles = 0;
363 cpu->nextEvent = INT_MAX;
364
365#ifndef NDEBUG
366 if (cycles < 0) {
367 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
368 }
369#endif
370 nextEvent = cycles;
371 do {
372 nextEvent = mTimingTick(&dscore->timing, nextEvent);
373 } while (ds->cpuBlocked);
374
375 cpu->nextEvent = nextEvent;
376
377 if (ds->earlyExit) {
378 ds->earlyExit = false;
379 break;
380 }
381 if (cpu->halted) {
382 cpu->cycles = nextEvent;
383 }
384#ifndef NDEBUG
385 else if (nextEvent < 0) {
386 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
387 }
388#endif
389 }
390}
391
392void DSRunLoop(struct DS* ds) {
393 if (ds->activeCpu == ds->ds9.cpu) {
394 ARMv5RunLoop(ds->ds9.cpu);
395 } else {
396 ARMv4RunLoop(ds->ds7.cpu);
397 }
398}
399
400void DS7Step(struct DS* ds) {
401 while (ds->activeCpu == ds->ds9.cpu) {
402 ARMv5RunLoop(ds->ds9.cpu);
403 }
404 ARMv4Run(ds->ds7.cpu);
405}
406
407void DS9Step(struct DS* ds) {
408 while (ds->activeCpu == ds->ds7.cpu) {
409 ARMv4RunLoop(ds->ds7.cpu);
410 }
411 ARMv5Run(ds->ds9.cpu);
412}
413
414void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
415 ds->debugger = (struct ARMDebugger*) debugger->platform;
416 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
417 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
418 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
419 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
420}
421
422void DSDetachDebugger(struct DS* ds) {
423 ds->debugger = NULL;
424 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
425 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
426 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
427 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
428}
429
430bool DSLoadROM(struct DS* ds, struct VFile* vf) {
431 DSUnloadROM(ds);
432 ds->romVf = vf;
433 // TODO: error check
434 return true;
435}
436
437bool DSIsROM(struct VFile* vf) {
438 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
439 return false;
440 }
441 uint8_t signature[sizeof(DS_ROM_MAGIC)];
442 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
443 return false;
444 }
445 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
446}
447
448bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
449 size_t size = vf->size(vf);
450 void* data = NULL;
451 uint32_t crc;
452 if (size == DS7_SIZE_BIOS) {
453 data = vf->map(vf, size, MAP_READ);
454 } else if (size == 0x1000) {
455 data = calloc(DS9_SIZE_BIOS, 1);
456 vf->read(vf, data, size);
457 } else if (size == DS9_SIZE_BIOS) {
458 data = vf->map(vf, size, MAP_READ);
459 }
460 if (!data) {
461 return false;
462 }
463 crc = doCrc32(data, size);
464 if (crc == DS7_BIOS_CHECKSUM) {
465 ds->bios7Vf = vf;
466 ds->memory.bios7 = data;
467 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
468 } else if (crc == DS9_BIOS_CHECKSUM) {
469 ds->bios9Vf = vf;
470 ds->memory.bios9 = data;
471 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
472 } else {
473 mLOG(DS, WARN, "BIOS checksum incorrect");
474 vf->unmap(vf, data, size);
475 return false;
476 }
477 return true;
478}
479
480void DSGetGameCode(struct DS* ds, char* out) {
481 memset(out, 0, 8);
482 if (!ds->romVf) {
483 return;
484 }
485
486 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
487 memcpy(out, "NTR-", 4);
488 memcpy(&out[4], &cart->id, 4);
489 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
490}
491
492void DSGetGameTitle(struct DS* ds, char* out) {
493 memset(out, 0, 12);
494 if (!ds->romVf) {
495 return;
496 }
497
498 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
499 memcpy(out, &cart->title, 4);
500 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
501}
502
503void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
504 struct DS* ds = (struct DS*) cpu->master;
505 if (ds->debugger) {
506 struct mDebuggerEntryInfo info = {
507 .address = _ARMPCAddress(cpu),
508 .opcode = opcode
509 };
510 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
511 }
512 // TODO: More sensible category?
513 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
514}
515
516void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
517 struct DS* ds = (struct DS*) cpu->master;
518 if (ds->debugger) {
519 struct mDebuggerEntryInfo info = {
520 .address = _ARMPCAddress(cpu),
521 .opcode = opcode
522 };
523 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
524 } else {
525 ARMRaiseUndefined(cpu);
526 }
527}
528
529void DSBreakpoint(struct ARMCore* cpu, int immediate) {
530 struct DS* ds = (struct DS*) cpu->master;
531 if (immediate >= CPU_COMPONENT_MAX) {
532 return;
533 }
534 switch (immediate) {
535 case CPU_COMPONENT_DEBUGGER:
536 if (ds->debugger) {
537 struct mDebuggerEntryInfo info = {
538 .address = _ARMPCAddress(cpu)
539 };
540 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
541 }
542 break;
543 default:
544 break;
545 }
546}
547
548void DS7TestIRQ(struct ARMCore* cpu) {
549 struct DS* ds = (struct DS*) cpu->master;
550 if (0) {
551 ds->ds7.springIRQ = 1;
552 cpu->nextEvent = cpu->cycles;
553 }
554}
555
556void DS9TestIRQ(struct ARMCore* cpu) {
557 struct DS* ds = (struct DS*) cpu->master;
558 if (0) {
559 ds->ds9.springIRQ = 1;
560 cpu->nextEvent = cpu->cycles;
561 }
562}
563
564static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
565 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
566}
567
568static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
569 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
570 switch (opcode2) {
571 case 0:
572 cpu->cp15.r2.d = value;
573 break;
574 case 1:
575 cpu->cp15.r2.i = value;
576 break;
577 default:
578 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
579 break;
580 }
581}
582
583static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
584 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
585 switch (opcode2) {
586 case 0:
587 cpu->cp15.r3.d = value;
588 break;
589 default:
590 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
591 break;
592 }
593}
594
595static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
596 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
597}
598
599static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
600 cpu->cp15.r6.region[crm] = value;
601 uint32_t base = ARMProtectionGetBase(value) << 12;
602 uint32_t size = 2 << ARMProtectionGetSize(value);
603 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
604}
605
606static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
607 switch (crm) {
608 case 0:
609 if (opcode2 == 4) {
610 ARMHalt(cpu);
611 return;
612 }
613 break;
614 }
615 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
616}
617
618static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
619 uint32_t base = ARMTCMControlGetBase(value) << 12;
620 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
621 struct DS* ds = (struct DS*) cpu->master;
622 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
623 switch (opcode2) {
624 case 0:
625 cpu->cp15.r9.d = value;
626 ds->memory.dtcmBase = base;
627 ds->memory.dtcmSize = size;
628 break;
629 case 1:
630 cpu->cp15.r9.i = value;
631 ds->memory.itcmSize = size;
632 break;
633 default:
634 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
635 break;
636 }
637}
638
639void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
640 switch (crn) {
641 default:
642 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
643 break;
644 case 0:
645 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
646 ARMRaiseUndefined(cpu);
647 break;
648 case 1:
649 _writeSysControl(cpu, crm, opcode2, value);
650 break;
651 case 2:
652 _writeCacheControl(cpu, crm, opcode2, value);
653 break;
654 case 3:
655 _writeWriteBufferControl(cpu, crm, opcode2, value);
656 break;
657 case 5:
658 _writeAccessControl(cpu, crm, opcode2, value);
659 break;
660 case 6:
661 _writeRegionConfiguration(cpu, crm, opcode2, value);
662 break;
663 case 7:
664 _writeCache(cpu, crm, opcode2, value);
665 break;
666 case 9:
667 _writeTCMControl(cpu, crm, opcode2, value);
668 break;
669 }
670}
671
672static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
673 switch (opcode2) {
674 case 0:
675 return cpu->cp15.r9.d;
676 case 1:
677 return cpu->cp15.r9.i;
678 default:
679 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
680 return 0;
681 }
682}
683
684uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
685 switch (crn) {
686 default:
687 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
688 return 0;
689 case 9:
690 return _readTCMControl(cpu, crm, opcode2);
691 }
692}
693
694void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
695 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
696 ARMRaiseIRQ(cpu);
697 }
698}
699void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
700 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
701 ARMRaiseIRQ(cpu);
702 }
703}
704
705void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
706 if (irq < 16) {
707 io[DS_REG_IF_LO >> 1] |= 1 << irq;
708 } else {
709 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
710 }
711
712 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
713 cpu->halted = 0;
714 if (io[DS_REG_IME >> 1]) {
715 ARMRaiseIRQ(cpu);
716 }
717 }
718}
719
720void DSFrameStarted(struct DS* ds) {
721 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
722 if (callbacks && callbacks->videoFrameStarted) {
723 callbacks->videoFrameStarted(callbacks->context);
724 }
725}
726
727void DSFrameEnded(struct DS* ds) {
728 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
729 if (callbacks && callbacks->videoFrameEnded) {
730 callbacks->videoFrameEnded(callbacks->context);
731 }
732}