src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5// Instruction definitions
6// Beware pre-processor insanity
7
8#define THUMB_ADDITION_S(M, N, D) \
9 cpu->cpsr.n = ARM_SIGN(D); \
10 cpu->cpsr.z = !(D); \
11 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
12 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
13
14#define THUMB_SUBTRACTION_S(M, N, D) \
15 cpu->cpsr.n = ARM_SIGN(D); \
16 cpu->cpsr.z = !(D); \
17 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
18 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
19
20#define THUMB_NEUTRAL_S(M, N, D) \
21 cpu->cpsr.n = ARM_SIGN(D); \
22 cpu->cpsr.z = !(D);
23
24#define THUMB_ADDITION(D, M, N) \
25 int n = N; \
26 int m = M; \
27 D = M + N; \
28 THUMB_ADDITION_S(m, n, D)
29
30#define THUMB_SUBTRACTION(D, M, N) \
31 int n = N; \
32 int m = M; \
33 D = M - N; \
34 THUMB_SUBTRACTION_S(m, n, D)
35
36#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activePrefetchCycles16)
37
38#define THUMB_STORE_POST_BODY \
39 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activePrefetchCycles16;
40
41#define APPLY(F, ...) F(__VA_ARGS__)
42
43#define COUNT_1(EMITTER, PREFIX, ...) \
44 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
45 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
46
47#define COUNT_2(EMITTER, PREFIX, ...) \
48 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
50 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
51
52#define COUNT_3(EMITTER, PREFIX, ...) \
53 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
54 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
55 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
56 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
57 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
58
59#define COUNT_4(EMITTER, PREFIX, ...) \
60 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
61 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
62 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
63 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
64 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
65 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
66 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
67 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
68 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
69
70#define COUNT_5(EMITTER, PREFIX, ...) \
71 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
72 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
73 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
74 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
75 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
76 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
77 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
78 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
79 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
80 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
81 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
82 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
83 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
84 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
85 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
86 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
87 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
88
89#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
90 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
91 int currentCycles = THUMB_PREFETCH_CYCLES; \
92 BODY; \
93 cpu->cycles += currentCycles; \
94 }
95
96#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
97 DEFINE_INSTRUCTION_THUMB(NAME, \
98 int immediate = IMMEDIATE; \
99 int rd = opcode & 0x0007; \
100 int rm = (opcode >> 3) & 0x0007; \
101 BODY;)
102
103#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
104 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
105
106DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
107 if (!immediate) {
108 cpu->gprs[rd] = cpu->gprs[rm];
109 } else {
110 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
111 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
112 }
113 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
114
115DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
116 if (!immediate) {
117 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
118 cpu->gprs[rd] = 0;
119 } else {
120 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
121 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
122 }
123 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
124
125DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
126 if (!immediate) {
127 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
128 if (cpu->cpsr.c) {
129 cpu->gprs[rd] = 0xFFFFFFFF;
130 } else {
131 cpu->gprs[rd] = 0;
132 }
133 } else {
134 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
135 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
136 }
137 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
138
139DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles))
140DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rm] + immediate, ¤tCycles))
141DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles))
142DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
143DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
144DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
145
146#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
147 DEFINE_INSTRUCTION_THUMB(NAME, \
148 int rm = RM; \
149 int rd = opcode & 0x0007; \
150 int rn = (opcode >> 3) & 0x0007; \
151 BODY;)
152
153#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
154 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
155
156DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
157DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
158
159#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
160 DEFINE_INSTRUCTION_THUMB(NAME, \
161 int immediate = IMMEDIATE; \
162 int rd = opcode & 0x0007; \
163 int rn = (opcode >> 3) & 0x0007; \
164 BODY;)
165
166#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
167 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
168
169DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
170DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
171
172#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
173 DEFINE_INSTRUCTION_THUMB(NAME, \
174 int rd = RD; \
175 int immediate = opcode & 0x00FF; \
176 BODY;)
177
178#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
179 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
180
181DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
182DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
183DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
184DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
185
186#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
187 DEFINE_INSTRUCTION_THUMB(NAME, \
188 int rd = opcode & 0x0007; \
189 int rn = (opcode >> 3) & 0x0007; \
190 BODY;)
191
192DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
193DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
194DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
195 int rs = cpu->gprs[rn] & 0xFF;
196 if (rs) {
197 if (rs < 32) {
198 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
199 cpu->gprs[rd] <<= rs;
200 } else {
201 if (rs > 32) {
202 cpu->cpsr.c = 0;
203 } else {
204 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
205 }
206 cpu->gprs[rd] = 0;
207 }
208 }
209 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
210
211DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
212 int rs = cpu->gprs[rn] & 0xFF;
213 if (rs) {
214 if (rs < 32) {
215 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
216 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
217 } else {
218 if (rs > 32) {
219 cpu->cpsr.c = 0;
220 } else {
221 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
222 }
223 cpu->gprs[rd] = 0;
224 }
225 }
226 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
227
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
229 int rs = cpu->gprs[rn] & 0xFF;
230 if (rs) {
231 if (rs < 32) {
232 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
233 cpu->gprs[rd] >>= rs;
234 } else {
235 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
236 if (cpu->cpsr.c) {
237 cpu->gprs[rd] = 0xFFFFFFFF;
238 } else {
239 cpu->gprs[rd] = 0;
240 }
241 }
242 }
243 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
244
245DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
246 int n = cpu->gprs[rn];
247 int d = cpu->gprs[rd];
248 cpu->gprs[rd] = d + n + cpu->cpsr.c;
249 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
250
251DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
252 int n = cpu->gprs[rn] + !cpu->cpsr.c;
253 int d = cpu->gprs[rd];
254 cpu->gprs[rd] = d - n;
255 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
256DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
257 int rs = cpu->gprs[rn] & 0xFF;
258 if (rs) {
259 int r4 = rs & 0x1F;
260 if (r4 > 0) {
261 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
262 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
263 } else {
264 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
265 }
266 }
267 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
268DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
269DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
270DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
271DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
272DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
273DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
274DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
275DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
276
277#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
278 DEFINE_INSTRUCTION_THUMB(NAME, \
279 int rd = (opcode & 0x0007) | H1; \
280 int rm = ((opcode >> 3) & 0x0007) | H2; \
281 BODY;)
282
283#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
284 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
285 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
286 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
287 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
288
289DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
290 cpu->gprs[rd] += cpu->gprs[rm];
291 if (rd == ARM_PC) {
292 THUMB_WRITE_PC;
293 })
294
295DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
296DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
297 cpu->gprs[rd] = cpu->gprs[rm];
298 if (rd == ARM_PC) {
299 THUMB_WRITE_PC;
300 })
301
302#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
303 DEFINE_INSTRUCTION_THUMB(NAME, \
304 int rd = RD; \
305 int immediate = (opcode & 0x00FF) << 2; \
306 BODY;)
307
308#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
309 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
310
311DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles))
312DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles))
313DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
314
315DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
316DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
317
318#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
319 DEFINE_INSTRUCTION_THUMB(NAME, \
320 int rm = RM; \
321 int rd = opcode & 0x0007; \
322 int rn = (opcode >> 3) & 0x0007; \
323 BODY;)
324
325#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
326 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
327
328DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
329DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
330DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
331DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
332DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
333DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
334DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
335DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
336
337#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
338 DEFINE_INSTRUCTION_THUMB(NAME, \
339 int rn = RN; \
340 UNUSED(rn); \
341 int rs = opcode & 0xFF; \
342 int32_t address = ADDRESS; \
343 int m; \
344 int i; \
345 int total = 0; \
346 PRE_BODY; \
347 for LOOP { \
348 if (rs & m) { \
349 BODY; \
350 address OP 4; \
351 ++total; \
352 } \
353 } \
354 POST_BODY; \
355 currentCycles += cpu->memory.waitMultiple(cpu, address, total); \
356 WRITEBACK;)
357
358#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
359 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
360
361DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
362 cpu->gprs[i] = cpu->memory.load32(cpu, address, 0),
363 if (!((1 << rn) & rs)) {
364 cpu->gprs[rn] = address;
365 })
366
367DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
368 cpu->memory.store32(cpu, address, cpu->gprs[i], 0),
369 THUMB_STORE_POST_BODY;
370 cpu->gprs[rn] = address;)
371
372#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
373 DEFINE_INSTRUCTION_THUMB(B ## COND, \
374 if (ARM_COND_ ## COND) { \
375 int8_t immediate = opcode; \
376 cpu->gprs[ARM_PC] += immediate << 1; \
377 THUMB_WRITE_PC; \
378 })
379
380DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
381DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
382DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
383DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
384DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
385DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
386DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
387DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
388DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
389DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
390DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
391DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
392DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
393DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
394
395DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
396DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
397
398DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
399 opcode & 0x00FF,
400 cpu->gprs[ARM_SP],
401 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
402 cpu->gprs[i] = cpu->memory.load32(cpu, address, 0),
403 +=,
404 , ,
405 cpu->gprs[ARM_SP] = address)
406
407DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
408 opcode & 0x00FF,
409 cpu->gprs[ARM_SP],
410 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
411 cpu->gprs[i] = cpu->memory.load32(cpu, address, 0),
412 +=,
413 ,
414 cpu->gprs[ARM_PC] = cpu->memory.load32(cpu, address, 0) & 0xFFFFFFFE;
415 address += 4;,
416 cpu->gprs[ARM_SP] = address;
417 THUMB_WRITE_PC;)
418
419DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
420 opcode & 0x00FF,
421 cpu->gprs[ARM_SP] - 4,
422 (m = 0x80, i = 7; m; m >>= 1, --i),
423 cpu->memory.store32(cpu, address, cpu->gprs[i], 0),
424 -=,
425 ,
426 THUMB_STORE_POST_BODY,
427 cpu->gprs[ARM_SP] = address + 4)
428
429DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
430 opcode & 0x00FF,
431 cpu->gprs[ARM_SP] - 4,
432 (m = 0x80, i = 7; m; m >>= 1, --i),
433 cpu->memory.store32(cpu, address, cpu->gprs[i], 0),
434 -=,
435 cpu->memory.store32(cpu, address, cpu->gprs[ARM_LR], 0);
436 address -= 4;,
437 THUMB_STORE_POST_BODY,
438 cpu->gprs[ARM_SP] = address + 4)
439
440DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
441DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
442DEFINE_INSTRUCTION_THUMB(B,
443 int16_t immediate = (opcode & 0x07FF) << 5;
444 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
445 THUMB_WRITE_PC;)
446
447DEFINE_INSTRUCTION_THUMB(BL1,
448 int16_t immediate = (opcode & 0x07FF) << 5;
449 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
450
451DEFINE_INSTRUCTION_THUMB(BL2,
452 uint16_t immediate = (opcode & 0x07FF) << 1;
453 uint32_t pc = cpu->gprs[ARM_PC];
454 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
455 cpu->gprs[ARM_LR] = pc - 1;
456 THUMB_WRITE_PC;)
457
458DEFINE_INSTRUCTION_THUMB(BX,
459 int rm = (opcode >> 3) & 0xF;
460 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
461 int misalign = 0;
462 if (rm == ARM_PC) {
463 misalign = cpu->gprs[rm] & 0x00000002;
464 }
465 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
466 if (cpu->executionMode == MODE_THUMB) {
467 THUMB_WRITE_PC;
468 } else {
469 ARM_WRITE_PC;
470 })
471
472DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
473
474#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
475 EMITTER ## NAME
476
477#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
478 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
479 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
480 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
481 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
482
483#define DUMMY(X, ...) X,
484#define DUMMY_4(...) \
485 DUMMY(__VA_ARGS__) \
486 DUMMY(__VA_ARGS__) \
487 DUMMY(__VA_ARGS__) \
488 DUMMY(__VA_ARGS__)
489
490#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
491 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
492 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
493 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
494 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
495 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
496 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
497 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
498 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
499 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
500 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
501 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
502 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
503 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
504 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
505 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
506 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
507 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
508 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
509 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
510 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
511 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
512 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
513 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
514 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
515 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
516 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
517 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
518 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
519 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
520 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
521 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
522 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
523 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
524 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
525 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
526 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
527 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
528 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
529 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
530 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
531 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
532 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
533 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
534 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
535 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
536 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
537 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
538 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
539 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
540 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
541 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
542 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
543 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
544 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
545 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
546 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
547 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
548 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
549 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
550 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
551 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
552 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
553 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
554 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
555 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
556 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
557 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
558 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
559 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
560 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
561 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
562 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
563 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
564 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
565 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
566 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
567 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
568 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
569 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
570 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
571 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
572 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
573 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
574 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
575 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
576 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
577 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
578 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
579 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
580 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
581 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2)))
582
583const ThumbInstruction _thumbTable[0x400] = {
584 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
585};