src/gba/dma.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/dma.h>
7
8#include <mgba/internal/gba/gba.h>
9#include <mgba/internal/gba/io.h>
10
11static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
12
13static void GBADMAService(struct GBA* gba, int number, struct GBADMA* info);
14
15static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
16
17void GBADMAInit(struct GBA* gba) {
18 gba->memory.dmaEvent.name = "GBA DMA";
19 gba->memory.dmaEvent.callback = _dmaEvent;
20 gba->memory.dmaEvent.context = gba;
21 gba->memory.dmaEvent.priority = 0x40;
22}
23
24void GBADMAReset(struct GBA* gba) {
25 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
26 int i;
27 for (i = 0; i < 4; ++i) {
28 gba->memory.dma[i].count = 0x4000;
29 }
30 gba->memory.dma[3].count = 0x10000;
31 gba->memory.activeDMA = -1;
32}
33static bool _isValidDMASAD(int dma, uint32_t address) {
34 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
35 return false;
36 }
37 return address >= BASE_WORKING_RAM;
38}
39
40static bool _isValidDMADAD(int dma, uint32_t address) {
41 return dma == 3 || address < BASE_CART0;
42}
43
44uint32_t GBADMAWriteSAD(struct GBA* gba, int dma, uint32_t address) {
45 struct GBAMemory* memory = &gba->memory;
46 address &= 0x0FFFFFFE;
47 if (_isValidDMASAD(dma, address)) {
48 memory->dma[dma].source = address;
49 } else {
50 memory->dma[dma].source = 0;
51 }
52 return memory->dma[dma].source;
53}
54
55uint32_t GBADMAWriteDAD(struct GBA* gba, int dma, uint32_t address) {
56 struct GBAMemory* memory = &gba->memory;
57 address &= 0x0FFFFFFE;
58 if (_isValidDMADAD(dma, address)) {
59 memory->dma[dma].dest = address;
60 }
61 return memory->dma[dma].dest;
62}
63
64void GBADMAWriteCNT_LO(struct GBA* gba, int dma, uint16_t count) {
65 struct GBAMemory* memory = &gba->memory;
66 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
67}
68
69uint16_t GBADMAWriteCNT_HI(struct GBA* gba, int dma, uint16_t control) {
70 struct GBAMemory* memory = &gba->memory;
71 struct GBADMA* currentDma = &memory->dma[dma];
72 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
73 if (dma < 3) {
74 control &= 0xF7E0;
75 } else {
76 control &= 0xFFE0;
77 }
78 currentDma->reg = control;
79
80 if (GBADMARegisterIsDRQ(currentDma->reg)) {
81 mLOG(GBA_MEM, STUB, "DRQ not implemented");
82 }
83
84 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
85 currentDma->nextSource = currentDma->source;
86 if (currentDma->nextSource >= BASE_CART0 && currentDma->nextSource < BASE_CART_SRAM && GBADMARegisterGetSrcControl(currentDma->reg) < 3) {
87 currentDma->reg = GBADMARegisterClearSrcControl(currentDma->reg);
88 }
89 currentDma->nextDest = currentDma->dest;
90
91 uint32_t width = 2 << GBADMARegisterGetWidth(currentDma->reg);
92 if (currentDma->nextSource & (width - 1)) {
93 mLOG(GBA_MEM, GAME_ERROR, "Misaligned DMA source address: 0x%08X", currentDma->nextSource);
94 }
95 if (currentDma->nextDest & (width - 1)) {
96 mLOG(GBA_MEM, GAME_ERROR, "Misaligned DMA destination address: 0x%08X", currentDma->nextDest);
97 }
98
99 GBADMASchedule(gba, dma, currentDma);
100 }
101 // If the DMA has already occurred, this value might have changed since the function started
102 return currentDma->reg;
103};
104
105void GBADMASchedule(struct GBA* gba, int number, struct GBADMA* info) {
106 switch (GBADMARegisterGetTiming(info->reg)) {
107 case GBA_DMA_TIMING_NOW:
108 info->when = mTimingCurrentTime(&gba->timing) + 3; // DMAs take 3 cycles to start
109 info->nextCount = info->count;
110 break;
111 case GBA_DMA_TIMING_HBLANK:
112 case GBA_DMA_TIMING_VBLANK:
113 // Handled implicitly
114 return;
115 case GBA_DMA_TIMING_CUSTOM:
116 switch (number) {
117 case 0:
118 mLOG(GBA_MEM, WARN, "Discarding invalid DMA0 scheduling");
119 return;
120 case 1:
121 case 2:
122 GBAAudioScheduleFifoDma(&gba->audio, number, info);
123 break;
124 case 3:
125 // Handled implicitly
126 break;
127 }
128 }
129 GBADMAUpdate(gba);
130}
131
132void GBADMARunHblank(struct GBA* gba, int32_t cycles) {
133 struct GBAMemory* memory = &gba->memory;
134 struct GBADMA* dma;
135 int i;
136 for (i = 0; i < 4; ++i) {
137 dma = &memory->dma[i];
138 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_HBLANK && !dma->nextCount) {
139 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
140 dma->nextCount = dma->count;
141 }
142 }
143 GBADMAUpdate(gba);
144}
145
146void GBADMARunVblank(struct GBA* gba, int32_t cycles) {
147 struct GBAMemory* memory = &gba->memory;
148 struct GBADMA* dma;
149 int i;
150 for (i = 0; i < 4; ++i) {
151 dma = &memory->dma[i];
152 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_VBLANK && !dma->nextCount) {
153 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
154 dma->nextCount = dma->count;
155 }
156 }
157 GBADMAUpdate(gba);
158}
159
160void GBADMARunDisplayStart(struct GBA* gba, int32_t cycles) {
161 struct GBAMemory* memory = &gba->memory;
162 struct GBADMA* dma = &memory->dma[3];
163 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_CUSTOM && !dma->nextCount) {
164 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
165 dma->nextCount = dma->count;
166 GBADMAUpdate(gba);
167 }
168}
169
170void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
171 UNUSED(timing);
172 UNUSED(cyclesLate);
173 struct GBA* gba = context;
174 struct GBAMemory* memory = &gba->memory;
175 struct GBADMA* dma = &memory->dma[memory->activeDMA];
176 if (dma->nextCount == dma->count) {
177 dma->when = mTimingCurrentTime(&gba->timing);
178 }
179 if (dma->nextCount & 0xFFFFF) {
180 GBADMAService(gba, memory->activeDMA, dma);
181 } else {
182 dma->nextCount = 0;
183 bool noRepeat = !GBADMARegisterIsRepeat(dma->reg);
184 noRepeat |= GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_NOW;
185 noRepeat |= memory->activeDMA == 3 && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_CUSTOM;
186 if (noRepeat) {
187 dma->reg = GBADMARegisterClearEnable(dma->reg);
188
189 // Clear the enable bit in memory
190 memory->io[(REG_DMA0CNT_HI + memory->activeDMA * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
191 }
192 if (GBADMARegisterGetDestControl(dma->reg) == GBA_DMA_INCREMENT_RELOAD) {
193 dma->nextDest = dma->dest;
194 }
195 if (GBADMARegisterIsDoIRQ(dma->reg)) {
196 GBARaiseIRQ(gba, IRQ_DMA0 + memory->activeDMA);
197 }
198 GBADMAUpdate(gba);
199 }
200}
201
202void GBADMAUpdate(struct GBA* gba) {
203 int i;
204 struct GBAMemory* memory = &gba->memory;
205 uint32_t currentTime = mTimingCurrentTime(&gba->timing);
206 int32_t leastTime = INT_MAX;
207 memory->activeDMA = -1;
208 for (i = 0; i < 4; ++i) {
209 struct GBADMA* dma = &memory->dma[i];
210 if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
211 int32_t time = dma->when - currentTime;
212 if (memory->activeDMA == -1 || (dma->count == dma->nextCount && time < leastTime)) {
213 leastTime = time;
214 memory->activeDMA = i;
215 }
216 }
217 }
218
219 if (memory->activeDMA >= 0) {
220 mTimingDeschedule(&gba->timing, &memory->dmaEvent);
221 mTimingSchedule(&gba->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
222 } else {
223 gba->cpuBlocked = false;
224 }
225}
226
227void GBADMAService(struct GBA* gba, int number, struct GBADMA* info) {
228 struct GBAMemory* memory = &gba->memory;
229 struct ARMCore* cpu = gba->cpu;
230 uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
231 int32_t wordsRemaining = info->nextCount;
232 uint32_t source = info->nextSource;
233 uint32_t dest = info->nextDest;
234 uint32_t sourceRegion = source >> BASE_OFFSET;
235 uint32_t destRegion = dest >> BASE_OFFSET;
236 int32_t cycles = 2;
237
238 gba->cpuBlocked = true;
239 if (info->count == info->nextCount) {
240 if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
241 cycles += 2;
242 }
243 if (width == 4) {
244 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
245 } else {
246 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
247 }
248 source &= -width;
249 dest &= -width;
250 } else {
251 if (width == 4) {
252 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
253 } else {
254 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
255 }
256 }
257 info->when += cycles;
258
259 gba->performingDMA = 1 | (number << 1);
260 if (width == 4) {
261 if (source) {
262 memory->dmaTransferRegister = cpu->memory.load32(cpu, source, 0);
263 }
264 gba->bus = memory->dmaTransferRegister;
265 cpu->memory.store32(cpu, dest, memory->dmaTransferRegister, 0);
266 memory->dmaTransferRegister &= 0xFFFF0000;
267 memory->dmaTransferRegister |= memory->dmaTransferRegister >> 16;
268 } else {
269 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
270 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
271 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
272 GBASavedataInitEEPROM(&memory->savedata);
273 }
274 memory->dmaTransferRegister = GBASavedataReadEEPROM(&memory->savedata);
275 } else {
276 if (source) {
277 memory->dmaTransferRegister = cpu->memory.load16(cpu, source, 0);
278 }
279 }
280 if (destRegion == REGION_CART2_EX) {
281 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
282 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
283 GBASavedataInitEEPROM(&memory->savedata);
284 }
285 GBASavedataWriteEEPROM(&memory->savedata, memory->dmaTransferRegister, wordsRemaining);
286 } else {
287 cpu->memory.store16(cpu, dest, memory->dmaTransferRegister, 0);
288
289 }
290 memory->dmaTransferRegister |= memory->dmaTransferRegister << 16;
291 gba->bus = memory->dmaTransferRegister;
292 }
293 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
294 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
295 if (source) {
296 source += sourceOffset;
297 }
298 dest += destOffset;
299 --wordsRemaining;
300 gba->performingDMA = 0;
301
302 info->nextCount = wordsRemaining;
303 info->nextSource = source;
304 info->nextDest = dest;
305 if (!wordsRemaining) {
306 info->nextCount |= 0x80000000;
307 }
308 GBADMAUpdate(gba);
309}