1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_DECODER_H
  7#define ARM_DECODER_H
  8
  9#include "arm.h"
 10
 11// Bit 0: a register is involved with this operand
 12// Bit 1: an immediate is invovled with this operand
 13// Bit 2: a memory access is invovled with this operand
 14// Bit 3: the destination of this operand is affected by this opcode
 15// Bit 4: this operand is shifted by a register
 16// Bit 5: this operand is shifted by an immediate
 17#define ARM_OPERAND_NONE                0x00000000
 18#define ARM_OPERAND_REGISTER_1          0x00000001
 19#define ARM_OPERAND_IMMEDIATE_1         0x00000002
 20#define ARM_OPERAND_MEMORY_1            0x00000004
 21#define ARM_OPERAND_AFFECTED_1          0x00000008
 22#define ARM_OPERAND_SHIFT_REGISTER_1    0x00000010
 23#define ARM_OPERAND_SHIFT_IMMEDIATE_1   0x00000020
 24#define ARM_OPERAND_1                   0x000000FF
 25
 26#define ARM_OPERAND_REGISTER_2          0x00000100
 27#define ARM_OPERAND_IMMEDIATE_2         0x00000200
 28#define ARM_OPERAND_MEMORY_2            0x00000400
 29#define ARM_OPERAND_AFFECTED_2          0x00000800
 30#define ARM_OPERAND_SHIFT_REGISTER_2    0x00001000
 31#define ARM_OPERAND_SHIFT_IMMEDIATE_2   0x00002000
 32#define ARM_OPERAND_2                   0x0000FF00
 33
 34#define ARM_OPERAND_REGISTER_3          0x00010000
 35#define ARM_OPERAND_IMMEDIATE_3         0x00020000
 36#define ARM_OPERAND_MEMORY_3            0x00040000
 37#define ARM_OPERAND_AFFECTED_3          0x00080000
 38#define ARM_OPERAND_SHIFT_REGISTER_3    0x00100000
 39#define ARM_OPERAND_SHIFT_IMMEDIATE_3   0x00200000
 40#define ARM_OPERAND_3                   0x00FF0000
 41
 42#define ARM_OPERAND_REGISTER_4          0x01000000
 43#define ARM_OPERAND_IMMEDIATE_4         0x02000000
 44#define ARM_OPERAND_MEMORY_4            0x04000000
 45#define ARM_OPERAND_AFFECTED_4          0x08000000
 46#define ARM_OPERAND_SHIFT_REGISTER_4    0x10000000
 47#define ARM_OPERAND_SHIFT_IMMEDIATE_4   0x20000000
 48#define ARM_OPERAND_4                   0xFF000000
 49
 50
 51#define ARM_MEMORY_REGISTER_BASE     0x0001
 52#define ARM_MEMORY_IMMEDIATE_OFFSET  0x0002
 53#define ARM_MEMORY_REGISTER_OFFSET   0x0004
 54#define ARM_MEMORY_SHIFTED_OFFSET    0x0008
 55#define ARM_MEMORY_PRE_INCREMENT     0x0010
 56#define ARM_MEMORY_POST_INCREMENT    0x0020
 57#define ARM_MEMORY_OFFSET_SUBTRACT   0x0040
 58#define ARM_MEMORY_WRITEBACK         0x0080
 59#define ARM_MEMORY_DECREMENT_AFTER   0x0000
 60#define ARM_MEMORY_INCREMENT_AFTER   0x0100
 61#define ARM_MEMORY_DECREMENT_BEFORE  0x0200
 62#define ARM_MEMORY_INCREMENT_BEFORE  0x0300
 63#define ARM_MEMORY_SPSR_SWAP         0x0400
 64
 65#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
 66
 67enum ARMCondition {
 68	ARM_CONDITION_EQ = 0x0,
 69	ARM_CONDITION_NE = 0x1,
 70	ARM_CONDITION_CS = 0x2,
 71	ARM_CONDITION_CC = 0x3,
 72	ARM_CONDITION_MI = 0x4,
 73	ARM_CONDITION_PL = 0x5,
 74	ARM_CONDITION_VS = 0x6,
 75	ARM_CONDITION_VC = 0x7,
 76	ARM_CONDITION_HI = 0x8,
 77	ARM_CONDITION_LS = 0x9,
 78	ARM_CONDITION_GE = 0xA,
 79	ARM_CONDITION_LT = 0xB,
 80	ARM_CONDITION_GT = 0xC,
 81	ARM_CONDITION_LE = 0xD,
 82	ARM_CONDITION_AL = 0xE,
 83	ARM_CONDITION_NV = 0xF
 84};
 85
 86enum ARMShifterOperation {
 87	ARM_SHIFT_NONE = 0,
 88	ARM_SHIFT_LSL,
 89	ARM_SHIFT_LSR,
 90	ARM_SHIFT_ASR,
 91	ARM_SHIFT_ROR,
 92	ARM_SHIFT_RRX
 93};
 94
 95union ARMOperand {
 96	struct {
 97		uint8_t reg;
 98		uint8_t shifterOp;
 99		union {
100			uint8_t shifterReg;
101			uint8_t shifterImm;
102		};
103	};
104	int32_t immediate;
105};
106
107enum ARMMemoryAccessType {
108	ARM_ACCESS_WORD = 4,
109	ARM_ACCESS_HALFWORD = 2,
110	ARM_ACCESS_SIGNED_HALFWORD = 10,
111	ARM_ACCESS_BYTE = 1,
112	ARM_ACCESS_SIGNED_BYTE = 9,
113	ARM_ACCESS_TRANSLATED_WORD = 20,
114	ARM_ACCESS_TRANSLATED_BYTE = 17
115};
116
117enum ARMBranchType {
118	ARM_BRANCH_NONE = 0,
119	ARM_BRANCH = 1,
120	ARM_BRANCH_INDIRECT = 2,
121	ARM_BRANCH_LINKED = 4
122};
123
124struct ARMMemoryAccess {
125	uint8_t baseReg;
126	uint8_t width;
127	uint16_t format;
128	union ARMOperand offset;
129};
130
131enum ARMMnemonic {
132	ARM_MN_ILL = 0,
133	ARM_MN_ADC,
134	ARM_MN_ADD,
135	ARM_MN_AND,
136	ARM_MN_ASR,
137	ARM_MN_B,
138	ARM_MN_BIC,
139	ARM_MN_BKPT,
140	ARM_MN_BL,
141	ARM_MN_BLH,
142	ARM_MN_BX,
143	ARM_MN_CMN,
144	ARM_MN_CMP,
145	ARM_MN_EOR,
146	ARM_MN_LDM,
147	ARM_MN_LDR,
148	ARM_MN_LSL,
149	ARM_MN_LSR,
150	ARM_MN_MLA,
151	ARM_MN_MOV,
152	ARM_MN_MRS,
153	ARM_MN_MSR,
154	ARM_MN_MUL,
155	ARM_MN_MVN,
156	ARM_MN_NEG,
157	ARM_MN_ORR,
158	ARM_MN_ROR,
159	ARM_MN_RSB,
160	ARM_MN_RSC,
161	ARM_MN_SBC,
162	ARM_MN_SMLAL,
163	ARM_MN_SMULL,
164	ARM_MN_STM,
165	ARM_MN_STR,
166	ARM_MN_SUB,
167	ARM_MN_SWI,
168	ARM_MN_SWP,
169	ARM_MN_TEQ,
170	ARM_MN_TST,
171	ARM_MN_UMLAL,
172	ARM_MN_UMULL,
173
174	ARM_MN_MAX
175};
176
177enum {
178	ARM_CPSR = 16,
179	ARM_SPSR = 17
180};
181
182struct ARMInstructionInfo {
183	uint32_t opcode;
184	union ARMOperand op1;
185	union ARMOperand op2;
186	union ARMOperand op3;
187	union ARMOperand op4;
188	struct ARMMemoryAccess memory;
189	int operandFormat;
190	unsigned execMode : 1;
191	bool traps : 1;
192	bool affectsCPSR : 1;
193	unsigned branchType : 3;
194	unsigned condition : 4;
195	unsigned mnemonic : 6;
196	unsigned iCycles : 3;
197	unsigned cCycles : 4;
198	unsigned sInstructionCycles : 4;
199	unsigned nInstructionCycles : 4;
200	unsigned sDataCycles : 10;
201	unsigned nDataCycles : 10;
202};
203
204void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
205void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
206int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
207
208#endif