src/ds/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/io.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/ds/ds.h>
10#include <mgba/internal/ds/ipc.h>
11#include <mgba/internal/ds/spi.h>
12
13mLOG_DEFINE_CATEGORY(DS_IO, "DS I/O");
14
15static void _DSHaltCNT(struct DSCommon* dscore, uint8_t value) {
16 switch (value >> 6) {
17 case 0:
18 default:
19 break;
20 case 1:
21 mLOG(DS_IO, STUB, "Enter GBA mode not supported");
22 break;
23 case 2:
24 ARMHalt(dscore->cpu);
25 break;
26 case 3:
27 mLOG(DS_IO, STUB, "Enter sleep mode not supported");
28 break;
29 }
30}
31
32static uint16_t _scheduleDiv(struct DS* ds, uint16_t control) {
33 mTimingDeschedule(&ds->ds9.timing, &ds->divEvent);
34 mTimingSchedule(&ds->ds9.timing, &ds->divEvent, (control & 3) ? 36 : 68);
35 return control | 0x8000;
36}
37
38static uint16_t _scheduleSqrt(struct DS* ds, uint16_t control) {
39 mTimingDeschedule(&ds->ds9.timing, &ds->sqrtEvent);
40 mTimingSchedule(&ds->ds9.timing, &ds->sqrtEvent, 26);
41 return control | 0x8000;
42}
43
44static uint32_t DSIOWrite(struct DSCommon* dscore, uint32_t address, uint16_t value) {
45 switch (address) {
46 // Video
47 case DS_REG_DISPSTAT:
48 DSVideoWriteDISPSTAT(dscore, value);
49 break;
50
51 // DMA Fill
52 case DS_REG_DMA0FILL_LO:
53 case DS_REG_DMA0FILL_HI:
54 case DS_REG_DMA1FILL_LO:
55 case DS_REG_DMA1FILL_HI:
56 case DS_REG_DMA2FILL_LO:
57 case DS_REG_DMA2FILL_HI:
58 case DS_REG_DMA3FILL_LO:
59 case DS_REG_DMA3FILL_HI:
60 break;
61
62 // Timers
63 case DS_REG_TM0CNT_LO:
64 GBATimerWriteTMCNT_LO(&dscore->timers[0], value);
65 return 0x20000;
66 case DS_REG_TM1CNT_LO:
67 GBATimerWriteTMCNT_LO(&dscore->timers[1], value);
68 return 0x20000;
69 case DS_REG_TM2CNT_LO:
70 GBATimerWriteTMCNT_LO(&dscore->timers[2], value);
71 return 0x20000;
72 case DS_REG_TM3CNT_LO:
73 GBATimerWriteTMCNT_LO(&dscore->timers[3], value);
74 return 0x20000;
75
76 case DS_REG_TM0CNT_HI:
77 value &= 0x00C7;
78 DSTimerWriteTMCNT_HI(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM0CNT_LO >> 1], value);
79 break;
80 case DS_REG_TM1CNT_HI:
81 value &= 0x00C7;
82 DSTimerWriteTMCNT_HI(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM1CNT_LO >> 1], value);
83 break;
84 case DS_REG_TM2CNT_HI:
85 value &= 0x00C7;
86 DSTimerWriteTMCNT_HI(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM2CNT_LO >> 1], value);
87 break;
88 case DS_REG_TM3CNT_HI:
89 value &= 0x00C7;
90 DSTimerWriteTMCNT_HI(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM3CNT_LO >> 1], value);
91 break;
92
93 // IPC
94 case DS_REG_IPCSYNC:
95 value &= 0x6F00;
96 value |= dscore->memory.io[address >> 1] & 0x000F;
97 DSIPCWriteSYNC(dscore->ipc->cpu, dscore->ipc->memory.io, value);
98 break;
99 case DS_REG_IPCFIFOCNT:
100 value = DSIPCWriteFIFOCNT(dscore, value);
101 break;
102
103 // Cart bus
104 case DS_REG_SLOT1CNT_LO:
105 mLOG(DS_IO, STUB, "ROM control not implemented");
106 value &= 0x7FFF;
107 break;
108
109 // Interrupts
110 case DS_REG_IME:
111 DSWriteIME(dscore->cpu, dscore->memory.io, value);
112 break;
113 case 0x20A:
114 value = 0;
115 // Some bad interrupt libraries will write to this
116 break;
117 case DS_REG_IF_LO:
118 case DS_REG_IF_HI:
119 value = dscore->memory.io[address >> 1] & ~value;
120 break;
121 default:
122 return 0;
123 }
124 return value | 0x10000;
125}
126
127static uint16_t DSIOReadKeyInput(struct DS* ds) {
128 uint16_t input = 0x3FF;
129 if (ds->keyCallback) {
130 input = ds->keyCallback->readKeys(ds->keyCallback);
131 } else if (ds->keySource) {
132 input = *ds->keySource;
133 }
134 // TODO: Put back
135 /*if (!dscore->p->allowOpposingDirections) {
136 unsigned rl = input & 0x030;
137 unsigned ud = input & 0x0C0;
138 input &= 0x30F;
139 if (rl != 0x030) {
140 input |= rl;
141 }
142 if (ud != 0x0C0) {
143 input |= ud;
144 }
145 }*/
146 return 0x3FF ^ input;
147}
148
149static void DSIOUpdateTimer(struct DSCommon* dscore, uint32_t address) {
150 switch (address) {
151 case DS_REG_TM0CNT_LO:
152 GBATimerUpdateRegisterInternal(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
153 break;
154 case DS_REG_TM1CNT_LO:
155 GBATimerUpdateRegisterInternal(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
156 break;
157 case DS_REG_TM2CNT_LO:
158 GBATimerUpdateRegisterInternal(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
159 break;
160 case DS_REG_TM3CNT_LO:
161 GBATimerUpdateRegisterInternal(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
162 break;
163 }
164}
165
166void DS7IOInit(struct DS* ds) {
167 memset(ds->memory.io7, 0, sizeof(ds->memory.io7));
168}
169
170void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
171 switch (address) {
172 case DS7_REG_SPICNT:
173 value &= 0xCF83;
174 value = DSSPIWriteControl(ds, value);
175 break;
176 case DS7_REG_SPIDATA:
177 DSSPIWrite(ds, value);
178 return;
179 default:
180 {
181 uint32_t v2 = DSIOWrite(&ds->ds7, address, value);
182 if (v2 & 0x10000) {
183 value = v2;
184 break;
185 } else if (v2 & 0x20000) {
186 return;
187 }
188 }
189 mLOG(DS_IO, STUB, "Stub DS7 I/O register write: %06X:%04X", address, value);
190 if (address >= DS7_REG_MAX) {
191 mLOG(DS_IO, GAME_ERROR, "Write to unused DS7 I/O register: %06X:%04X", address, value);
192 return;
193 }
194 break;
195 }
196 ds->memory.io7[address >> 1] = value;
197}
198
199void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
200 if (address == DS7_REG_HALTCNT) {
201 _DSHaltCNT(&ds->ds7, value);
202 return;
203 }
204 if (address < DS7_REG_MAX) {
205 uint16_t value16 = value << (8 * (address & 1));
206 value16 |= (ds->ds7.memory.io[(address & 0xFFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
207 DS7IOWrite(ds, address & 0xFFFFFFFE, value16);
208 } else {
209 mLOG(DS, STUB, "Writing to unknown DS7 register: %08X:%02X", address, value);
210 }
211}
212
213void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
214 switch (address) {
215 case DS_REG_DMA0SAD_LO:
216 value = DSDMAWriteSAD(&ds->ds7, 0, value);
217 break;
218 case DS_REG_DMA1SAD_LO:
219 value = DSDMAWriteSAD(&ds->ds7, 1, value);
220 break;
221 case DS_REG_DMA2SAD_LO:
222 value = DSDMAWriteSAD(&ds->ds7, 2, value);
223 break;
224 case DS_REG_DMA3SAD_LO:
225 value = DSDMAWriteSAD(&ds->ds7, 3, value);
226 break;
227
228 case DS_REG_DMA0DAD_LO:
229 value = DSDMAWriteDAD(&ds->ds7, 0, value);
230 break;
231 case DS_REG_DMA1DAD_LO:
232 value = DSDMAWriteDAD(&ds->ds7, 1, value);
233 break;
234 case DS_REG_DMA2DAD_LO:
235 value = DSDMAWriteDAD(&ds->ds7, 2, value);
236 break;
237 case DS_REG_DMA3DAD_LO:
238 value = DSDMAWriteDAD(&ds->ds7, 3, value);
239 break;
240
241 case DS_REG_DMA0CNT_LO:
242 DS7DMAWriteCNT(&ds->ds7, 0, value);
243 break;
244 case DS_REG_DMA1CNT_LO:
245 DS7DMAWriteCNT(&ds->ds7, 1, value);
246 break;
247 case DS_REG_DMA2CNT_LO:
248 DS7DMAWriteCNT(&ds->ds7, 2, value);
249 break;
250 case DS_REG_DMA3CNT_LO:
251 DS7DMAWriteCNT(&ds->ds7, 3, value);
252 break;
253
254 case DS_REG_IPCFIFOSEND_LO:
255 DSIPCWriteFIFO(&ds->ds7, value);
256 break;
257 case DS_REG_IE_LO:
258 DSWriteIE(ds->ds7.cpu, ds->ds7.memory.io, value);
259 break;
260 default:
261 DS7IOWrite(ds, address, value & 0xFFFF);
262 DS7IOWrite(ds, address | 2, value >> 16);
263 return;
264 }
265 ds->ds7.memory.io[address >> 1] = value;
266 ds->ds7.memory.io[(address >> 1) + 1] = value >> 16;
267}
268
269uint16_t DS7IORead(struct DS* ds, uint32_t address) {
270 switch (address) {
271 case DS_REG_TM0CNT_LO:
272 case DS_REG_TM1CNT_LO:
273 case DS_REG_TM2CNT_LO:
274 case DS_REG_TM3CNT_LO:
275 DSIOUpdateTimer(&ds->ds7, address);
276 break;
277 case DS_REG_KEYINPUT:
278 return DSIOReadKeyInput(ds);
279 case DS_REG_DMA0FILL_LO:
280 case DS_REG_DMA0FILL_HI:
281 case DS_REG_DMA1FILL_LO:
282 case DS_REG_DMA1FILL_HI:
283 case DS_REG_DMA2FILL_LO:
284 case DS_REG_DMA2FILL_HI:
285 case DS_REG_DMA3FILL_LO:
286 case DS_REG_DMA3FILL_HI:
287 case DS_REG_TM0CNT_HI:
288 case DS_REG_TM1CNT_HI:
289 case DS_REG_TM2CNT_HI:
290 case DS_REG_TM3CNT_HI:
291 case DS7_REG_SPICNT:
292 case DS7_REG_SPIDATA:
293 case DS_REG_IPCSYNC:
294 case DS_REG_IPCFIFOCNT:
295 case DS_REG_IME:
296 case 0x20A:
297 case DS_REG_IE_LO:
298 case DS_REG_IE_HI:
299 case DS_REG_IF_LO:
300 case DS_REG_IF_HI:
301 // Handled transparently by the registers
302 break;
303 default:
304 mLOG(DS_IO, STUB, "Stub DS7 I/O register read: %06X", address);
305 }
306 if (address < DS7_REG_MAX) {
307 return ds->memory.io7[address >> 1];
308 }
309 return 0;
310}
311
312uint32_t DS7IORead32(struct DS* ds, uint32_t address) {
313 switch (address) {
314 case DS_REG_IPCFIFORECV_LO:
315 return DSIPCReadFIFO(&ds->ds7);
316 default:
317 return DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
318 }
319}
320
321void DS9IOInit(struct DS* ds) {
322 memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
323}
324
325void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
326 switch (address) {
327 // VRAM control
328 case DS9_REG_VRAMCNT_A:
329 case DS9_REG_VRAMCNT_C:
330 case DS9_REG_VRAMCNT_E:
331 DSVideoConfigureVRAM(&ds->memory, address - DS9_REG_VRAMCNT_A + 1, value & 0xFF);
332 DSVideoConfigureVRAM(&ds->memory, address - DS9_REG_VRAMCNT_A, value >> 8);
333 break;
334 case DS9_REG_VRAMCNT_G:
335 DSVideoConfigureVRAM(&ds->memory, 6, value >> 8);
336 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address + 1, value);
337 break;
338 case DS9_REG_VRAMCNT_H:
339 DSVideoConfigureVRAM(&ds->memory, 7, value >> 8);
340 DSVideoConfigureVRAM(&ds->memory, 8, value & 0xFF);
341 break;
342
343 // Math
344 case DS9_REG_DIVCNT:
345 value = _scheduleDiv(ds, value);
346 break;
347 case DS9_REG_DIV_NUMER_0:
348 case DS9_REG_DIV_NUMER_1:
349 case DS9_REG_DIV_NUMER_2:
350 case DS9_REG_DIV_NUMER_3:
351 case DS9_REG_DIV_DENOM_0:
352 case DS9_REG_DIV_DENOM_1:
353 case DS9_REG_DIV_DENOM_2:
354 case DS9_REG_DIV_DENOM_3:
355 ds->memory.io9[DS9_REG_DIVCNT >> 1] = _scheduleDiv(ds, ds->memory.io9[DS9_REG_DIVCNT >> 1]);
356 break;
357 case DS9_REG_SQRTCNT:
358 value = _scheduleSqrt(ds, value);
359 break;
360 case DS9_REG_SQRT_PARAM_0:
361 case DS9_REG_SQRT_PARAM_1:
362 case DS9_REG_SQRT_PARAM_2:
363 case DS9_REG_SQRT_PARAM_3:
364 ds->memory.io9[DS9_REG_SQRTCNT >> 1] = _scheduleSqrt(ds, ds->memory.io9[DS9_REG_SQRTCNT >> 1]);
365 break;
366
367 default:
368 {
369 uint32_t v2 = DSIOWrite(&ds->ds9, address, value);
370 if (v2 & 0x10000) {
371 value = v2;
372 break;
373 } else if (v2 & 0x20000) {
374 return;
375 }
376 }
377 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address, value);
378 if (address >= DS7_REG_MAX) {
379 mLOG(DS_IO, GAME_ERROR, "Write to unused DS9 I/O register: %06X:%04X", address, value);
380 return;
381 }
382 break;
383 }
384 ds->memory.io9[address >> 1] = value;
385}
386
387void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
388 if (address < DS9_REG_MAX) {
389 uint16_t value16 = value << (8 * (address & 1));
390 value16 |= (ds->memory.io9[(address & 0x1FFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
391 DS9IOWrite(ds, address & 0xFFFFFFFE, value16);
392 } else {
393 mLOG(DS, STUB, "Writing to unknown DS9 register: %08X:%02X", address, value);
394 }
395}
396
397void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
398 switch (address) {
399 case DS_REG_DMA0SAD_LO:
400 value = DSDMAWriteSAD(&ds->ds9, 0, value);
401 break;
402 case DS_REG_DMA1SAD_LO:
403 value = DSDMAWriteSAD(&ds->ds9, 1, value);
404 break;
405 case DS_REG_DMA2SAD_LO:
406 value = DSDMAWriteSAD(&ds->ds9, 2, value);
407 break;
408 case DS_REG_DMA3SAD_LO:
409 value = DSDMAWriteSAD(&ds->ds9, 3, value);
410 break;
411
412 case DS_REG_DMA0DAD_LO:
413 value = DSDMAWriteDAD(&ds->ds9, 0, value);
414 break;
415 case DS_REG_DMA1DAD_LO:
416 value = DSDMAWriteDAD(&ds->ds9, 1, value);
417 break;
418 case DS_REG_DMA2DAD_LO:
419 value = DSDMAWriteDAD(&ds->ds9, 2, value);
420 break;
421 case DS_REG_DMA3DAD_LO:
422 value = DSDMAWriteDAD(&ds->ds9, 3, value);
423 break;
424
425 case DS_REG_DMA0CNT_LO:
426 DS9DMAWriteCNT(&ds->ds9, 0, value);
427 break;
428 case DS_REG_DMA1CNT_LO:
429 DS9DMAWriteCNT(&ds->ds9, 1, value);
430 break;
431 case DS_REG_DMA2CNT_LO:
432 DS9DMAWriteCNT(&ds->ds9, 2, value);
433 break;
434 case DS_REG_DMA3CNT_LO:
435 DS9DMAWriteCNT(&ds->ds9, 3, value);
436 break;
437
438 case DS_REG_IPCFIFOSEND_LO:
439 DSIPCWriteFIFO(&ds->ds9, value);
440 break;
441 case DS_REG_IE_LO:
442 DSWriteIE(ds->ds9.cpu, ds->ds9.memory.io, value);
443 break;
444 default:
445 DS9IOWrite(ds, address, value & 0xFFFF);
446 DS9IOWrite(ds, address | 2, value >> 16);
447 return;
448 }
449 ds->ds9.memory.io[address >> 1] = value;
450 ds->ds9.memory.io[(address >> 1) + 1] = value >> 16;
451}
452
453uint16_t DS9IORead(struct DS* ds, uint32_t address) {
454 switch (address) {
455 case DS_REG_TM0CNT_LO:
456 case DS_REG_TM1CNT_LO:
457 case DS_REG_TM2CNT_LO:
458 case DS_REG_TM3CNT_LO:
459 DSIOUpdateTimer(&ds->ds9, address);
460 break;
461 case DS_REG_KEYINPUT:
462 return DSIOReadKeyInput(ds);
463 case DS_REG_DMA0FILL_LO:
464 case DS_REG_DMA0FILL_HI:
465 case DS_REG_DMA1FILL_LO:
466 case DS_REG_DMA1FILL_HI:
467 case DS_REG_DMA2FILL_LO:
468 case DS_REG_DMA2FILL_HI:
469 case DS_REG_DMA3FILL_LO:
470 case DS_REG_DMA3FILL_HI:
471 case DS_REG_TM0CNT_HI:
472 case DS_REG_TM1CNT_HI:
473 case DS_REG_TM2CNT_HI:
474 case DS_REG_TM3CNT_HI:
475 case DS_REG_IPCSYNC:
476 case DS_REG_IPCFIFOCNT:
477 case DS_REG_IME:
478 case 0x20A:
479 case DS_REG_IE_LO:
480 case DS_REG_IE_HI:
481 case DS_REG_IF_LO:
482 case DS_REG_IF_HI:
483 case DS9_REG_DIVCNT:
484 case DS9_REG_DIV_NUMER_0:
485 case DS9_REG_DIV_NUMER_1:
486 case DS9_REG_DIV_NUMER_2:
487 case DS9_REG_DIV_NUMER_3:
488 case DS9_REG_DIV_DENOM_0:
489 case DS9_REG_DIV_DENOM_1:
490 case DS9_REG_DIV_DENOM_2:
491 case DS9_REG_DIV_DENOM_3:
492 case DS9_REG_DIV_RESULT_0:
493 case DS9_REG_DIV_RESULT_1:
494 case DS9_REG_DIV_RESULT_2:
495 case DS9_REG_DIV_RESULT_3:
496 case DS9_REG_DIVREM_RESULT_0:
497 case DS9_REG_DIVREM_RESULT_1:
498 case DS9_REG_DIVREM_RESULT_2:
499 case DS9_REG_DIVREM_RESULT_3:
500 case DS9_REG_SQRTCNT:
501 case DS9_REG_SQRT_PARAM_0:
502 case DS9_REG_SQRT_PARAM_1:
503 case DS9_REG_SQRT_PARAM_2:
504 case DS9_REG_SQRT_PARAM_3:
505 case DS9_REG_SQRT_RESULT_LO:
506 case DS9_REG_SQRT_RESULT_HI:
507 // Handled transparently by the registers
508 break;
509 default:
510 mLOG(DS_IO, STUB, "Stub DS9 I/O register read: %06X", address);
511 }
512 if (address < DS9_REG_MAX) {
513 return ds->ds9.memory.io[address >> 1];
514 }
515 return 0;
516}
517
518uint32_t DS9IORead32(struct DS* ds, uint32_t address) {
519 switch (address) {
520 case DS_REG_IPCFIFORECV_LO:
521 return DSIPCReadFIFO(&ds->ds9);
522 default:
523 return DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
524 }
525}