src/gba.c (view raw)
1#include "gba.h"
2
3#include <sys/mman.h>
4#include <unistd.h>
5
6static const char* GBA_CANNOT_MMAP = "Could not map memory";
7
8void GBAInit(struct GBA* gba) {
9 gba->errno = GBA_NO_ERROR;
10 gba->errstr = 0;
11
12 ARMInit(&gba->cpu);
13
14 gba->memory.p = gba;
15 GBAMemoryInit(&gba->memory);
16 ARMAssociateMemory(&gba->cpu, &gba->memory.d);
17}
18
19void GBADeinit(struct GBA* gba) {
20 GBAMemoryDeinit(&gba->memory);
21}
22
23void GBAMemoryInit(struct GBAMemory* memory) {
24 memory->d.load32 = GBALoad32;
25 memory->d.load16 = GBALoad16;
26 memory->d.loadU16 = GBALoadU16;
27 memory->d.load8 = GBALoad8;
28 memory->d.loadU8 = GBALoadU8;
29 memory->d.store32 = GBAStore32;
30 memory->d.store16 = GBAStore16;
31 memory->d.store8 = GBAStore8;
32
33 memory->bios = 0;
34 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->rom = 0;
37
38 if (!memory->wram || !memory->iwram) {
39 GBAMemoryDeinit(memory);
40 memory->p->errno = GBA_OUT_OF_MEMORY;
41 memory->p->errstr = GBA_CANNOT_MMAP;
42 }
43}
44
45void GBAMemoryDeinit(struct GBAMemory* memory) {
46 munmap(memory->wram, SIZE_WORKING_RAM);
47 munmap(memory->iwram, SIZE_WORKING_IRAM);
48}
49
50void GBALoadROM(struct GBA* gba, int fd) {
51 gba->memory.rom = mmap(0, SIZE_CART0, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_FILE, fd, 0);
52 // TODO: error check
53}
54
55int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
56 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
57
58 switch (address & ~OFFSET_MASK) {
59 case BASE_BIOS:
60 break;
61 case BASE_WORKING_RAM:
62 break;
63 case BASE_WORKING_IRAM:
64 break;
65 case BASE_IO:
66 break;
67 case BASE_PALETTE_RAM:
68 break;
69 case BASE_VRAM:
70 break;
71 case BASE_OAM:
72 break;
73 case BASE_CART0:
74 case BASE_CART0_EX:
75 case BASE_CART1:
76 case BASE_CART1_EX:
77 case BASE_CART2:
78 case BASE_CART2_EX:
79 return gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
80 case BASE_CART_SRAM:
81 break;
82 default:
83 break;
84 }
85
86 return 0;
87}
88
89int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
90 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
91
92 switch (address & ~OFFSET_MASK) {
93 case BASE_BIOS:
94 break;
95 case BASE_WORKING_RAM:
96 break;
97 case BASE_WORKING_IRAM:
98 break;
99 case BASE_IO:
100 break;
101 case BASE_PALETTE_RAM:
102 break;
103 case BASE_VRAM:
104 break;
105 case BASE_OAM:
106 break;
107 case BASE_CART0:
108 case BASE_CART0_EX:
109 case BASE_CART1:
110 case BASE_CART1_EX:
111 case BASE_CART2:
112 case BASE_CART2_EX:
113 break;
114 case BASE_CART_SRAM:
115 break;
116 default:
117 break;
118 }
119
120 return 0;
121}
122
123uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
124 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
125
126 switch (address & ~OFFSET_MASK) {
127 case BASE_BIOS:
128 break;
129 case BASE_WORKING_RAM:
130 break;
131 case BASE_WORKING_IRAM:
132 break;
133 case BASE_IO:
134 break;
135 case BASE_PALETTE_RAM:
136 break;
137 case BASE_VRAM:
138 break;
139 case BASE_OAM:
140 break;
141 case BASE_CART0:
142 case BASE_CART0_EX:
143 case BASE_CART1:
144 case BASE_CART1_EX:
145 case BASE_CART2:
146 case BASE_CART2_EX:
147 break;
148 case BASE_CART_SRAM:
149 break;
150 default:
151 break;
152 }
153
154 return 0;
155}
156
157int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
158 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
159
160 switch (address & ~OFFSET_MASK) {
161 case BASE_BIOS:
162 break;
163 case BASE_WORKING_RAM:
164 break;
165 case BASE_WORKING_IRAM:
166 break;
167 case BASE_IO:
168 break;
169 case BASE_PALETTE_RAM:
170 break;
171 case BASE_VRAM:
172 break;
173 case BASE_OAM:
174 break;
175 case BASE_CART0:
176 case BASE_CART0_EX:
177 case BASE_CART1:
178 case BASE_CART1_EX:
179 case BASE_CART2:
180 case BASE_CART2_EX:
181 break;
182 case BASE_CART_SRAM:
183 break;
184 default:
185 break;
186 }
187
188 return 0;
189}
190
191uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
192 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
193
194 switch (address & ~OFFSET_MASK) {
195 case BASE_BIOS:
196 break;
197 case BASE_WORKING_RAM:
198 break;
199 case BASE_WORKING_IRAM:
200 break;
201 case BASE_IO:
202 break;
203 case BASE_PALETTE_RAM:
204 break;
205 case BASE_VRAM:
206 break;
207 case BASE_OAM:
208 break;
209 case BASE_CART0:
210 case BASE_CART0_EX:
211 case BASE_CART1:
212 case BASE_CART1_EX:
213 case BASE_CART2:
214 case BASE_CART2_EX:
215 break;
216 case BASE_CART_SRAM:
217 break;
218 default:
219 break;
220 }
221
222 return 0;
223}
224
225void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
226 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
227
228 switch (address & ~OFFSET_MASK) {
229 case BASE_WORKING_RAM:
230 break;
231 case BASE_WORKING_IRAM:
232 break;
233 case BASE_IO:
234 break;
235 case BASE_PALETTE_RAM:
236 break;
237 case BASE_VRAM:
238 break;
239 case BASE_OAM:
240 break;
241 case BASE_CART0:
242 break;
243 case BASE_CART2_EX:
244 break;
245 case BASE_CART_SRAM:
246 break;
247 default:
248 break;
249 }
250}
251
252void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
253 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
254
255 switch (address & ~OFFSET_MASK) {
256 case BASE_WORKING_RAM:
257 break;
258 case BASE_WORKING_IRAM:
259 break;
260 case BASE_IO:
261 break;
262 case BASE_PALETTE_RAM:
263 break;
264 case BASE_VRAM:
265 break;
266 case BASE_OAM:
267 break;
268 case BASE_CART0:
269 break;
270 case BASE_CART2_EX:
271 break;
272 case BASE_CART_SRAM:
273 break;
274 default:
275 break;
276 }
277}
278
279void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
280 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
281
282 switch (address & ~OFFSET_MASK) {
283 case BASE_WORKING_RAM:
284 break;
285 case BASE_WORKING_IRAM:
286 break;
287 case BASE_IO:
288 break;
289 case BASE_PALETTE_RAM:
290 break;
291 case BASE_VRAM:
292 break;
293 case BASE_OAM:
294 break;
295 case BASE_CART0:
296 break;
297 case BASE_CART2_EX:
298 break;
299 case BASE_CART_SRAM:
300 break;
301 default:
302 break;
303 }
304}