include/mgba/internal/gba/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GBA_SERIALIZE_H
7#define GBA_SERIALIZE_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/core.h>
14#include <mgba/internal/gba/gba.h>
15#include <mgba/internal/gb/serialize.h>
16
17extern const uint32_t GBA_SAVESTATE_MAGIC;
18extern const uint32_t GBA_SAVESTATE_VERSION;
19
20mLOG_DECLARE_CATEGORY(GBA_STATE);
21
22/* Savestate format:
23 * 0x00000 - 0x00003: Version Magic (0x01000001)
24 * 0x00004 - 0x00007: BIOS checksum (e.g. 0xBAAE187F for official BIOS)
25 * 0x00008 - 0x0000B: ROM CRC32
26 * 0x0000C - 0x0000F: Master cycles
27 * 0x00010 - 0x0001B: Game title (e.g. METROID4USA)
28 * 0x0001C - 0x0001F: Game code (e.g. AMTE)
29 * 0x00020 - 0x0012F: CPU state:
30 * | 0x00020 - 0x0005F: GPRs
31 * | 0x00060 - 0x00063: CPSR
32 * | 0x00064 - 0x00067: SPSR
33 * | 0x00068 - 0x0006B: Cycles since last event
34 * | 0x0006C - 0x0006F: Cycles until next event
35 * | 0x00070 - 0x00117: Banked registers
36 * | 0x00118 - 0x0012F: Banked SPSRs
37 * 0x00130 - 0x00143: Audio channel 1/framer state
38 * | 0x00130 - 0x00133: Envelepe timing
39 * | bits 0 - 6: Remaining length
40 * | bits 7 - 9: Next step
41 * | bits 10 - 20: Shadow frequency register
42 * | bits 21 - 31: Reserved
43 * | 0x00134 - 0x00137: Next frame
44 * | 0x00138 - 0x0013B: Next channel 3 fade
45 * | 0x0013C - 0x0013F: Sweep state
46 * | bits 0 - 2: Timesteps
47 * | bits 3 - 7: Reserved
48 * | 0x00140 - 0x00143: Next event
49 * 0x00144 - 0x00153: Audio channel 2 state
50 * | 0x00144 - 0x00147: Envelepe timing
51 * | bits 0 - 2: Remaining length
52 * | bits 3 - 5: Next step
53 * | bits 6 - 31: Reserved
54 * | 0x00148 - 0x0014F: Reserved
55 * | 0x00150 - 0x00153: Next event
56 * 0x00154 - 0x0017B: Audio channel 3 state
57 * | 0x00154 - 0x00173: Wave banks
58 * | 0x00174 - 0x00175: Remaining length
59 * | 0x00176 - 0x00177: Reserved
60 * | 0x00178 - 0x0017B: Next event
61 * 0x0017C - 0x0018B: Audio channel 4 state
62 * | 0x0017C - 0x0017F: Linear feedback shift register state
63 * | 0x00180 - 0x00183: Envelepe timing
64 * | bits 0 - 2: Remaining length
65 * | bits 3 - 5: Next step
66 * | bits 6 - 31: Reserved
67 * | 0x00184 - 0x00187: Last event
68 * | 0x00188 - 0x0018B: Next event
69 * 0x0018C - 0x001AB: Audio FIFO 1
70 * 0x001AC - 0x001CB: Audio FIFO 2
71 * 0x001CC - 0x001DF: Audio miscellaneous state
72 * | 0x001CC - 0x001CF: FIFO 1 size
73 * | 0x001D0 - 0x001D3: Reserved
74 * | 0x001D4 - 0x001D7: Next sample
75 * | 0x001D8 - 0x001DB: FIFO 2 size
76 * | TODO: Fix this, they're in big-endian order, but field is little-endian
77 * | 0x001DC - 0x001DC: Channel 1 envelope state
78 * | bits 0 - 3: Current volume
79 * | bits 4 - 5: Is dead?
80 * | bit 6: Is high?
81* | bit 7: Reserved
82 * | 0x001DD - 0x001DD: Channel 2 envelope state
83 * | bits 0 - 3: Current volume
84 * | bits 4 - 5: Is dead?
85 * | bit 6: Is high?
86* | bit 7: Reserved
87 * | 0x001DE - 0x001DE: Channel 4 envelope state
88 * | bits 0 - 3: Current volume
89 * | bits 4 - 5: Is dead?
90 * | bits 6 - 7: Current frame (continued)
91 * | 0x001DF - 0x001DF: Miscellaneous audio flags
92 * | bit 0: Current frame (continuation)
93 * | bit 1: Is channel 1 sweep enabled?
94 * | bit 2: Has channel 1 sweep occurred?
95 * | bit 3: Is channel 3's memory readable?
96 * | bit 4: Skip frame
97 * | bits 5 - 7: Reserved
98 * 0x001E0 - 0x001FF: Video miscellaneous state
99 * | 0x001E0 - 0x001E3: Next event
100 * | 0x001E4 - 0x001F7: Reserved
101 * | 0x001F8 - 0x001FB: Miscellaneous flags
102 * | 0x001FC - 0x001FF: Frame counter
103 * 0x00200 - 0x00213: Timer 0
104 * | 0x00200 - 0x00201: Reload value
105 * | 0x00202 - 0x00203: Old reload value
106 * | 0x00204 - 0x00207: Last event
107 * | 0x00208 - 0x0020B: Next event
108 * | 0x0020C - 0x0020F: Reserved
109 * | 0x00210 - 0x00213: Miscellaneous flags
110 * 0x00214 - 0x00227: Timer 1
111 * | 0x00214 - 0x00215: Reload value
112 * | 0x00216 - 0x00217: Old reload value
113 * | 0x00218 - 0x0021B: Last event
114 * | 0x0021C - 0x0021F: Next event
115 * | 0x00220 - 0x00223: Reserved
116 * | 0x00224 - 0x00227: Miscellaneous flags
117 * 0x00228 - 0x0023B: Timer 2
118 * | 0x00228 - 0x00229: Reload value
119 * | 0x0022A - 0x0022B: Old reload value
120 * | 0x0022C - 0x0022F: Last event
121 * | 0x00230 - 0x00233: Next event
122 * | 0x00234 - 0x00237: Reserved
123 * | 0x00238 - 0x0023B: Miscellaneous flags
124 * 0x0023C - 0x00250: Timer 3
125 * | 0x0023C - 0x0023D: Reload value
126 * | 0x0023E - 0x0023F: Old reload value
127 * | 0x00240 - 0x00243: Last event
128 * | 0x00244 - 0x00247: Next event
129 * | 0x00248 - 0x0024B: Reserved
130 * | 0x0024C - 0x0024F: Miscellaneous flags
131 * 0x00250 - 0x0025F: DMA 0
132 * | 0x00250 - 0x00253: DMA next source
133 * | 0x00254 - 0x00257: DMA next destination
134 * | 0x00258 - 0x0025B: DMA next count
135 * | 0x0025C - 0x0025F: DMA next event
136 * 0x00260 - 0x0026F: DMA 1
137 * | 0x00260 - 0x00263: DMA next source
138 * | 0x00264 - 0x00267: DMA next destination
139 * | 0x00268 - 0x0026B: DMA next count
140 * | 0x0026C - 0x0026F: DMA next event
141 * 0x00270 - 0x0027F: DMA 2
142 * | 0x00270 - 0x00273: DMA next source
143 * | 0x00274 - 0x00277: DMA next destination
144 * | 0x00278 - 0x0027B: DMA next count
145 * | 0x0027C - 0x0027F: DMA next event
146 * 0x00280 - 0x0028F: DMA 3
147 * | 0x00280 - 0x00283: DMA next source
148 * | 0x00284 - 0x00287: DMA next destination
149 * | 0x00288 - 0x0028B: DMA next count
150 * | 0x0028C - 0x0028F: DMA next event
151 * 0x00290 - 0x002C3: GPIO state
152 * | 0x00290 - 0x00291: Pin state
153 * | 0x00292 - 0x00293: Direction state
154 * | 0x00294 - 0x002B6: RTC state (see hardware.h for format)
155 * | 0x002B7 - 0x002B7: GPIO devices
156 * | bit 0: Has RTC values
157 * | bit 1: Has rumble value (reserved)
158 * | bit 2: Has light sensor value
159 * | bit 3: Has gyroscope value
160 * | bit 4: Has tilt values
161 * | bit 5: Has Game Boy Player attached
162 * | bits 6 - 7: Reserved
163 * | 0x002B8 - 0x002B9: Gyroscope sample
164 * | 0x002BA - 0x002BB: Tilt x sample
165 * | 0x002BC - 0x002BD: Tilt y sample
166 * | 0x002BE - 0x002BF: Flags
167 * | bit 0: Is read enabled
168 * | bit 1: Gyroscope sample is edge
169 * | bit 2: Light sample is edge
170 * | bit 3: Reserved
171 * | bits 4 - 15: Light counter
172 * | 0x002C0 - 0x002C0: Light sample
173 * | 0x002C1 - 0x002C3: Flags
174 * | bits 0 - 1: Tilt state machine
175 * | bits 2 - 3: GB Player inputs posted
176 * | bits 4 - 8: GB Player transmit position
177 * | bits 9 - 23: Reserved
178 * 0x002C4 - 0x002C7: Game Boy Player next event
179 * 0x002C8 - 0x002CB: Current DMA transfer word
180 * 0x002CC - 0x002CF: Last DMA transfer PC
181 * 0x002D0 - 0x002DF: Reserved (leave zero)
182 * 0x002E0 - 0x002EF: Savedata state
183 * | 0x002E0 - 0x002E0: Savedata type
184 * | 0x002E1 - 0x002E1: Savedata command (see savedata.h)
185 * | 0x002E2 - 0x002E2: Flags
186 * | bits 0 - 1: Flash state machine
187 * | bits 2 - 3: Reserved
188 * | bit 4: Flash bank
189 * | bit 5: Is settling occurring?
190 * | bits 6 - 7: Reserved
191 * | 0x002E3 - 0x002E3: EEPROM read bits remaining
192 * | 0x002E4 - 0x002E7: Settling cycles remaining
193 * | 0x002E8 - 0x002EB: EEPROM read address
194 * | 0x002EC - 0x002EF: EEPROM write address
195 * | 0x002F0 - 0x002F1: Flash settling sector
196 * | 0x002F2 - 0x002F3: Reserved
197 * 0x002F4 - 0x002FF: Prefetch
198 * | 0x002F4 - 0x002F7: GBA BIOS bus prefetch
199 * | 0x002F8 - 0x002FB: CPU prefecth (decode slot)
200 * | 0x002FC - 0x002FF: CPU prefetch (fetch slot)
201 * 0x00300 - 0x0030F: Reserved (leave zero)
202 * 0x00310 - 0x00317: Global cycle counter
203 * 0x00318 - 0x0031B: Last prefetched program counter
204 * 0x0031C - 0x0031F: Miscellaneous flags
205 * | bit 0: Is CPU halted?
206 * | bit 1: POSTFLG
207 * | bit 2: Is IRQ pending?
208 * 0x00320 - 0x00323: Next IRQ event
209 * 0x00324 - 0x00327: Interruptable BIOS stall cycles
210 * 0x00328 - 0x003FF: Reserved (leave zero)
211 * 0x00400 - 0x007FF: I/O memory
212 * 0x00800 - 0x00BFF: Palette
213 * 0x00C00 - 0x00FFF: OAM
214 * 0x01000 - 0x18FFF: VRAM
215 * 0x19000 - 0x20FFF: IWRAM
216 * 0x21000 - 0x60FFF: WRAM
217 * Total size: 0x61000 (397,312) bytes
218 */
219
220DECL_BITFIELD(GBASerializedVideoFlags, uint32_t);
221DECL_BITS(GBASerializedVideoFlags, Mode, 0, 2);
222
223DECL_BITFIELD(GBASerializedHWFlags1, uint16_t);
224DECL_BIT(GBASerializedHWFlags1, ReadWrite, 0);
225DECL_BIT(GBASerializedHWFlags1, GyroEdge, 1);
226DECL_BIT(GBASerializedHWFlags1, LightEdge, 2);
227DECL_BITS(GBASerializedHWFlags1, LightCounter, 4, 12);
228
229DECL_BITFIELD(GBASerializedHWFlags2, uint8_t);
230DECL_BITS(GBASerializedHWFlags2, TiltState, 0, 2);
231DECL_BITS(GBASerializedHWFlags2, GbpInputsPosted, 2, 2);
232DECL_BITS(GBASerializedHWFlags2, GbpTxPosition, 4, 5);
233
234DECL_BITFIELD(GBASerializedHWFlags3, uint16_t);
235
236DECL_BITFIELD(GBASerializedSavedataFlags, uint8_t);
237DECL_BITS(GBASerializedSavedataFlags, FlashState, 0, 2);
238DECL_BIT(GBASerializedSavedataFlags, FlashBank, 4);
239DECL_BIT(GBASerializedSavedataFlags, DustSettling, 5);
240
241DECL_BITFIELD(GBASerializedMiscFlags, uint32_t);
242DECL_BIT(GBASerializedMiscFlags, Halted, 0);
243DECL_BIT(GBASerializedMiscFlags, POSTFLG, 1);
244DECL_BIT(GBASerializedMiscFlags, IrqPending, 2);
245DECL_BIT(GBASerializedMiscFlags, Blocked, 3);
246
247struct GBASerializedState {
248 uint32_t versionMagic;
249 uint32_t biosChecksum;
250 uint32_t romCrc32;
251 uint32_t masterCycles;
252
253 char title[12];
254 uint32_t id;
255
256 struct {
257 int32_t gprs[16];
258 union PSR cpsr;
259 union PSR spsr;
260
261 int32_t cycles;
262 int32_t nextEvent;
263
264 int32_t bankedRegisters[6][7];
265 int32_t bankedSPSRs[6];
266 } cpu;
267
268 struct {
269 struct GBSerializedPSGState psg;
270 uint8_t fifoA[32];
271 uint8_t fifoB[32];
272 uint32_t fifoSizeA;
273 int32_t reserved;
274 int32_t nextSample;
275 uint32_t fifoSizeB;
276 GBSerializedAudioFlags flags;
277 } audio;
278
279 struct {
280 int32_t nextEvent;
281 int32_t reserved[5];
282 GBASerializedVideoFlags flags;
283 int32_t frameCounter;
284 } video;
285
286 struct {
287 uint16_t reload;
288 uint16_t reserved0;
289 uint32_t lastEvent;
290 uint32_t nextEvent;
291 uint32_t reserved1;
292 GBATimerFlags flags;
293 } timers[4];
294
295 struct {
296 uint32_t nextSource;
297 uint32_t nextDest;
298 int32_t nextCount;
299 int32_t when;
300 } dma[4];
301
302 struct {
303 uint16_t pinState;
304 uint16_t pinDirection;
305 struct GBARTC rtc;
306 uint8_t devices;
307 uint16_t gyroSample;
308 uint16_t tiltSampleX;
309 uint16_t tiltSampleY;
310 GBASerializedHWFlags1 flags1;
311 uint8_t lightSample;
312 GBASerializedHWFlags2 flags2;
313 GBASerializedHWFlags3 flags3;
314 uint32_t gbpNextEvent;
315 } hw;
316
317 uint32_t dmaTransferRegister;
318 uint32_t dmaBlockPC;
319
320 uint32_t reservedHardware[4];
321
322 struct {
323 uint8_t type;
324 uint8_t command;
325 GBASerializedSavedataFlags flags;
326 int8_t readBitsRemaining;
327 uint32_t settlingDust;
328 uint32_t readAddress;
329 uint32_t writeAddress;
330 uint16_t settlingSector;
331 uint16_t reserved;
332 } savedata;
333
334 uint32_t biosPrefetch;
335 uint32_t cpuPrefetch[2];
336
337 uint32_t reservedCpu[4];
338
339 uint64_t globalCycles;
340 uint32_t lastPrefetchedPc;
341 GBASerializedMiscFlags miscFlags;
342 uint32_t nextIrq;
343 int32_t biosStall;
344
345 uint32_t reserved[54];
346
347 uint16_t io[SIZE_IO >> 1];
348 uint16_t pram[SIZE_PALETTE_RAM >> 1];
349 uint16_t oam[SIZE_OAM >> 1];
350 uint16_t vram[SIZE_VRAM >> 1];
351 uint8_t iwram[SIZE_WORKING_IRAM];
352 uint8_t wram[SIZE_WORKING_RAM];
353};
354
355struct VDir;
356
357void GBASerialize(struct GBA* gba, struct GBASerializedState* state);
358bool GBADeserialize(struct GBA* gba, const struct GBASerializedState* state);
359
360CXX_GUARD_END
361
362#endif