src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39
40static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
43static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
44
45static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
46
47static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
48static void _GBPocketCamCapture(struct GBMemory*);
49
50void GBMBCSwitchBank(struct GB* gb, int bank) {
51 size_t bankStart = bank * GB_SIZE_CART_BANK0;
52 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
53 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
54 bankStart &= (gb->memory.romSize - 1);
55 bank = bankStart / GB_SIZE_CART_BANK0;
56 }
57 gb->memory.romBank = &gb->memory.rom[bankStart];
58 gb->memory.currentBank = bank;
59 if (gb->cpu->pc < GB_BASE_VRAM) {
60 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
61 }
62}
63
64void GBMBCSwitchBank0(struct GB* gb, int bank) {
65 size_t bankStart = bank * GB_SIZE_CART_BANK0;
66 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
67 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
68 bankStart &= (gb->memory.romSize - 1);
69 }
70 gb->memory.romBase = &gb->memory.rom[bankStart];
71 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
72 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
73 }
74}
75
76void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
77 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
78 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
79 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
80 bankStart &= (gb->memory.romSize - 1);
81 bank = bankStart / GB_SIZE_CART_HALFBANK;
82 if (!bank) {
83 ++bank;
84 }
85 }
86 if (!half) {
87 gb->memory.romBank = &gb->memory.rom[bankStart];
88 gb->memory.currentBank = bank;
89 } else {
90 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
91 gb->memory.mbcState.mbc6.currentBank1 = bank;
92 }
93 if (gb->cpu->pc < GB_BASE_VRAM) {
94 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
95 }
96}
97
98static bool _isMulticart(const uint8_t* mem) {
99 bool success;
100 struct VFile* vf;
101
102 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
103 success = GBIsROM(vf);
104 vf->close(vf);
105
106 if (!success) {
107 return false;
108 }
109
110 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
111 success = GBIsROM(vf);
112 vf->close(vf);
113
114 if (!success) {
115 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
116 success = GBIsROM(vf);
117 vf->close(vf);
118 }
119
120 return success;
121}
122
123static bool _isWisdomTree(const uint8_t* mem, size_t size) {
124 size_t i;
125 for (i = 0x134; i < 0x14C; i += 4) {
126 if (*(uint32_t*) &mem[i] != 0) {
127 return false;
128 }
129 }
130 for (i = 0xF0; i < 0x100; i += 4) {
131 if (*(uint32_t*) &mem[i] != 0) {
132 return false;
133 }
134 }
135 if (mem[0x14D] != 0xE7) {
136 return false;
137 }
138 for (i = 0x300; i < size - 11; ++i) {
139 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
140 return true;
141 }
142 }
143 return false;
144}
145
146void GBMBCSwitchSramBank(struct GB* gb, int bank) {
147 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
148 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
149 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
150 bankStart &= (gb->sramSize - 1);
151 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
152 }
153 gb->memory.sramBank = &gb->memory.sram[bankStart];
154 gb->memory.sramCurrentBank = bank;
155}
156
157void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
158 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
159 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
160 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
161 bankStart &= (gb->sramSize - 1);
162 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
163 }
164 if (!half) {
165 gb->memory.sramBank = &gb->memory.sram[bankStart];
166 gb->memory.sramCurrentBank = bank;
167 } else {
168 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
169 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
170 }
171}
172
173void GBMBCInit(struct GB* gb) {
174 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
175 if (gb->memory.rom) {
176 if (gb->memory.romSize >= 0x8000) {
177 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
178 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
179 cart = cartFooter;
180 }
181 }
182 switch (cart->ramSize) {
183 case 0:
184 gb->sramSize = 0;
185 break;
186 case 1:
187 gb->sramSize = 0x800;
188 break;
189 default:
190 case 2:
191 gb->sramSize = 0x2000;
192 break;
193 case 3:
194 gb->sramSize = 0x8000;
195 break;
196 case 4:
197 gb->sramSize = 0x20000;
198 break;
199 case 5:
200 gb->sramSize = 0x10000;
201 break;
202 }
203
204 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
205 switch (cart->type) {
206 case 0:
207 if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) {
208 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
209 break;
210 }
211 // Fall through
212 case 8:
213 case 9:
214 gb->memory.mbcType = GB_MBC_NONE;
215 break;
216 case 1:
217 case 2:
218 case 3:
219 gb->memory.mbcType = GB_MBC1;
220 break;
221 case 5:
222 case 6:
223 gb->memory.mbcType = GB_MBC2;
224 break;
225 case 0x0B:
226 case 0x0C:
227 case 0x0D:
228 gb->memory.mbcType = GB_MMM01;
229 break;
230 case 0x0F:
231 case 0x10:
232 gb->memory.mbcType = GB_MBC3_RTC;
233 break;
234 case 0x11:
235 case 0x12:
236 case 0x13:
237 gb->memory.mbcType = GB_MBC3;
238 break;
239 default:
240 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
241 // Fall through
242 case 0x19:
243 case 0x1A:
244 case 0x1B:
245 gb->memory.mbcType = GB_MBC5;
246 break;
247 case 0x1C:
248 case 0x1D:
249 case 0x1E:
250 gb->memory.mbcType = GB_MBC5_RUMBLE;
251 break;
252 case 0x20:
253 gb->memory.mbcType = GB_MBC6;
254 break;
255 case 0x22:
256 gb->memory.mbcType = GB_MBC7;
257 break;
258 case 0xFC:
259 gb->memory.mbcType = GB_POCKETCAM;
260 break;
261 case 0xFD:
262 gb->memory.mbcType = GB_TAMA5;
263 break;
264 case 0xFE:
265 gb->memory.mbcType = GB_HuC3;
266 break;
267 case 0xFF:
268 gb->memory.mbcType = GB_HuC1;
269 break;
270 }
271 }
272 } else {
273 gb->memory.mbcType = GB_MBC_NONE;
274 }
275 gb->memory.mbcRead = NULL;
276 switch (gb->memory.mbcType) {
277 case GB_MBC_NONE:
278 gb->memory.mbcWrite = _GBMBCNone;
279 break;
280 case GB_MBC1:
281 gb->memory.mbcWrite = _GBMBC1;
282 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
283 gb->memory.mbcState.mbc1.multicartStride = 4;
284 } else {
285 gb->memory.mbcState.mbc1.multicartStride = 5;
286 }
287 break;
288 case GB_MBC2:
289 gb->memory.mbcWrite = _GBMBC2;
290 gb->memory.mbcRead = _GBMBC2Read;
291 gb->sramSize = 0x100;
292 break;
293 case GB_MBC3:
294 gb->memory.mbcWrite = _GBMBC3;
295 break;
296 default:
297 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
298 // Fall through
299 case GB_MBC5:
300 gb->memory.mbcWrite = _GBMBC5;
301 break;
302 case GB_MBC6:
303 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
304 gb->memory.mbcWrite = _GBMBC6;
305 gb->memory.mbcRead = _GBMBC6Read;
306 break;
307 case GB_MBC7:
308 gb->memory.mbcWrite = _GBMBC7;
309 gb->memory.mbcRead = _GBMBC7Read;
310 gb->sramSize = 0x100;
311 break;
312 case GB_MMM01:
313 gb->memory.mbcWrite = _GBMMM01;
314 break;
315 case GB_HuC1:
316 gb->memory.mbcWrite = _GBHuC1;
317 break;
318 case GB_HuC3:
319 gb->memory.mbcWrite = _GBHuC3;
320 break;
321 case GB_TAMA5:
322 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
323 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
324 gb->memory.mbcWrite = _GBTAMA5;
325 gb->memory.mbcRead = _GBTAMA5Read;
326 gb->sramSize = 0x20;
327 break;
328 case GB_MBC3_RTC:
329 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
330 gb->memory.mbcWrite = _GBMBC3;
331 break;
332 case GB_MBC5_RUMBLE:
333 gb->memory.mbcWrite = _GBMBC5;
334 break;
335 case GB_POCKETCAM:
336 gb->memory.mbcWrite = _GBPocketCam;
337 gb->memory.mbcRead = _GBPocketCamRead;
338 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
339 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
340 }
341 break;
342 case GB_UNL_WISDOM_TREE:
343 gb->memory.mbcWrite = _GBWisdomTree;
344 break;
345 }
346
347 gb->memory.currentBank = 1;
348 gb->memory.sramCurrentBank = 0;
349 gb->memory.sramAccess = false;
350 gb->memory.rtcAccess = false;
351 gb->memory.activeRtcReg = 0;
352 gb->memory.rtcLatched = false;
353 gb->memory.rtcLastLatch = 0;
354 if (gb->memory.rtc) {
355 if (gb->memory.rtc->sample) {
356 gb->memory.rtc->sample(gb->memory.rtc);
357 }
358 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
359 } else {
360 gb->memory.rtcLastLatch = time(0);
361 }
362 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
363
364 GBResizeSram(gb, gb->sramSize);
365
366 if (gb->memory.mbcType == GB_MBC3_RTC) {
367 GBMBCRTCRead(gb);
368 }
369}
370
371static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
372 time_t t;
373 if (rtc) {
374 if (rtc->sample) {
375 rtc->sample(rtc);
376 }
377 t = rtc->unixTime(rtc);
378 } else {
379 t = time(0);
380 }
381 time_t currentLatch = t;
382 t -= *rtcLastLatch;
383 *rtcLastLatch = currentLatch;
384
385 int64_t diff;
386 diff = rtcRegs[0] + t % 60;
387 if (diff < 0) {
388 diff += 60;
389 t -= 60;
390 }
391 rtcRegs[0] = diff % 60;
392 t /= 60;
393 t += diff / 60;
394
395 diff = rtcRegs[1] + t % 60;
396 if (diff < 0) {
397 diff += 60;
398 t -= 60;
399 }
400 rtcRegs[1] = diff % 60;
401 t /= 60;
402 t += diff / 60;
403
404 diff = rtcRegs[2] + t % 24;
405 if (diff < 0) {
406 diff += 24;
407 t -= 24;
408 }
409 rtcRegs[2] = diff % 24;
410 t /= 24;
411 t += diff / 24;
412
413 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
414 rtcRegs[3] = diff;
415 rtcRegs[4] &= 0xFE;
416 rtcRegs[4] |= (diff >> 8) & 1;
417 if (diff & 0x200) {
418 rtcRegs[4] |= 0x80;
419 }
420}
421
422static void _GBMBC1Update(struct GB* gb) {
423 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
424 int bank = state->bankLo;
425 bank &= (1 << state->multicartStride) - 1;
426 bank |= state->bankHi << state->multicartStride;
427 if (state->mode) {
428 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
429 GBMBCSwitchSramBank(gb, state->bankHi & 3);
430 } else {
431 GBMBCSwitchBank0(gb, 0);
432 GBMBCSwitchSramBank(gb, 0);
433 }
434 if (!(state->bankLo & 0x1F)) {
435 ++bank;
436 }
437 GBMBCSwitchBank(gb, bank);
438}
439
440void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
441 struct GBMemory* memory = &gb->memory;
442 int bank = value & 0x1F;
443 switch (address >> 13) {
444 case 0x0:
445 switch (value & 0xF) {
446 case 0:
447 memory->sramAccess = false;
448 break;
449 case 0xA:
450 memory->sramAccess = true;
451 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
452 break;
453 default:
454 // TODO
455 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
456 break;
457 }
458 break;
459 case 0x1:
460 memory->mbcState.mbc1.bankLo = bank;
461 _GBMBC1Update(gb);
462 break;
463 case 0x2:
464 bank &= 3;
465 memory->mbcState.mbc1.bankHi = bank;
466 _GBMBC1Update(gb);
467 break;
468 case 0x3:
469 memory->mbcState.mbc1.mode = value & 1;
470 _GBMBC1Update(gb);
471 break;
472 default:
473 // TODO
474 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
475 break;
476 }
477}
478
479void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
480 struct GBMemory* memory = &gb->memory;
481 int shift = (address & 1) * 4;
482 int bank = value & 0xF;
483 switch ((address & 0xC100) >> 8) {
484 case 0x0:
485 switch (value & 0x0F) {
486 case 0:
487 memory->sramAccess = false;
488 break;
489 case 0xA:
490 memory->sramAccess = true;
491 break;
492 default:
493 // TODO
494 mLOG(GB_MBC, STUB, "MBC2 unknown value %02X", value);
495 break;
496 }
497 break;
498 case 0x1:
499 if (!bank) {
500 ++bank;
501 }
502 GBMBCSwitchBank(gb, bank);
503 break;
504 case 0x80:
505 case 0x81:
506 case 0x82:
507 case 0x83:
508 if (!memory->sramAccess) {
509 return;
510 }
511 address &= 0x1FF;
512 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
513 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
514 break;
515 default:
516 // TODO
517 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
518 break;
519 }
520}
521
522static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
523 if (!memory->sramAccess) {
524 return 0xFF;
525 }
526 address &= 0x1FF;
527 int shift = (address & 1) * 4;
528 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
529}
530
531void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
532 struct GBMemory* memory = &gb->memory;
533 int bank = value;
534 switch (address >> 13) {
535 case 0x0:
536 switch (value) {
537 case 0:
538 memory->sramAccess = false;
539 break;
540 case 0xA:
541 memory->sramAccess = true;
542 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
543 break;
544 default:
545 // TODO
546 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
547 break;
548 }
549 break;
550 case 0x1:
551 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
552 bank &= 0x7F;
553 }
554 if (!bank) {
555 ++bank;
556 }
557 GBMBCSwitchBank(gb, bank);
558 break;
559 case 0x2:
560 if (value < 8) {
561 GBMBCSwitchSramBank(gb, value);
562 memory->rtcAccess = false;
563 } else if (value <= 0xC) {
564 memory->activeRtcReg = value - 8;
565 memory->rtcAccess = true;
566 }
567 break;
568 case 0x3:
569 if (memory->rtcLatched && value == 0) {
570 memory->rtcLatched = false;
571 } else if (!memory->rtcLatched && value == 1) {
572 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
573 memory->rtcLatched = true;
574 }
575 break;
576 }
577}
578
579void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
580 struct GBMemory* memory = &gb->memory;
581 int bank;
582 switch (address >> 12) {
583 case 0x0:
584 case 0x1:
585 switch (value) {
586 case 0:
587 memory->sramAccess = false;
588 break;
589 case 0xA:
590 memory->sramAccess = true;
591 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
592 break;
593 default:
594 // TODO
595 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
596 break;
597 }
598 break;
599 case 0x2:
600 bank = (memory->currentBank & 0x100) | value;
601 GBMBCSwitchBank(gb, bank);
602 break;
603 case 0x3:
604 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
605 GBMBCSwitchBank(gb, bank);
606 break;
607 case 0x4:
608 case 0x5:
609 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
610 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
611 value &= ~8;
612 }
613 GBMBCSwitchSramBank(gb, value & 0xF);
614 break;
615 default:
616 // TODO
617 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
618 break;
619 }
620}
621
622void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
623 struct GBMemory* memory = &gb->memory;
624 int bank = value;
625 switch (address >> 10) {
626 case 0:
627 switch (value) {
628 case 0:
629 memory->mbcState.mbc6.sramAccess = false;
630 break;
631 case 0xA:
632 memory->mbcState.mbc6.sramAccess = true;
633 break;
634 default:
635 // TODO
636 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
637 break;
638 }
639 break;
640 case 0x1:
641 GBMBCSwitchSramHalfBank(gb, 0, bank);
642 break;
643 case 0x2:
644 GBMBCSwitchSramHalfBank(gb, 1, bank);
645 break;
646 case 0x8:
647 case 0x9:
648 GBMBCSwitchHalfBank(gb, 0, bank);
649 break;
650 case 0xC:
651 case 0xD:
652 GBMBCSwitchHalfBank(gb, 1, bank);
653 break;
654 case 0x28:
655 case 0x29:
656 case 0x2A:
657 case 0x2B:
658 if (memory->mbcState.mbc6.sramAccess) {
659 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
660 }
661 break;
662 case 0x2C:
663 case 0x2D:
664 case 0x2E:
665 case 0x2F:
666 if (memory->mbcState.mbc6.sramAccess) {
667 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
668 }
669 break;
670 default:
671 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
672 break;
673 }
674}
675
676uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
677 if (!memory->mbcState.mbc6.sramAccess) {
678 return 0xFF;
679 }
680 switch (address >> 12) {
681 case 0xA:
682 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
683 case 0xB:
684 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
685 }
686 return 0xFF;
687}
688
689void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
690 int bank = value & 0x7F;
691 switch (address >> 13) {
692 case 0x0:
693 switch (value) {
694 default:
695 case 0:
696 gb->memory.mbcState.mbc7.access = 0;
697 break;
698 case 0xA:
699 gb->memory.mbcState.mbc7.access |= 1;
700 break;
701 }
702 break;
703 case 0x1:
704 GBMBCSwitchBank(gb, bank);
705 break;
706 case 0x2:
707 if (value == 0x40) {
708 gb->memory.mbcState.mbc7.access |= 2;
709 } else {
710 gb->memory.mbcState.mbc7.access &= ~2;
711 }
712 break;
713 case 0x5:
714 _GBMBC7Write(&gb->memory, address, value);
715 break;
716 default:
717 // TODO
718 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
719 break;
720 }
721}
722
723uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
724 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
725 if (mbc7->access != 3) {
726 return 0xFF;
727 }
728 switch (address & 0xF0) {
729 case 0x20:
730 if (memory->rotation && memory->rotation->readTiltX) {
731 int32_t x = -memory->rotation->readTiltX(memory->rotation);
732 x >>= 21;
733 x += 0x81D0;
734 return x;
735 }
736 return 0xFF;
737 case 0x30:
738 if (memory->rotation && memory->rotation->readTiltX) {
739 int32_t x = -memory->rotation->readTiltX(memory->rotation);
740 x >>= 21;
741 x += 0x81D0;
742 return x >> 8;
743 }
744 return 7;
745 case 0x40:
746 if (memory->rotation && memory->rotation->readTiltY) {
747 int32_t y = -memory->rotation->readTiltY(memory->rotation);
748 y >>= 21;
749 y += 0x81D0;
750 return y;
751 }
752 return 0xFF;
753 case 0x50:
754 if (memory->rotation && memory->rotation->readTiltY) {
755 int32_t y = -memory->rotation->readTiltY(memory->rotation);
756 y >>= 21;
757 y += 0x81D0;
758 return y >> 8;
759 }
760 return 7;
761 case 0x60:
762 return 0;
763 case 0x80:
764 return mbc7->eeprom;
765 default:
766 return 0xFF;
767 }
768}
769
770static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
771 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
772 if (mbc7->access != 3) {
773 return;
774 }
775 switch (address & 0xF0) {
776 case 0x00:
777 mbc7->latch = (value & 0x55) == 0x55;
778 return;
779 case 0x10:
780 mbc7->latch |= (value & 0xAA);
781 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
782 memory->rotation->sample(memory->rotation);
783 }
784 mbc7->latch = 0;
785 return;
786 default:
787 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
788 return;
789 case 0x80:
790 break;
791 }
792 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
793 value = GBMBC7FieldFillDO(value); // Hi-Z
794 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
795 mbc7->state = GBMBC7_STATE_IDLE;
796 }
797 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
798 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
799 mbc7->sr <<= 1;
800 mbc7->sr |= GBMBC7FieldGetDI(value);
801 ++mbc7->srBits;
802 }
803 switch (mbc7->state) {
804 case GBMBC7_STATE_IDLE:
805 if (GBMBC7FieldIsDI(value)) {
806 mbc7->state = GBMBC7_STATE_READ_COMMAND;
807 mbc7->srBits = 0;
808 mbc7->sr = 0;
809 }
810 break;
811 case GBMBC7_STATE_READ_COMMAND:
812 if (mbc7->srBits == 10) {
813 mbc7->state = 0x10 | (mbc7->sr >> 6);
814 if (mbc7->state & 0xC) {
815 mbc7->state &= ~0x3;
816 }
817 mbc7->srBits = 0;
818 mbc7->address = mbc7->sr & 0x7F;
819 }
820 break;
821 case GBMBC7_STATE_DO:
822 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
823 mbc7->sr <<= 1;
824 --mbc7->srBits;
825 if (!mbc7->srBits) {
826 mbc7->state = GBMBC7_STATE_IDLE;
827 }
828 break;
829 default:
830 break;
831 }
832 switch (mbc7->state) {
833 case GBMBC7_STATE_EEPROM_EWEN:
834 mbc7->writable = true;
835 mbc7->state = GBMBC7_STATE_IDLE;
836 break;
837 case GBMBC7_STATE_EEPROM_EWDS:
838 mbc7->writable = false;
839 mbc7->state = GBMBC7_STATE_IDLE;
840 break;
841 case GBMBC7_STATE_EEPROM_WRITE:
842 if (mbc7->srBits == 16) {
843 if (mbc7->writable) {
844 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
845 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
846 }
847 mbc7->state = GBMBC7_STATE_IDLE;
848 }
849 break;
850 case GBMBC7_STATE_EEPROM_ERASE:
851 if (mbc7->writable) {
852 memory->sram[mbc7->address * 2] = 0xFF;
853 memory->sram[mbc7->address * 2 + 1] = 0xFF;
854 }
855 mbc7->state = GBMBC7_STATE_IDLE;
856 break;
857 case GBMBC7_STATE_EEPROM_READ:
858 mbc7->srBits = 16;
859 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
860 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
861 mbc7->state = GBMBC7_STATE_DO;
862 value = GBMBC7FieldClearDO(value);
863 break;
864 case GBMBC7_STATE_EEPROM_WRAL:
865 if (mbc7->srBits == 16) {
866 if (mbc7->writable) {
867 int i;
868 for (i = 0; i < 128; ++i) {
869 memory->sram[i * 2] = mbc7->sr >> 8;
870 memory->sram[i * 2 + 1] = mbc7->sr;
871 }
872 }
873 mbc7->state = GBMBC7_STATE_IDLE;
874 }
875 break;
876 case GBMBC7_STATE_EEPROM_ERAL:
877 if (mbc7->writable) {
878 int i;
879 for (i = 0; i < 128; ++i) {
880 memory->sram[i * 2] = 0xFF;
881 memory->sram[i * 2 + 1] = 0xFF;
882 }
883 }
884 mbc7->state = GBMBC7_STATE_IDLE;
885 break;
886 default:
887 break;
888 }
889 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
890 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
891 }
892 mbc7->eeprom = value;
893}
894
895void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
896 struct GBMemory* memory = &gb->memory;
897 if (!memory->mbcState.mmm01.locked) {
898 switch (address >> 13) {
899 case 0x0:
900 memory->mbcState.mmm01.locked = true;
901 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
902 break;
903 case 0x1:
904 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
905 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
906 break;
907 case 0x2:
908 memory->mbcState.mmm01.currentBank0 &= ~0x180;
909 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
910 break;
911 default:
912 // TODO
913 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
914 break;
915 }
916 return;
917 }
918 switch (address >> 13) {
919 case 0x0:
920 switch (value) {
921 case 0xA:
922 memory->sramAccess = true;
923 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
924 break;
925 default:
926 memory->sramAccess = false;
927 break;
928 }
929 break;
930 case 0x1:
931 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
932 break;
933 case 0x2:
934 GBMBCSwitchSramBank(gb, value);
935 break;
936 default:
937 // TODO
938 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
939 break;
940 }
941}
942
943void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
944 struct GBMemory* memory = &gb->memory;
945 int bank = value & 0x3F;
946 switch (address >> 13) {
947 case 0x0:
948 switch (value) {
949 case 0xE:
950 memory->sramAccess = false;
951 break;
952 default:
953 memory->sramAccess = true;
954 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
955 break;
956 }
957 break;
958 case 0x1:
959 GBMBCSwitchBank(gb, bank);
960 break;
961 case 0x2:
962 GBMBCSwitchSramBank(gb, value);
963 break;
964 default:
965 // TODO
966 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
967 break;
968 }
969}
970
971void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
972 struct GBMemory* memory = &gb->memory;
973 int bank = value & 0x3F;
974 if (address & 0x1FFF) {
975 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
976 }
977
978 switch (address >> 13) {
979 case 0x0:
980 switch (value) {
981 case 0xA:
982 memory->sramAccess = true;
983 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
984 break;
985 default:
986 memory->sramAccess = false;
987 break;
988 }
989 break;
990 case 0x1:
991 GBMBCSwitchBank(gb, bank);
992 break;
993 case 0x2:
994 GBMBCSwitchSramBank(gb, bank);
995 break;
996 default:
997 // TODO
998 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
999 break;
1000 }
1001}
1002
1003void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
1004 struct GBMemory* memory = &gb->memory;
1005 int bank = value & 0x3F;
1006 switch (address >> 13) {
1007 case 0x0:
1008 switch (value) {
1009 case 0:
1010 memory->sramAccess = false;
1011 break;
1012 case 0xA:
1013 memory->sramAccess = true;
1014 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1015 break;
1016 default:
1017 // TODO
1018 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1019 break;
1020 }
1021 break;
1022 case 0x1:
1023 GBMBCSwitchBank(gb, bank);
1024 break;
1025 case 0x2:
1026 if (value < 0x10) {
1027 GBMBCSwitchSramBank(gb, value);
1028 memory->mbcState.pocketCam.registersActive = false;
1029 } else {
1030 memory->mbcState.pocketCam.registersActive = true;
1031 }
1032 break;
1033 case 0x5:
1034 address &= 0x7F;
1035 if (address == 0 && value & 1) {
1036 value &= 6; // TODO: Timing
1037 _GBPocketCamCapture(memory);
1038 }
1039 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1040 memory->mbcState.pocketCam.registers[address] = value;
1041 }
1042 break;
1043 default:
1044 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1045 break;
1046 }
1047}
1048
1049uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1050 if (memory->mbcState.pocketCam.registersActive) {
1051 if ((address & 0x7F) == 0) {
1052 return memory->mbcState.pocketCam.registers[0];
1053 }
1054 return 0;
1055 }
1056 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1057}
1058
1059void _GBPocketCamCapture(struct GBMemory* memory) {
1060 if (!memory->cam) {
1061 return;
1062 }
1063 const void* image = NULL;
1064 size_t stride;
1065 enum mColorFormat format;
1066 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1067 if (!image) {
1068 return;
1069 }
1070 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1071 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1072 size_t x, y;
1073 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1074 for (x = 0; x < GBCAM_WIDTH; ++x) {
1075 uint32_t gray;
1076 uint32_t color;
1077 switch (format) {
1078 case mCOLOR_XBGR8:
1079 case mCOLOR_XRGB8:
1080 case mCOLOR_ARGB8:
1081 case mCOLOR_ABGR8:
1082 color = ((const uint32_t*) image)[y * stride + x];
1083 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1084 break;
1085 case mCOLOR_BGRX8:
1086 case mCOLOR_RGBX8:
1087 case mCOLOR_RGBA8:
1088 case mCOLOR_BGRA8:
1089 color = ((const uint32_t*) image)[y * stride + x];
1090 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1091 break;
1092 case mCOLOR_BGR5:
1093 case mCOLOR_RGB5:
1094 case mCOLOR_ARGB5:
1095 case mCOLOR_ABGR5:
1096 color = ((const uint16_t*) image)[y * stride + x];
1097 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1098 break;
1099 case mCOLOR_BGR565:
1100 case mCOLOR_RGB565:
1101 color = ((const uint16_t*) image)[y * stride + x];
1102 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1103 break;
1104 case mCOLOR_BGRA5:
1105 case mCOLOR_RGBA5:
1106 color = ((const uint16_t*) image)[y * stride + x];
1107 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1108 break;
1109 default:
1110 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1111 return;
1112 }
1113 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1114 gray = (gray + 1) * exposure / 0x300;
1115 // TODO: Additional processing
1116 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1117 if (gray < pocketCam->registers[matrixEntry + 6]) {
1118 gray = 0x101;
1119 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1120 gray = 0x100;
1121 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1122 gray = 0x001;
1123 } else {
1124 gray = 0;
1125 }
1126 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1127 uint16_t existing;
1128 LOAD_16LE(existing, coord + 0x100, memory->sram);
1129 existing |= gray << (7 - (x & 7));
1130 STORE_16LE(existing, coord + 0x100, memory->sram);
1131 }
1132 }
1133}
1134
1135void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1136 struct GBMemory* memory = &gb->memory;
1137 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1138 switch (address >> 13) {
1139 case 0x5:
1140 if (address & 1) {
1141 tama5->reg = value;
1142 } else {
1143 value &= 0xF;
1144 if (tama5->reg < GBTAMA5_MAX) {
1145 tama5->registers[tama5->reg] = value;
1146 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1147 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1148 switch (tama5->reg) {
1149 case GBTAMA5_BANK_LO:
1150 case GBTAMA5_BANK_HI:
1151 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1152 break;
1153 case GBTAMA5_WRITE_LO:
1154 case GBTAMA5_WRITE_HI:
1155 case GBTAMA5_CS:
1156 break;
1157 case GBTAMA5_ADDR_LO:
1158 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1159 case 0x0: // RAM write
1160 memory->sram[address] = out;
1161 break;
1162 case 0x1: // RAM read
1163 break;
1164 default:
1165 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1166 }
1167 break;
1168 default:
1169 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1170 break;
1171 }
1172 } else {
1173 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1174 }
1175 }
1176 break;
1177 default:
1178 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1179 }
1180}
1181
1182uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1183 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1184 if ((address & 0x1FFF) > 1) {
1185 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1186 }
1187 if (address & 1) {
1188 return 0xFF;
1189 } else {
1190 uint8_t value = 0xF0;
1191 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1192 switch (tama5->reg) {
1193 case GBTAMA5_ACTIVE:
1194 return 0xF1;
1195 case GBTAMA5_READ_LO:
1196 case GBTAMA5_READ_HI:
1197 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1198 case 1:
1199 value = memory->sram[address];
1200 break;
1201 default:
1202 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1203 break;
1204 }
1205 if (tama5->reg == GBTAMA5_READ_HI) {
1206 value >>= 4;
1207 }
1208 value |= 0xF0;
1209 return value;
1210 default:
1211 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1212 return 0xF1;
1213 }
1214 }
1215}
1216
1217void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1218 UNUSED(value);
1219 int bank = address & 0x3F;
1220 switch (address >> 14) {
1221 case 0x0:
1222 GBMBCSwitchBank0(gb, bank * 2);
1223 GBMBCSwitchBank(gb, bank * 2 + 1);
1224 break;
1225 default:
1226 // TODO
1227 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1228 break;
1229 }
1230}
1231
1232void GBMBCRTCRead(struct GB* gb) {
1233 struct GBMBCRTCSaveBuffer rtcBuffer;
1234 struct VFile* vf = gb->sramVf;
1235 if (!vf) {
1236 return;
1237 }
1238 vf->seek(vf, gb->sramSize, SEEK_SET);
1239 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1240 return;
1241 }
1242
1243 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1244 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1245 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1246 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1247 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1248 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1249}
1250
1251void GBMBCRTCWrite(struct GB* gb) {
1252 struct VFile* vf = gb->sramVf;
1253 if (!vf) {
1254 return;
1255 }
1256
1257 uint8_t rtcRegs[5];
1258 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1259 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1260 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1261
1262 struct GBMBCRTCSaveBuffer rtcBuffer;
1263 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1264 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1265 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1266 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1267 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1268 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1269 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1270 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1271 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1272 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1273 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1274
1275 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1276 // Writing past the end of the file can invalidate the file mapping
1277 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1278 gb->memory.sram = NULL;
1279 }
1280 vf->seek(vf, gb->sramSize, SEEK_SET);
1281 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1282 if (!gb->memory.sram) {
1283 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1284 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1285 }
1286}