src/arm/arm.c (view raw)
1#include "arm.h"
2
3#include "isa-arm.h"
4#include "isa-inlines.h"
5#include "isa-thumb.h"
6
7static inline enum RegisterBank _ARMSelectBank(enum PrivilegeMode);
8
9void ARMSetPrivilegeMode(struct ARMCore* cpu, enum PrivilegeMode mode) {
10 if (mode == cpu->privilegeMode) {
11 // Not switching modes after all
12 return;
13 }
14
15 enum RegisterBank newBank = _ARMSelectBank(mode);
16 enum RegisterBank oldBank = _ARMSelectBank(cpu->privilegeMode);
17 if (newBank != oldBank) {
18 // Switch banked registers
19 if (mode == MODE_FIQ || cpu->privilegeMode == MODE_FIQ) {
20 int oldFIQBank = oldBank == BANK_FIQ;
21 int newFIQBank = newBank == BANK_FIQ;
22 cpu->bankedRegisters[oldFIQBank][2] = cpu->gprs[8];
23 cpu->bankedRegisters[oldFIQBank][3] = cpu->gprs[9];
24 cpu->bankedRegisters[oldFIQBank][4] = cpu->gprs[10];
25 cpu->bankedRegisters[oldFIQBank][5] = cpu->gprs[11];
26 cpu->bankedRegisters[oldFIQBank][6] = cpu->gprs[12];
27 cpu->gprs[8] = cpu->bankedRegisters[newFIQBank][2];
28 cpu->gprs[9] = cpu->bankedRegisters[newFIQBank][3];
29 cpu->gprs[10] = cpu->bankedRegisters[newFIQBank][4];
30 cpu->gprs[11] = cpu->bankedRegisters[newFIQBank][5];
31 cpu->gprs[12] = cpu->bankedRegisters[newFIQBank][6];
32 }
33 cpu->bankedRegisters[oldBank][0] = cpu->gprs[ARM_SP];
34 cpu->bankedRegisters[oldBank][1] = cpu->gprs[ARM_LR];
35 cpu->gprs[ARM_SP] = cpu->bankedRegisters[newBank][0];
36 cpu->gprs[ARM_LR] = cpu->bankedRegisters[newBank][1];
37
38 cpu->bankedSPSRs[oldBank] = cpu->spsr.packed;
39 cpu->spsr.packed = cpu->bankedSPSRs[newBank];
40
41 }
42 cpu->privilegeMode = mode;
43}
44
45static inline enum RegisterBank _ARMSelectBank(enum PrivilegeMode mode) {
46 switch (mode) {
47 case MODE_USER:
48 case MODE_SYSTEM:
49 // No banked registers
50 return BANK_NONE;
51 case MODE_FIQ:
52 return BANK_FIQ;
53 case MODE_IRQ:
54 return BANK_IRQ;
55 case MODE_SUPERVISOR:
56 return BANK_SUPERVISOR;
57 case MODE_ABORT:
58 return BANK_ABORT;
59 case MODE_UNDEFINED:
60 return BANK_UNDEFINED;
61 default:
62 // This should be unreached
63 return BANK_NONE;
64 }
65}
66
67void ARMInit(struct ARMCore* cpu) {
68 cpu->master->init(cpu, cpu->master);
69 int i;
70 for (i = 0; i < cpu->numComponents; ++i) {
71 cpu->components[i]->init(cpu, cpu->components[i]);
72 }
73}
74
75void ARMDeinit(struct ARMCore* cpu) {
76 if (cpu->master->deinit) {
77 cpu->master->deinit(cpu->master);
78 }
79 int i;
80 for (i = 0; i < cpu->numComponents; ++i) {
81 if (cpu->components[i]->deinit) {
82 cpu->components[i]->deinit(cpu->components[i]);
83 }
84 }
85}
86
87void ARMSetComponents(struct ARMCore* cpu, struct ARMComponent* master, int extra, struct ARMComponent** extras) {
88 // TODO: Call init/deinit
89 cpu->master = master;
90 cpu->numComponents = extra;
91 cpu->components = extras;
92}
93
94
95void ARMReset(struct ARMCore* cpu) {
96 int i;
97 for (i = 0; i < 16; ++i) {
98 cpu->gprs[i] = 0;
99 }
100 for (i = 0; i < 6; ++i) {
101 cpu->bankedRegisters[i][0] = 0;
102 cpu->bankedRegisters[i][1] = 0;
103 cpu->bankedRegisters[i][2] = 0;
104 cpu->bankedRegisters[i][3] = 0;
105 cpu->bankedRegisters[i][4] = 0;
106 cpu->bankedRegisters[i][5] = 0;
107 cpu->bankedRegisters[i][6] = 0;
108 cpu->bankedSPSRs[i] = 0;
109 }
110
111 cpu->privilegeMode = MODE_SYSTEM;
112 cpu->cpsr.packed = MODE_SYSTEM;
113 cpu->spsr.packed = 0;
114
115 cpu->shifterOperand = 0;
116 cpu->shifterCarryOut = 0;
117
118 cpu->executionMode = MODE_THUMB;
119 _ARMSetMode(cpu, MODE_ARM);
120
121 cpu->currentPC = 0;
122 int currentCycles = 0;
123 ARM_WRITE_PC;
124
125 cpu->cycles = 0;
126 cpu->nextEvent = 0;
127 cpu->halted = 0;
128
129 cpu->irqh.reset(cpu);
130}
131
132void ARMRaiseIRQ(struct ARMCore* cpu) {
133 if (cpu->cpsr.i) {
134 return;
135 }
136 union PSR cpsr = cpu->cpsr;
137 int instructionWidth;
138 if (cpu->executionMode == MODE_THUMB) {
139 instructionWidth = WORD_SIZE_THUMB;
140 } else {
141 instructionWidth = WORD_SIZE_ARM;
142 }
143 ARMSetPrivilegeMode(cpu, MODE_IRQ);
144 cpu->cpsr.priv = MODE_IRQ;
145 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth + WORD_SIZE_ARM;
146 cpu->gprs[ARM_PC] = BASE_IRQ + WORD_SIZE_ARM;
147 cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);
148 _ARMSetMode(cpu, MODE_ARM);
149 cpu->spsr = cpsr;
150 cpu->cpsr.i = 1;
151}
152
153void ARMRaiseSWI(struct ARMCore* cpu) {
154 union PSR cpsr = cpu->cpsr;
155 int instructionWidth;
156 if (cpu->executionMode == MODE_THUMB) {
157 instructionWidth = WORD_SIZE_THUMB;
158 } else {
159 instructionWidth = WORD_SIZE_ARM;
160 }
161 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
162 cpu->cpsr.priv = MODE_SUPERVISOR;
163 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth;
164 cpu->gprs[ARM_PC] = BASE_SWI + WORD_SIZE_ARM;
165 cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);
166 _ARMSetMode(cpu, MODE_ARM);
167 cpu->spsr = cpsr;
168 cpu->cpsr.i = 1;
169}
170
171static inline void ARMStep(struct ARMCore* cpu) {
172 uint32_t opcode;
173 cpu->currentPC = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
174 LOAD_32(opcode, cpu->currentPC & cpu->memory.activeMask, cpu->memory.activeRegion);
175 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
176
177 int condition = opcode >> 28;
178 if (condition == 0xE) {
179 ARMInstruction instruction = _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
180 instruction(cpu, opcode);
181 return;
182 } else {
183 switch (condition) {
184 case 0x0:
185 if (!ARM_COND_EQ) {
186 cpu->cycles += ARM_PREFETCH_CYCLES;
187 return;
188 }
189 break;
190 case 0x1:
191 if (!ARM_COND_NE) {
192 cpu->cycles += ARM_PREFETCH_CYCLES;
193 return;
194 }
195 break;
196 case 0x2:
197 if (!ARM_COND_CS) {
198 cpu->cycles += ARM_PREFETCH_CYCLES;
199 return;
200 }
201 break;
202 case 0x3:
203 if (!ARM_COND_CC) {
204 cpu->cycles += ARM_PREFETCH_CYCLES;
205 return;
206 }
207 break;
208 case 0x4:
209 if (!ARM_COND_MI) {
210 cpu->cycles += ARM_PREFETCH_CYCLES;
211 return;
212 }
213 break;
214 case 0x5:
215 if (!ARM_COND_PL) {
216 cpu->cycles += ARM_PREFETCH_CYCLES;
217 return;
218 }
219 break;
220 case 0x6:
221 if (!ARM_COND_VS) {
222 cpu->cycles += ARM_PREFETCH_CYCLES;
223 return;
224 }
225 break;
226 case 0x7:
227 if (!ARM_COND_VC) {
228 cpu->cycles += ARM_PREFETCH_CYCLES;
229 return;
230 }
231 break;
232 case 0x8:
233 if (!ARM_COND_HI) {
234 cpu->cycles += ARM_PREFETCH_CYCLES;
235 return;
236 }
237 break;
238 case 0x9:
239 if (!ARM_COND_LS) {
240 cpu->cycles += ARM_PREFETCH_CYCLES;
241 return;
242 }
243 break;
244 case 0xA:
245 if (!ARM_COND_GE) {
246 cpu->cycles += ARM_PREFETCH_CYCLES;
247 return;
248 }
249 break;
250 case 0xB:
251 if (!ARM_COND_LT) {
252 cpu->cycles += ARM_PREFETCH_CYCLES;
253 return;
254 }
255 break;
256 case 0xC:
257 if (!ARM_COND_GT) {
258 cpu->cycles += ARM_PREFETCH_CYCLES;
259 return;
260 }
261 break;
262 case 0xD:
263 if (!ARM_COND_LE) {
264 cpu->cycles += ARM_PREFETCH_CYCLES;
265 return;
266 }
267 break;
268 default:
269 break;
270 }
271 }
272 ARMInstruction instruction = _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
273 instruction(cpu, opcode);
274}
275
276static inline void ThumbStep(struct ARMCore* cpu) {
277 cpu->currentPC = cpu->gprs[ARM_PC] - WORD_SIZE_THUMB;
278 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
279 uint16_t opcode;
280 LOAD_16(opcode, cpu->currentPC & cpu->memory.activeMask, cpu->memory.activeRegion);
281 ThumbInstruction instruction = _thumbTable[opcode >> 6];
282 instruction(cpu, opcode);
283}
284
285void ARMRun(struct ARMCore* cpu) {
286 if (cpu->executionMode == MODE_THUMB) {
287 ThumbStep(cpu);
288 } else {
289 ARMStep(cpu);
290 }
291 if (cpu->cycles >= cpu->nextEvent) {
292 cpu->irqh.processEvents(cpu);
293 }
294}