src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259
260#define ADDR_MODE_4_WRITEBACK_LDM \
261 if (!((1 << rn) & rs)) { \
262 cpu->gprs[rn] = address; \
263 }
264
265#define ADDR_MODE_4_WRITEBACK_LDMv5 \
266 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
267 cpu->gprs[rn] = address; \
268 }
269
270#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
271
272#define ARM_LOAD_POST_BODY \
273 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
274 if (rd == ARM_PC) { \
275 ARM_WRITE_PC; \
276 }
277
278#define ARM_STORE_POST_BODY \
279 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
280
281#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
282 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
283 int currentCycles = ARM_PREFETCH_CYCLES; \
284 BODY; \
285 cpu->cycles += currentCycles; \
286 }
287
288#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
289 DEFINE_INSTRUCTION_ARM(NAME, \
290 int rd = (opcode >> 12) & 0xF; \
291 int rn = (opcode >> 16) & 0xF; \
292 UNUSED(rn); \
293 SHIFTER(cpu, opcode); \
294 BODY; \
295 S_BODY; \
296 if (rd == ARM_PC) { \
297 if (cpu->executionMode == MODE_ARM) { \
298 ARM_WRITE_PC; \
299 } else { \
300 THUMB_WRITE_PC; \
301 } \
302 })
303
304#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
315
316#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
322
323#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
324 DEFINE_INSTRUCTION_ARM(NAME, \
325 int rd = (opcode >> 16) & 0xF; \
326 int rs = (opcode >> 8) & 0xF; \
327 int rm = opcode & 0xF; \
328 if (rd == ARM_PC) { \
329 return; \
330 } \
331 ARM_WAIT_MUL(cpu->gprs[rs]); \
332 BODY; \
333 S_BODY; \
334 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
335
336#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
337 DEFINE_INSTRUCTION_ARM(NAME, \
338 int rd = (opcode >> 12) & 0xF; \
339 int rdHi = (opcode >> 16) & 0xF; \
340 int rs = (opcode >> 8) & 0xF; \
341 int rm = opcode & 0xF; \
342 if (rdHi == ARM_PC || rd == ARM_PC) { \
343 return; \
344 } \
345 currentCycles += cpu->memory.stall(cpu, WAIT); \
346 BODY; \
347 S_BODY; \
348 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
349
350#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
351 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
352 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
353
354#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
355 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
356 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
357
358#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
359 DEFINE_INSTRUCTION_ARM(NAME, \
360 int rd = (opcode >> 16) & 0xF; \
361 int rs = (opcode >> 8) & 0xF; \
362 int rn = (opcode >> 12) & 0xF; \
363 int rm = opcode & 0xF; \
364 if (rd == ARM_PC) { \
365 return; \
366 } \
367 /* TODO: Timing */ \
368 int32_t x; \
369 int32_t y; \
370 BODY; \
371 int32_t dn = cpu->gprs[rn]; \
372 int32_t d = x * y; \
373 cpu->gprs[rd] = d + dn; \
374 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]); \
375 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
376
377#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
378 DEFINE_INSTRUCTION_ARM(NAME, \
379 uint32_t address; \
380 int rn = (opcode >> 16) & 0xF; \
381 int rd = (opcode >> 12) & 0xF; \
382 int rm = opcode & 0xF; \
383 UNUSED(rm); \
384 address = ADDRESS; \
385 WRITEBACK; \
386 BODY;)
387
388#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
395
396#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
407
408#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
421
422#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
423 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
424 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
425
426#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
427 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
428 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
429 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
430 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
431 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
433
434#define ARM_MS_PRE \
435 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
436 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
437
438#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
439
440#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
441 DEFINE_INSTRUCTION_ARM(NAME, \
442 int rn = (opcode >> 16) & 0xF; \
443 int rs = opcode & 0x0000FFFF; \
444 uint32_t address = cpu->gprs[rn]; \
445 S_PRE; \
446 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
447 S_POST; \
448 POST_BODY; \
449 WRITEBACK;)
450
451
452#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
461
462#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
464 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
465 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
469 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
470 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
471 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
472
473// Begin ALU definitions
474
475DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
476 int32_t n = cpu->gprs[rn];
477 cpu->gprs[rd] = n + cpu->shifterOperand;)
478
479DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
480 int32_t n = cpu->gprs[rn];
481 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
482
483DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
484 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
487 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
490 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
493 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
496 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
502 cpu->gprs[rd] = ~cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
505 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
506
507DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
508 int32_t n = cpu->gprs[rn];
509 cpu->gprs[rd] = cpu->shifterOperand - n;)
510
511DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
512 int32_t n = cpu->gprs[rn];
513 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
514
515DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
516 int32_t n = cpu->gprs[rn];
517 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
518
519DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
520 int32_t n = cpu->gprs[rn];
521 cpu->gprs[rd] = n - cpu->shifterOperand;)
522
523DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
524 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
525
526DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
527 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
528
529// End ALU definitions
530
531// Begin multiply definitions
532
533DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
534DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
535
536DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
537 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
538 int32_t dm = cpu->gprs[rd];
539 int32_t dn = d;
540 cpu->gprs[rd] = dm + dn;
541 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
542 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
543
544DEFINE_MULTIPLY_INSTRUCTION_3_ARM(SMLABB,
545 x = ARM_SXT_16(cpu->gprs[rm]);
546 y = ARM_SXT_16(cpu->gprs[rs]);)
547
548DEFINE_MULTIPLY_INSTRUCTION_3_ARM(SMLABT,
549 x = ARM_SXT_16(cpu->gprs[rm]);
550 y = ARM_SXT_16(cpu->gprs[rs] >> 16);)
551
552DEFINE_MULTIPLY_INSTRUCTION_3_ARM(SMLATB,
553 x = ARM_SXT_16(cpu->gprs[rm] >> 16);
554 y = ARM_SXT_16(cpu->gprs[rs]);)
555
556DEFINE_MULTIPLY_INSTRUCTION_3_ARM(SMLATT,
557 x = ARM_SXT_16(cpu->gprs[rm] >> 16);
558 y = ARM_SXT_16(cpu->gprs[rs] >> 16);)
559
560DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
561 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
562 cpu->gprs[rd] = d;
563 cpu->gprs[rdHi] = d >> 32;,
564 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
565
566DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
567 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
568 int32_t dm = cpu->gprs[rd];
569 int32_t dn = d;
570 cpu->gprs[rd] = dm + dn;
571 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
572 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
573
574DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
575 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
576 cpu->gprs[rd] = d;
577 cpu->gprs[rdHi] = d >> 32;,
578 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
579
580// End multiply definitions
581
582// Begin load/store definitions
583
584DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
585DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
586DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
587DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
588DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
589DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
590DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
591DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
592
593DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
594 enum PrivilegeMode priv = cpu->privilegeMode;
595 ARMSetPrivilegeMode(cpu, MODE_USER);
596 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
597 ARMSetPrivilegeMode(cpu, priv);
598 cpu->gprs[rd] = r;
599 ARM_LOAD_POST_BODY;)
600
601DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
602 enum PrivilegeMode priv = cpu->privilegeMode;
603 ARMSetPrivilegeMode(cpu, MODE_USER);
604 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
605 ARMSetPrivilegeMode(cpu, priv);
606 cpu->gprs[rd] = r;
607 ARM_LOAD_POST_BODY;)
608
609DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
610 enum PrivilegeMode priv = cpu->privilegeMode;
611 int32_t r = cpu->gprs[rd];
612 ARMSetPrivilegeMode(cpu, MODE_USER);
613 cpu->memory.store8(cpu, address, r, ¤tCycles);
614 ARMSetPrivilegeMode(cpu, priv);
615 ARM_STORE_POST_BODY;)
616
617DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
618 enum PrivilegeMode priv = cpu->privilegeMode;
619 int32_t r = cpu->gprs[rd];
620 ARMSetPrivilegeMode(cpu, MODE_USER);
621 cpu->memory.store32(cpu, address, r, ¤tCycles);
622 ARMSetPrivilegeMode(cpu, priv);
623 ARM_STORE_POST_BODY;)
624
625DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
626 load,
627 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
628 if (rs & 0x8000) {
629 ARM_WRITE_PC;
630 })
631
632DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
633 load,
634 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
635 if (rs & 0x8000) {
636 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
637 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
638 if (cpu->executionMode == MODE_THUMB) {
639 THUMB_WRITE_PC;
640 } else {
641 ARM_WRITE_PC;
642
643 }
644 })
645
646DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
647 store,
648 ARM_STORE_POST_BODY;)
649
650DEFINE_INSTRUCTION_ARM(SWP,
651 int rm = opcode & 0xF;
652 int rd = (opcode >> 12) & 0xF;
653 int rn = (opcode >> 16) & 0xF;
654 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
655 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
656 cpu->gprs[rd] = d;)
657
658DEFINE_INSTRUCTION_ARM(SWPB,
659 int rm = opcode & 0xF;
660 int rd = (opcode >> 12) & 0xF;
661 int rn = (opcode >> 16) & 0xF;
662 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
663 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
664 cpu->gprs[rd] = d;)
665
666// End load/store definitions
667
668// Begin branch definitions
669
670DEFINE_INSTRUCTION_ARM(B,
671 int32_t offset = opcode << 8;
672 offset >>= 6;
673 cpu->gprs[ARM_PC] += offset;
674 ARM_WRITE_PC;)
675
676DEFINE_INSTRUCTION_ARM(BL,
677 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
678 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
679 cpu->gprs[ARM_PC] += immediate >> 6;
680 ARM_WRITE_PC;)
681
682DEFINE_INSTRUCTION_ARM(BX,
683 int rm = opcode & 0x0000000F;
684 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
685 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
686 if (cpu->executionMode == MODE_THUMB) {
687 THUMB_WRITE_PC;
688 } else {
689 ARM_WRITE_PC;
690
691 })
692
693DEFINE_INSTRUCTION_ARM(BLX,
694 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
695 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
696 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
697 _ARMSetMode(cpu, MODE_THUMB);
698 THUMB_WRITE_PC;)
699
700DEFINE_INSTRUCTION_ARM(BLX2,
701 int rm = opcode & 0x0000000F;
702 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
703 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
704 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
705 if (cpu->executionMode == MODE_THUMB) {
706 THUMB_WRITE_PC;
707 } else {
708 ARM_WRITE_PC;
709 })
710
711// End branch definitions
712
713// Begin coprocessor definitions
714
715#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
716 DEFINE_INSTRUCTION_ARM(NAME, \
717 int op1 = (opcode >> 21) & 7; \
718 int op2 = (opcode >> 5) & 7; \
719 int rd = (opcode >> 12) & 0xF; \
720 int cp = (opcode >> 8) & 0xF; \
721 int crn = (opcode >> 16) & 0xF; \
722 int crm = opcode & 0xF; \
723 UNUSED(op1); \
724 UNUSED(op2); \
725 UNUSED(rd); \
726 UNUSED(crn); \
727 UNUSED(crm); \
728 BODY;)
729
730DEFINE_COPROCESSOR_INSTRUCTION(MRC,
731 if (cp == 15 && cpu->irqh.readCP15) {
732 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
733 } else {
734 ARM_STUB;
735 })
736
737DEFINE_COPROCESSOR_INSTRUCTION(MCR,
738 if (cp == 15 && cpu->irqh.writeCP15) {
739 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
740 } else {
741 ARM_STUB;
742 })
743
744DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
745DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
746DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
747
748// Begin miscellaneous definitions
749
750DEFINE_INSTRUCTION_ARM(CLZ,
751 int rm = opcode & 0xF;
752 int rd = (opcode >> 12) & 0xF;
753 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
754
755DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
756DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
757
758DEFINE_INSTRUCTION_ARM(MSR,
759 int c = opcode & 0x00010000;
760 int f = opcode & 0x00080000;
761 int32_t operand = cpu->gprs[opcode & 0x0000000F];
762 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
763 if (mask & PSR_USER_MASK) {
764 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
765 }
766 if (mask & PSR_STATE_MASK) {
767 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
768 }
769 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
770 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
771 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
772 }
773 _ARMReadCPSR(cpu);
774 if (cpu->executionMode == MODE_THUMB) {
775 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
776 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
777 } else {
778 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
779 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
780 })
781
782DEFINE_INSTRUCTION_ARM(MSRR,
783 int c = opcode & 0x00010000;
784 int f = opcode & 0x00080000;
785 int32_t operand = cpu->gprs[opcode & 0x0000000F];
786 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
787 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
788 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
789
790DEFINE_INSTRUCTION_ARM(MRS, \
791 int rd = (opcode >> 12) & 0xF; \
792 cpu->gprs[rd] = cpu->cpsr.packed;)
793
794DEFINE_INSTRUCTION_ARM(MRSR, \
795 int rd = (opcode >> 12) & 0xF; \
796 cpu->gprs[rd] = cpu->spsr.packed;)
797
798DEFINE_INSTRUCTION_ARM(MSRI,
799 int c = opcode & 0x00010000;
800 int f = opcode & 0x00080000;
801 int rotate = (opcode & 0x00000F00) >> 7;
802 int32_t operand = ROR(opcode & 0x000000FF, rotate);
803 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
804 if (mask & PSR_USER_MASK) {
805 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
806 }
807 if (mask & PSR_STATE_MASK) {
808 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
809 }
810 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
811 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
812 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
813 }
814 _ARMReadCPSR(cpu);
815 if (cpu->executionMode == MODE_THUMB) {
816 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
817 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
818 } else {
819 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
820 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
821 })
822
823DEFINE_INSTRUCTION_ARM(MSRRI,
824 int c = opcode & 0x00010000;
825 int f = opcode & 0x00080000;
826 int rotate = (opcode & 0x00000F00) >> 7;
827 int32_t operand = ROR(opcode & 0x000000FF, rotate);
828 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
829 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
830 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
831
832DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
833
834const ARMInstruction _armv4Table[0x1000] = {
835 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
836};
837
838const ARMInstruction _armv5Table[0x1000] = {
839 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
840};
841
842const ARMInstruction _armv4FTable[0x1000] = {
843 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
844};
845
846const ARMInstruction _armv5FTable[0x1000] = {
847 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
848};