src/ds/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/io.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/ds/ds.h>
10#include <mgba/internal/ds/ipc.h>
11#include <mgba/internal/ds/spi.h>
12
13mLOG_DEFINE_CATEGORY(DS_IO, "DS I/O");
14
15static void _DSHaltCNT(struct DSCommon* dscore, uint8_t value) {
16 switch (value >> 6) {
17 case 0:
18 default:
19 break;
20 case 1:
21 mLOG(DS_IO, STUB, "Enter GBA mode not supported");
22 break;
23 case 2:
24 ARMHalt(dscore->cpu);
25 break;
26 case 3:
27 mLOG(DS_IO, STUB, "Enter sleep mode not supported");
28 break;
29 }
30}
31
32static uint16_t _scheduleDiv(struct DS* ds, uint16_t control) {
33 mTimingDeschedule(&ds->ds9.timing, &ds->divEvent);
34 mTimingSchedule(&ds->ds9.timing, &ds->divEvent, (control & 3) ? 36 : 68);
35 return control | 0x8000;
36}
37
38static uint16_t _scheduleSqrt(struct DS* ds, uint16_t control) {
39 mTimingDeschedule(&ds->ds9.timing, &ds->sqrtEvent);
40 mTimingSchedule(&ds->ds9.timing, &ds->sqrtEvent, 26);
41 return control | 0x8000;
42}
43
44static uint32_t DSIOWrite(struct DSCommon* dscore, uint32_t address, uint16_t value) {
45 switch (address) {
46 // Video
47 case DS_REG_DISPSTAT:
48 DSVideoWriteDISPSTAT(dscore, value);
49 break;
50
51 // DMA Fill
52 case DS_REG_DMA0FILL_LO:
53 case DS_REG_DMA0FILL_HI:
54 case DS_REG_DMA1FILL_LO:
55 case DS_REG_DMA1FILL_HI:
56 case DS_REG_DMA2FILL_LO:
57 case DS_REG_DMA2FILL_HI:
58 case DS_REG_DMA3FILL_LO:
59 case DS_REG_DMA3FILL_HI:
60 break;
61
62 // Timers
63 case DS_REG_TM0CNT_LO:
64 GBATimerWriteTMCNT_LO(&dscore->timers[0], value);
65 return 0x20000;
66 case DS_REG_TM1CNT_LO:
67 GBATimerWriteTMCNT_LO(&dscore->timers[1], value);
68 return 0x20000;
69 case DS_REG_TM2CNT_LO:
70 GBATimerWriteTMCNT_LO(&dscore->timers[2], value);
71 return 0x20000;
72 case DS_REG_TM3CNT_LO:
73 GBATimerWriteTMCNT_LO(&dscore->timers[3], value);
74 return 0x20000;
75
76 case DS_REG_TM0CNT_HI:
77 value &= 0x00C7;
78 DSTimerWriteTMCNT_HI(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM0CNT_LO >> 1], value);
79 break;
80 case DS_REG_TM1CNT_HI:
81 value &= 0x00C7;
82 DSTimerWriteTMCNT_HI(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM1CNT_LO >> 1], value);
83 break;
84 case DS_REG_TM2CNT_HI:
85 value &= 0x00C7;
86 DSTimerWriteTMCNT_HI(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM2CNT_LO >> 1], value);
87 break;
88 case DS_REG_TM3CNT_HI:
89 value &= 0x00C7;
90 DSTimerWriteTMCNT_HI(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM3CNT_LO >> 1], value);
91 break;
92
93 // IPC
94 case DS_REG_IPCSYNC:
95 value &= 0x6F00;
96 value |= dscore->memory.io[address >> 1] & 0x000F;
97 DSIPCWriteSYNC(dscore->ipc->cpu, dscore->ipc->memory.io, value);
98 break;
99 case DS_REG_IPCFIFOCNT:
100 value = DSIPCWriteFIFOCNT(dscore, value);
101 break;
102
103 // Cart bus
104 case DS_REG_SLOT1CNT_LO:
105 mLOG(DS_IO, STUB, "ROM control not implemented");
106 value &= 0x7FFF;
107 break;
108
109 // Interrupts
110 case DS_REG_IME:
111 DSWriteIME(dscore->cpu, dscore->memory.io, value);
112 break;
113 case 0x20A:
114 value = 0;
115 // Some bad interrupt libraries will write to this
116 break;
117 case DS_REG_IF_LO:
118 case DS_REG_IF_HI:
119 value = dscore->memory.io[address >> 1] & ~value;
120 break;
121 default:
122 return 0;
123 }
124 return value | 0x10000;
125}
126
127static uint16_t DSIOReadKeyInput(struct DS* ds) {
128 uint16_t input = 0x3FF;
129 if (ds->keyCallback) {
130 input = ds->keyCallback->readKeys(ds->keyCallback);
131 } else if (ds->keySource) {
132 input = *ds->keySource;
133 }
134 // TODO: Put back
135 /*if (!dscore->p->allowOpposingDirections) {
136 unsigned rl = input & 0x030;
137 unsigned ud = input & 0x0C0;
138 input &= 0x30F;
139 if (rl != 0x030) {
140 input |= rl;
141 }
142 if (ud != 0x0C0) {
143 input |= ud;
144 }
145 }*/
146 return 0x3FF ^ input;
147}
148
149static void DSIOUpdateTimer(struct DSCommon* dscore, uint32_t address) {
150 switch (address) {
151 case DS_REG_TM0CNT_LO:
152 GBATimerUpdateRegisterInternal(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
153 break;
154 case DS_REG_TM1CNT_LO:
155 GBATimerUpdateRegisterInternal(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
156 break;
157 case DS_REG_TM2CNT_LO:
158 GBATimerUpdateRegisterInternal(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
159 break;
160 case DS_REG_TM3CNT_LO:
161 GBATimerUpdateRegisterInternal(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
162 break;
163 }
164}
165
166void DS7IOInit(struct DS* ds) {
167 memset(ds->memory.io7, 0, sizeof(ds->memory.io7));
168 ds->memory.io7[DS_REG_IPCFIFOCNT >> 1] = 0x0101;
169}
170
171void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
172 switch (address) {
173 case DS7_REG_SPICNT:
174 value &= 0xCF83;
175 value = DSSPIWriteControl(ds, value);
176 break;
177 case DS7_REG_SPIDATA:
178 DSSPIWrite(ds, value);
179 return;
180 default:
181 {
182 uint32_t v2 = DSIOWrite(&ds->ds7, address, value);
183 if (v2 & 0x10000) {
184 value = v2;
185 break;
186 } else if (v2 & 0x20000) {
187 return;
188 }
189 }
190 mLOG(DS_IO, STUB, "Stub DS7 I/O register write: %06X:%04X", address, value);
191 if (address >= DS7_REG_MAX) {
192 mLOG(DS_IO, GAME_ERROR, "Write to unused DS7 I/O register: %06X:%04X", address, value);
193 return;
194 }
195 break;
196 }
197 ds->memory.io7[address >> 1] = value;
198}
199
200void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
201 if (address == DS7_REG_HALTCNT) {
202 _DSHaltCNT(&ds->ds7, value);
203 return;
204 }
205 if (address < DS7_REG_MAX) {
206 uint16_t value16 = value << (8 * (address & 1));
207 value16 |= (ds->ds7.memory.io[(address & 0xFFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
208 DS7IOWrite(ds, address & 0xFFFFFFFE, value16);
209 } else {
210 mLOG(DS, STUB, "Writing to unknown DS7 register: %08X:%02X", address, value);
211 }
212}
213
214void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
215 switch (address) {
216 case DS_REG_DMA0SAD_LO:
217 value = DSDMAWriteSAD(&ds->ds7, 0, value);
218 break;
219 case DS_REG_DMA1SAD_LO:
220 value = DSDMAWriteSAD(&ds->ds7, 1, value);
221 break;
222 case DS_REG_DMA2SAD_LO:
223 value = DSDMAWriteSAD(&ds->ds7, 2, value);
224 break;
225 case DS_REG_DMA3SAD_LO:
226 value = DSDMAWriteSAD(&ds->ds7, 3, value);
227 break;
228
229 case DS_REG_DMA0DAD_LO:
230 value = DSDMAWriteDAD(&ds->ds7, 0, value);
231 break;
232 case DS_REG_DMA1DAD_LO:
233 value = DSDMAWriteDAD(&ds->ds7, 1, value);
234 break;
235 case DS_REG_DMA2DAD_LO:
236 value = DSDMAWriteDAD(&ds->ds7, 2, value);
237 break;
238 case DS_REG_DMA3DAD_LO:
239 value = DSDMAWriteDAD(&ds->ds7, 3, value);
240 break;
241
242 case DS_REG_DMA0CNT_LO:
243 DS7DMAWriteCNT(&ds->ds7, 0, value);
244 break;
245 case DS_REG_DMA1CNT_LO:
246 DS7DMAWriteCNT(&ds->ds7, 1, value);
247 break;
248 case DS_REG_DMA2CNT_LO:
249 DS7DMAWriteCNT(&ds->ds7, 2, value);
250 break;
251 case DS_REG_DMA3CNT_LO:
252 DS7DMAWriteCNT(&ds->ds7, 3, value);
253 break;
254
255 case DS_REG_IPCFIFOSEND_LO:
256 DSIPCWriteFIFO(&ds->ds7, value);
257 break;
258 case DS_REG_IE_LO:
259 DSWriteIE(ds->ds7.cpu, ds->ds7.memory.io, value);
260 break;
261 default:
262 DS7IOWrite(ds, address, value & 0xFFFF);
263 DS7IOWrite(ds, address | 2, value >> 16);
264 return;
265 }
266 ds->ds7.memory.io[address >> 1] = value;
267 ds->ds7.memory.io[(address >> 1) + 1] = value >> 16;
268}
269
270uint16_t DS7IORead(struct DS* ds, uint32_t address) {
271 switch (address) {
272 case DS_REG_TM0CNT_LO:
273 case DS_REG_TM1CNT_LO:
274 case DS_REG_TM2CNT_LO:
275 case DS_REG_TM3CNT_LO:
276 DSIOUpdateTimer(&ds->ds7, address);
277 break;
278 case DS_REG_KEYINPUT:
279 return DSIOReadKeyInput(ds);
280 case DS_REG_DMA0FILL_LO:
281 case DS_REG_DMA0FILL_HI:
282 case DS_REG_DMA1FILL_LO:
283 case DS_REG_DMA1FILL_HI:
284 case DS_REG_DMA2FILL_LO:
285 case DS_REG_DMA2FILL_HI:
286 case DS_REG_DMA3FILL_LO:
287 case DS_REG_DMA3FILL_HI:
288 case DS_REG_TM0CNT_HI:
289 case DS_REG_TM1CNT_HI:
290 case DS_REG_TM2CNT_HI:
291 case DS_REG_TM3CNT_HI:
292 case DS7_REG_SPICNT:
293 case DS7_REG_SPIDATA:
294 case DS_REG_IPCSYNC:
295 case DS_REG_IPCFIFOCNT:
296 case DS_REG_IME:
297 case 0x20A:
298 case DS_REG_IE_LO:
299 case DS_REG_IE_HI:
300 case DS_REG_IF_LO:
301 case DS_REG_IF_HI:
302 // Handled transparently by the registers
303 break;
304 default:
305 mLOG(DS_IO, STUB, "Stub DS7 I/O register read: %06X", address);
306 }
307 if (address < DS7_REG_MAX) {
308 return ds->memory.io7[address >> 1];
309 }
310 return 0;
311}
312
313uint32_t DS7IORead32(struct DS* ds, uint32_t address) {
314 switch (address) {
315 case DS_REG_IPCFIFORECV_LO:
316 return DSIPCReadFIFO(&ds->ds7);
317 default:
318 return DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
319 }
320}
321
322void DS9IOInit(struct DS* ds) {
323 memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
324 ds->memory.io9[DS_REG_IPCFIFOCNT >> 1] = 0x0101;
325}
326
327void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
328 switch (address) {
329 // VRAM control
330 case DS9_REG_VRAMCNT_A:
331 case DS9_REG_VRAMCNT_C:
332 case DS9_REG_VRAMCNT_E:
333 DSVideoConfigureVRAM(&ds->memory, address - DS9_REG_VRAMCNT_A + 1, value & 0xFF);
334 DSVideoConfigureVRAM(&ds->memory, address - DS9_REG_VRAMCNT_A, value >> 8);
335 break;
336 case DS9_REG_VRAMCNT_G:
337 DSVideoConfigureVRAM(&ds->memory, 6, value >> 8);
338 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address + 1, value);
339 break;
340 case DS9_REG_VRAMCNT_H:
341 DSVideoConfigureVRAM(&ds->memory, 7, value >> 8);
342 DSVideoConfigureVRAM(&ds->memory, 8, value & 0xFF);
343 break;
344
345 // Math
346 case DS9_REG_DIVCNT:
347 value = _scheduleDiv(ds, value);
348 break;
349 case DS9_REG_DIV_NUMER_0:
350 case DS9_REG_DIV_NUMER_1:
351 case DS9_REG_DIV_NUMER_2:
352 case DS9_REG_DIV_NUMER_3:
353 case DS9_REG_DIV_DENOM_0:
354 case DS9_REG_DIV_DENOM_1:
355 case DS9_REG_DIV_DENOM_2:
356 case DS9_REG_DIV_DENOM_3:
357 ds->memory.io9[DS9_REG_DIVCNT >> 1] = _scheduleDiv(ds, ds->memory.io9[DS9_REG_DIVCNT >> 1]);
358 break;
359 case DS9_REG_SQRTCNT:
360 value = _scheduleSqrt(ds, value);
361 break;
362 case DS9_REG_SQRT_PARAM_0:
363 case DS9_REG_SQRT_PARAM_1:
364 case DS9_REG_SQRT_PARAM_2:
365 case DS9_REG_SQRT_PARAM_3:
366 ds->memory.io9[DS9_REG_SQRTCNT >> 1] = _scheduleSqrt(ds, ds->memory.io9[DS9_REG_SQRTCNT >> 1]);
367 break;
368
369 default:
370 {
371 uint32_t v2 = DSIOWrite(&ds->ds9, address, value);
372 if (v2 & 0x10000) {
373 value = v2;
374 break;
375 } else if (v2 & 0x20000) {
376 return;
377 }
378 }
379 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address, value);
380 if (address >= DS7_REG_MAX) {
381 mLOG(DS_IO, GAME_ERROR, "Write to unused DS9 I/O register: %06X:%04X", address, value);
382 return;
383 }
384 break;
385 }
386 ds->memory.io9[address >> 1] = value;
387}
388
389void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
390 if (address < DS9_REG_MAX) {
391 uint16_t value16 = value << (8 * (address & 1));
392 value16 |= (ds->memory.io9[(address & 0x1FFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
393 DS9IOWrite(ds, address & 0xFFFFFFFE, value16);
394 } else {
395 mLOG(DS, STUB, "Writing to unknown DS9 register: %08X:%02X", address, value);
396 }
397}
398
399void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
400 switch (address) {
401 case DS_REG_DMA0SAD_LO:
402 value = DSDMAWriteSAD(&ds->ds9, 0, value);
403 break;
404 case DS_REG_DMA1SAD_LO:
405 value = DSDMAWriteSAD(&ds->ds9, 1, value);
406 break;
407 case DS_REG_DMA2SAD_LO:
408 value = DSDMAWriteSAD(&ds->ds9, 2, value);
409 break;
410 case DS_REG_DMA3SAD_LO:
411 value = DSDMAWriteSAD(&ds->ds9, 3, value);
412 break;
413
414 case DS_REG_DMA0DAD_LO:
415 value = DSDMAWriteDAD(&ds->ds9, 0, value);
416 break;
417 case DS_REG_DMA1DAD_LO:
418 value = DSDMAWriteDAD(&ds->ds9, 1, value);
419 break;
420 case DS_REG_DMA2DAD_LO:
421 value = DSDMAWriteDAD(&ds->ds9, 2, value);
422 break;
423 case DS_REG_DMA3DAD_LO:
424 value = DSDMAWriteDAD(&ds->ds9, 3, value);
425 break;
426
427 case DS_REG_DMA0CNT_LO:
428 DS9DMAWriteCNT(&ds->ds9, 0, value);
429 break;
430 case DS_REG_DMA1CNT_LO:
431 DS9DMAWriteCNT(&ds->ds9, 1, value);
432 break;
433 case DS_REG_DMA2CNT_LO:
434 DS9DMAWriteCNT(&ds->ds9, 2, value);
435 break;
436 case DS_REG_DMA3CNT_LO:
437 DS9DMAWriteCNT(&ds->ds9, 3, value);
438 break;
439
440 case DS_REG_IPCFIFOSEND_LO:
441 DSIPCWriteFIFO(&ds->ds9, value);
442 break;
443 case DS_REG_IE_LO:
444 DSWriteIE(ds->ds9.cpu, ds->ds9.memory.io, value);
445 break;
446 default:
447 DS9IOWrite(ds, address, value & 0xFFFF);
448 DS9IOWrite(ds, address | 2, value >> 16);
449 return;
450 }
451 ds->ds9.memory.io[address >> 1] = value;
452 ds->ds9.memory.io[(address >> 1) + 1] = value >> 16;
453}
454
455uint16_t DS9IORead(struct DS* ds, uint32_t address) {
456 switch (address) {
457 case DS_REG_TM0CNT_LO:
458 case DS_REG_TM1CNT_LO:
459 case DS_REG_TM2CNT_LO:
460 case DS_REG_TM3CNT_LO:
461 DSIOUpdateTimer(&ds->ds9, address);
462 break;
463 case DS_REG_KEYINPUT:
464 return DSIOReadKeyInput(ds);
465 case DS_REG_DMA0FILL_LO:
466 case DS_REG_DMA0FILL_HI:
467 case DS_REG_DMA1FILL_LO:
468 case DS_REG_DMA1FILL_HI:
469 case DS_REG_DMA2FILL_LO:
470 case DS_REG_DMA2FILL_HI:
471 case DS_REG_DMA3FILL_LO:
472 case DS_REG_DMA3FILL_HI:
473 case DS_REG_TM0CNT_HI:
474 case DS_REG_TM1CNT_HI:
475 case DS_REG_TM2CNT_HI:
476 case DS_REG_TM3CNT_HI:
477 case DS_REG_IPCSYNC:
478 case DS_REG_IPCFIFOCNT:
479 case DS_REG_IME:
480 case 0x20A:
481 case DS_REG_IE_LO:
482 case DS_REG_IE_HI:
483 case DS_REG_IF_LO:
484 case DS_REG_IF_HI:
485 case DS9_REG_DIVCNT:
486 case DS9_REG_DIV_NUMER_0:
487 case DS9_REG_DIV_NUMER_1:
488 case DS9_REG_DIV_NUMER_2:
489 case DS9_REG_DIV_NUMER_3:
490 case DS9_REG_DIV_DENOM_0:
491 case DS9_REG_DIV_DENOM_1:
492 case DS9_REG_DIV_DENOM_2:
493 case DS9_REG_DIV_DENOM_3:
494 case DS9_REG_DIV_RESULT_0:
495 case DS9_REG_DIV_RESULT_1:
496 case DS9_REG_DIV_RESULT_2:
497 case DS9_REG_DIV_RESULT_3:
498 case DS9_REG_DIVREM_RESULT_0:
499 case DS9_REG_DIVREM_RESULT_1:
500 case DS9_REG_DIVREM_RESULT_2:
501 case DS9_REG_DIVREM_RESULT_3:
502 case DS9_REG_SQRTCNT:
503 case DS9_REG_SQRT_PARAM_0:
504 case DS9_REG_SQRT_PARAM_1:
505 case DS9_REG_SQRT_PARAM_2:
506 case DS9_REG_SQRT_PARAM_3:
507 case DS9_REG_SQRT_RESULT_LO:
508 case DS9_REG_SQRT_RESULT_HI:
509 // Handled transparently by the registers
510 break;
511 default:
512 mLOG(DS_IO, STUB, "Stub DS9 I/O register read: %06X", address);
513 }
514 if (address < DS9_REG_MAX) {
515 return ds->ds9.memory.io[address >> 1];
516 }
517 return 0;
518}
519
520uint32_t DS9IORead32(struct DS* ds, uint32_t address) {
521 switch (address) {
522 case DS_REG_IPCFIFORECV_LO:
523 return DSIPCReadFIFO(&ds->ds9);
524 default:
525 return DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
526 }
527}