src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define ARM_ADDITION_S(M, N, D) \
188 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
189 cpu->cpsr = cpu->spsr; \
190 _ARMReadCPSR(cpu); \
191 } else { \
192 cpu->cpsr.n = ARM_SIGN(D); \
193 cpu->cpsr.z = !(D); \
194 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
195 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
196 }
197
198#define ARM_SUBTRACTION_S(M, N, D) \
199 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
200 cpu->cpsr = cpu->spsr; \
201 _ARMReadCPSR(cpu); \
202 } else { \
203 cpu->cpsr.n = ARM_SIGN(D); \
204 cpu->cpsr.z = !(D); \
205 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
206 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
207 }
208
209#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 cpu->cpsr.n = ARM_SIGN(D); \
215 cpu->cpsr.z = !(D); \
216 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
217 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
218 }
219
220#define ARM_NEUTRAL_S(M, N, D) \
221 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
222 cpu->cpsr = cpu->spsr; \
223 _ARMReadCPSR(cpu); \
224 } else { \
225 cpu->cpsr.n = ARM_SIGN(D); \
226 cpu->cpsr.z = !(D); \
227 cpu->cpsr.c = cpu->shifterCarryOut; \
228 }
229
230#define ARM_NEUTRAL_HI_S(DLO, DHI) \
231 cpu->cpsr.n = ARM_SIGN(DHI); \
232 cpu->cpsr.z = !((DHI) | (DLO));
233
234#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
235#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
236#define ADDR_MODE_2_ADDRESS (address)
237#define ADDR_MODE_2_RN (cpu->gprs[rn])
238#define ADDR_MODE_2_RM (cpu->gprs[rm])
239#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
240#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
241#define ADDR_MODE_2_WRITEBACK(ADDR) \
242 cpu->gprs[rn] = ADDR; \
243 if (UNLIKELY(rn == ARM_PC)) { \
244 ARM_WRITE_PC; \
245 }
246
247#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
248#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
249#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
250#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
251
252#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
253#define ADDR_MODE_3_RN ADDR_MODE_2_RN
254#define ADDR_MODE_3_RM ADDR_MODE_2_RM
255#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
256#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
257#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
258
259#define ADDR_MODE_4_WRITEBACK_LDM \
260 if (!((1 << rn) & rs)) { \
261 cpu->gprs[rn] = address; \
262 }
263
264#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
265
266#define ARM_LOAD_POST_BODY \
267 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
268 if (rd == ARM_PC) { \
269 ARM_WRITE_PC; \
270 }
271
272#define ARM_STORE_POST_BODY \
273 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
274
275#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
276 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
277 int currentCycles = ARM_PREFETCH_CYCLES; \
278 BODY; \
279 cpu->cycles += currentCycles; \
280 }
281
282#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
283 DEFINE_INSTRUCTION_ARM(NAME, \
284 int rd = (opcode >> 12) & 0xF; \
285 int rn = (opcode >> 16) & 0xF; \
286 UNUSED(rn); \
287 SHIFTER(cpu, opcode); \
288 BODY; \
289 S_BODY; \
290 if (rd == ARM_PC) { \
291 if (cpu->executionMode == MODE_ARM) { \
292 ARM_WRITE_PC; \
293 } else { \
294 THUMB_WRITE_PC; \
295 } \
296 })
297
298#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
309
310#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
316
317#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
318 DEFINE_INSTRUCTION_ARM(NAME, \
319 int rd = (opcode >> 16) & 0xF; \
320 int rs = (opcode >> 8) & 0xF; \
321 int rm = opcode & 0xF; \
322 if (rd == ARM_PC) { \
323 return; \
324 } \
325 ARM_WAIT_MUL(cpu->gprs[rs]); \
326 BODY; \
327 S_BODY; \
328 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
329
330#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
331 DEFINE_INSTRUCTION_ARM(NAME, \
332 int rd = (opcode >> 12) & 0xF; \
333 int rdHi = (opcode >> 16) & 0xF; \
334 int rs = (opcode >> 8) & 0xF; \
335 int rm = opcode & 0xF; \
336 if (rdHi == ARM_PC || rd == ARM_PC) { \
337 return; \
338 } \
339 currentCycles += cpu->memory.stall(cpu, WAIT); \
340 BODY; \
341 S_BODY; \
342 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
343
344#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
345 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
346 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
347
348#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
349 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
350 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
351
352#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
353 DEFINE_INSTRUCTION_ARM(NAME, \
354 uint32_t address; \
355 int rn = (opcode >> 16) & 0xF; \
356 int rd = (opcode >> 12) & 0xF; \
357 int rm = opcode & 0xF; \
358 UNUSED(rm); \
359 address = ADDRESS; \
360 WRITEBACK; \
361 BODY;)
362
363#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
370
371#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
382
383#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
396
397#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
400
401#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
402 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
403 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
404 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
405 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
408
409#define ARM_MS_PRE \
410 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
411 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
412
413#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
414
415#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
416 DEFINE_INSTRUCTION_ARM(NAME, \
417 int rn = (opcode >> 16) & 0xF; \
418 int rs = opcode & 0x0000FFFF; \
419 uint32_t address = cpu->gprs[rn]; \
420 S_PRE; \
421 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
422 S_POST; \
423 POST_BODY; \
424 WRITEBACK;)
425
426
427#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
428 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
429 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
430 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
431 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
432 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
433 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
434 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
435 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
436 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
437 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
438 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
439 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
444
445// Begin ALU definitions
446
447DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
448 int32_t n = cpu->gprs[rn];
449 cpu->gprs[rd] = n + cpu->shifterOperand;)
450
451DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
452 int32_t n = cpu->gprs[rn];
453 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
454
455DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
456 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
457
458DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
459 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
460
461DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
462 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
463
464DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
465 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
466
467DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
468 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
469
470DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
471 cpu->gprs[rd] = cpu->shifterOperand;)
472
473DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
474 cpu->gprs[rd] = ~cpu->shifterOperand;)
475
476DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
477 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
478
479DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
480 int32_t n = cpu->gprs[rn];
481 cpu->gprs[rd] = cpu->shifterOperand - n;)
482
483DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
484 int32_t n = cpu->gprs[rn];
485 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
486
487DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
488 int32_t n = cpu->gprs[rn];
489 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
490
491DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
492 int32_t n = cpu->gprs[rn];
493 cpu->gprs[rd] = n - cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
496 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
499 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
500
501// End ALU definitions
502
503// Begin multiply definitions
504
505DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
506DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
507
508DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
509 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
510 int32_t dm = cpu->gprs[rd];
511 int32_t dn = d;
512 cpu->gprs[rd] = dm + dn;
513 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
514 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
515
516DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
517 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
518 cpu->gprs[rd] = d;
519 cpu->gprs[rdHi] = d >> 32;,
520 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
521
522DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
523 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
524 int32_t dm = cpu->gprs[rd];
525 int32_t dn = d;
526 cpu->gprs[rd] = dm + dn;
527 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
528 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
529
530DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
531 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
532 cpu->gprs[rd] = d;
533 cpu->gprs[rdHi] = d >> 32;,
534 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
535
536// End multiply definitions
537
538// Begin load/store definitions
539
540DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
541DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
542DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
543DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
544DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
545DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
546DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
547DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
548
549DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
550 enum PrivilegeMode priv = cpu->privilegeMode;
551 ARMSetPrivilegeMode(cpu, MODE_USER);
552 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
553 ARMSetPrivilegeMode(cpu, priv);
554 cpu->gprs[rd] = r;
555 ARM_LOAD_POST_BODY;)
556
557DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
558 enum PrivilegeMode priv = cpu->privilegeMode;
559 ARMSetPrivilegeMode(cpu, MODE_USER);
560 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
561 ARMSetPrivilegeMode(cpu, priv);
562 cpu->gprs[rd] = r;
563 ARM_LOAD_POST_BODY;)
564
565DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
566 enum PrivilegeMode priv = cpu->privilegeMode;
567 int32_t r = cpu->gprs[rd];
568 ARMSetPrivilegeMode(cpu, MODE_USER);
569 cpu->memory.store8(cpu, address, r, ¤tCycles);
570 ARMSetPrivilegeMode(cpu, priv);
571 ARM_STORE_POST_BODY;)
572
573DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
574 enum PrivilegeMode priv = cpu->privilegeMode;
575 int32_t r = cpu->gprs[rd];
576 ARMSetPrivilegeMode(cpu, MODE_USER);
577 cpu->memory.store32(cpu, address, r, ¤tCycles);
578 ARMSetPrivilegeMode(cpu, priv);
579 ARM_STORE_POST_BODY;)
580
581DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
582 load,
583 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
584 if (rs & 0x8000) {
585 ARM_WRITE_PC;
586 })
587
588DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
589 store,
590 ARM_STORE_POST_BODY;)
591
592DEFINE_INSTRUCTION_ARM(SWP,
593 int rm = opcode & 0xF;
594 int rd = (opcode >> 12) & 0xF;
595 int rn = (opcode >> 16) & 0xF;
596 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
597 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
598 cpu->gprs[rd] = d;)
599
600DEFINE_INSTRUCTION_ARM(SWPB,
601 int rm = opcode & 0xF;
602 int rd = (opcode >> 12) & 0xF;
603 int rn = (opcode >> 16) & 0xF;
604 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
605 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
606 cpu->gprs[rd] = d;)
607
608// End load/store definitions
609
610// Begin branch definitions
611
612DEFINE_INSTRUCTION_ARM(B,
613 int32_t offset = opcode << 8;
614 offset >>= 6;
615 cpu->gprs[ARM_PC] += offset;
616 ARM_WRITE_PC;)
617
618DEFINE_INSTRUCTION_ARM(BL,
619 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
620 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
621 cpu->gprs[ARM_PC] += immediate >> 6;
622 ARM_WRITE_PC;)
623
624DEFINE_INSTRUCTION_ARM(BX,
625 int rm = opcode & 0x0000000F;
626 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
627 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
628 if (cpu->executionMode == MODE_THUMB) {
629 THUMB_WRITE_PC;
630 } else {
631 ARM_WRITE_PC;
632 })
633
634// End branch definitions
635
636// Begin coprocessor definitions
637
638DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
639DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
640DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
641DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
642DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
643
644// Begin miscellaneous definitions
645
646DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
647DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
648
649DEFINE_INSTRUCTION_ARM(MSR,
650 int c = opcode & 0x00010000;
651 int f = opcode & 0x00080000;
652 int32_t operand = cpu->gprs[opcode & 0x0000000F];
653 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
654 if (mask & PSR_USER_MASK) {
655 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
656 }
657 if (mask & PSR_STATE_MASK) {
658 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
659 }
660 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
661 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
662 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
663 }
664 _ARMReadCPSR(cpu);
665 if (cpu->executionMode == MODE_THUMB) {
666 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
667 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
668 } else {
669 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
670 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
671 })
672
673DEFINE_INSTRUCTION_ARM(MSRR,
674 int c = opcode & 0x00010000;
675 int f = opcode & 0x00080000;
676 int32_t operand = cpu->gprs[opcode & 0x0000000F];
677 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
678 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
679 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
680
681DEFINE_INSTRUCTION_ARM(MRS, \
682 int rd = (opcode >> 12) & 0xF; \
683 cpu->gprs[rd] = cpu->cpsr.packed;)
684
685DEFINE_INSTRUCTION_ARM(MRSR, \
686 int rd = (opcode >> 12) & 0xF; \
687 cpu->gprs[rd] = cpu->spsr.packed;)
688
689DEFINE_INSTRUCTION_ARM(MSRI,
690 int c = opcode & 0x00010000;
691 int f = opcode & 0x00080000;
692 int rotate = (opcode & 0x00000F00) >> 7;
693 int32_t operand = ROR(opcode & 0x000000FF, rotate);
694 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
695 if (mask & PSR_USER_MASK) {
696 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
697 }
698 if (mask & PSR_STATE_MASK) {
699 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
700 }
701 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
702 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
703 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
704 }
705 _ARMReadCPSR(cpu);
706 if (cpu->executionMode == MODE_THUMB) {
707 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
708 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
709 } else {
710 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
711 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
712 })
713
714DEFINE_INSTRUCTION_ARM(MSRRI,
715 int c = opcode & 0x00010000;
716 int f = opcode & 0x00080000;
717 int rotate = (opcode & 0x00000F00) >> 7;
718 int32_t operand = ROR(opcode & 0x000000FF, rotate);
719 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
720 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
721 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
722
723DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
724
725const ARMInstruction _armTable[0x1000] = {
726 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
727};