src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/memory.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/macros.h>
10#include <mgba/internal/gba/gba.h>
11#include <mgba/internal/gba/dma.h>
12#include <mgba/internal/gba/io.h>
13#include <mgba/internal/gba/serialize.h>
14#include "gba/hle-bios.h"
15
16#include <mgba-util/math.h>
17#include <mgba-util/memory.h>
18#include <mgba-util/vfs.h>
19
20#define IDLE_LOOP_THRESHOLD 10000
21
22mLOG_DEFINE_CATEGORY(GBA_MEM, "GBA Memory");
23
24static void _pristineCow(struct GBA* gba);
25static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
26
27static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
28static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
29
30static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
31static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
32static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
33static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
34static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
35static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
36
37void GBAMemoryInit(struct GBA* gba) {
38 struct ARMCore* cpu = gba->cpu;
39 cpu->memory.load32 = GBALoad32;
40 cpu->memory.load16 = GBALoad16;
41 cpu->memory.load8 = GBALoad8;
42 cpu->memory.loadMultiple = GBALoadMultiple;
43 cpu->memory.store32 = GBAStore32;
44 cpu->memory.store16 = GBAStore16;
45 cpu->memory.store8 = GBAStore8;
46 cpu->memory.storeMultiple = GBAStoreMultiple;
47 cpu->memory.stall = GBAMemoryStall;
48
49 gba->memory.bios = (uint32_t*) hleBios;
50 gba->memory.fullBios = 0;
51 gba->memory.wram = 0;
52 gba->memory.iwram = 0;
53 gba->memory.rom = 0;
54 gba->memory.romSize = 0;
55 gba->memory.romMask = 0;
56 gba->memory.hw.p = gba;
57
58 int i;
59 for (i = 0; i < 16; ++i) {
60 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
61 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
62 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
63 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
64 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
65 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
66 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
67 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
68 }
69 for (; i < 256; ++i) {
70 gba->memory.waitstatesNonseq16[i] = 0;
71 gba->memory.waitstatesSeq16[i] = 0;
72 gba->memory.waitstatesNonseq32[i] = 0;
73 gba->memory.waitstatesSeq32[i] = 0;
74 }
75
76 gba->memory.activeRegion = -1;
77 cpu->memory.activeRegion = 0;
78 cpu->memory.activeMask = 0;
79 cpu->memory.setActiveRegion = GBASetActiveRegion;
80 cpu->memory.activeSeqCycles32 = 0;
81 cpu->memory.activeSeqCycles16 = 0;
82 cpu->memory.activeNonseqCycles32 = 0;
83 cpu->memory.activeNonseqCycles16 = 0;
84 gba->memory.biosPrefetch = 0;
85 gba->memory.mirroring = false;
86
87 GBADMAInit(gba);
88 GBAVFameInit(&gba->memory.vfame);
89}
90
91void GBAMemoryDeinit(struct GBA* gba) {
92 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
93 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
94 if (gba->memory.rom) {
95 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
96 }
97 GBASavedataUnmask(&gba->memory.savedata);
98 GBASavedataDeinit(&gba->memory.savedata);
99 if (gba->memory.savedata.realVf) {
100 gba->memory.savedata.realVf->close(gba->memory.savedata.realVf);
101 }
102}
103
104void GBAMemoryReset(struct GBA* gba) {
105 if (gba->memory.rom || gba->memory.fullBios) {
106 // Not multiboot
107 if (gba->memory.wram) {
108 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
109 }
110 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
111 }
112
113 if (gba->memory.iwram) {
114 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
115 }
116 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
117
118 memset(gba->memory.io, 0, sizeof(gba->memory.io));
119
120 gba->memory.prefetch = false;
121 gba->memory.lastPrefetchedPc = 0;
122
123 if (!gba->memory.wram || !gba->memory.iwram) {
124 GBAMemoryDeinit(gba);
125 mLOG(GBA_MEM, FATAL, "Could not map memory");
126 }
127
128 GBADMAReset(gba);
129}
130
131static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
132 struct ARMInstructionInfo info;
133 uint32_t nextAddress = address;
134 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
135 if (cpu->executionMode == MODE_THUMB) {
136 while (true) {
137 uint16_t opcode;
138 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
139 ARMDecodeThumb(opcode, &info);
140 switch (info.branchType) {
141 case ARM_BRANCH_NONE:
142 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
143 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
144 gba->idleDetectionStep = -1;
145 return;
146 }
147 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
148 uint32_t offset = 0;
149 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
150 offset = info.memory.offset.immediate;
151 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
152 int reg = info.memory.offset.reg;
153 if (gba->cachedRegisters[reg]) {
154 gba->idleDetectionStep = -1;
155 return;
156 }
157 offset = gba->cachedRegisters[reg];
158 }
159 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
160 loadAddress -= offset;
161 } else {
162 loadAddress += offset;
163 }
164 if ((loadAddress >> BASE_OFFSET) == REGION_IO && !GBAIOIsReadConstant(loadAddress)) {
165 gba->idleDetectionStep = -1;
166 return;
167 }
168 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
169 gba->taintedRegisters[info.op1.reg] = true;
170 } else {
171 switch (info.memory.width) {
172 case 1:
173 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
174 break;
175 case 2:
176 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
177 break;
178 case 4:
179 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
180 break;
181 }
182 }
183 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
184 gba->taintedRegisters[info.op1.reg] = true;
185 }
186 nextAddress += WORD_SIZE_THUMB;
187 break;
188 case ARM_BRANCH:
189 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
190 gba->idleLoop = address;
191 gba->idleOptimization = IDLE_LOOP_REMOVE;
192 }
193 gba->idleDetectionStep = -1;
194 return;
195 default:
196 gba->idleDetectionStep = -1;
197 return;
198 }
199 }
200 } else {
201 gba->idleDetectionStep = -1;
202 }
203}
204
205static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
206 struct GBA* gba = (struct GBA*) cpu->master;
207 struct GBAMemory* memory = &gba->memory;
208
209 int newRegion = address >> BASE_OFFSET;
210 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
211 if (address == gba->idleLoop) {
212 if (gba->haltPending) {
213 gba->haltPending = false;
214 GBAHalt(gba);
215 } else {
216 gba->haltPending = true;
217 }
218 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
219 if (address == gba->lastJump) {
220 switch (gba->idleDetectionStep) {
221 case 0:
222 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
223 ++gba->idleDetectionStep;
224 break;
225 case 1:
226 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
227 gba->idleDetectionStep = -1;
228 ++gba->idleDetectionFailures;
229 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
230 gba->idleOptimization = IDLE_LOOP_IGNORE;
231 }
232 break;
233 }
234 _analyzeForIdleLoop(gba, cpu, address);
235 break;
236 }
237 } else {
238 gba->idleDetectionStep = 0;
239 }
240 }
241 }
242
243 gba->lastJump = address;
244 memory->lastPrefetchedPc = 0;
245 if (newRegion == memory->activeRegion) {
246 if (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize) {
247 return;
248 }
249 if (memory->mirroring && (address & memory->romMask) < memory->romSize) {
250 return;
251 }
252 }
253
254 if (memory->activeRegion == REGION_BIOS) {
255 memory->biosPrefetch = cpu->prefetch[1];
256 }
257 memory->activeRegion = newRegion;
258 switch (newRegion) {
259 case REGION_BIOS:
260 cpu->memory.activeRegion = memory->bios;
261 cpu->memory.activeMask = SIZE_BIOS - 1;
262 break;
263 case REGION_WORKING_RAM:
264 cpu->memory.activeRegion = memory->wram;
265 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
266 break;
267 case REGION_WORKING_IRAM:
268 cpu->memory.activeRegion = memory->iwram;
269 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
270 break;
271 case REGION_PALETTE_RAM:
272 cpu->memory.activeRegion = (uint32_t*) gba->video.palette;
273 cpu->memory.activeMask = SIZE_PALETTE_RAM - 1;
274 break;
275 case REGION_VRAM:
276 if (address & 0x10000) {
277 cpu->memory.activeRegion = (uint32_t*) &gba->video.renderer->vram[0x8000];
278 cpu->memory.activeMask = 0x00007FFF;
279 } else {
280 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
281 cpu->memory.activeMask = 0x0000FFFF;
282 }
283 break;
284 case REGION_OAM:
285 cpu->memory.activeRegion = (uint32_t*) gba->video.oam.raw;
286 cpu->memory.activeMask = SIZE_OAM - 1;
287 break;
288 case REGION_CART0:
289 case REGION_CART0_EX:
290 case REGION_CART1:
291 case REGION_CART1_EX:
292 case REGION_CART2:
293 case REGION_CART2_EX:
294 cpu->memory.activeRegion = memory->rom;
295 cpu->memory.activeMask = memory->romMask;
296 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
297 break;
298 }
299 // Fall through
300 default:
301 memory->activeRegion = -1;
302 cpu->memory.activeRegion = _deadbeef;
303 cpu->memory.activeMask = 0;
304 if (gba->yankedRomSize || !gba->hardCrash) {
305 mLOG(GBA_MEM, GAME_ERROR, "Jumped to invalid address: %08X", address);
306 } else if (gba->coreCallbacks && gba->coreCallbacks->coreCrashed) {
307 mLOG(GBA_MEM, GAME_ERROR, "Jumped to invalid address: %08X", address);
308 gba->coreCallbacks->coreCrashed(gba->coreCallbacks->context);
309 } else {
310 mLOG(GBA_MEM, FATAL, "Jumped to invalid address: %08X", address);
311 }
312 return;
313 }
314 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
315 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
316 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
317 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
318}
319
320#define LOAD_BAD \
321 if (gba->performingDMA) { \
322 value = gba->bus; \
323 } else { \
324 value = cpu->prefetch[1]; \
325 if (cpu->executionMode == MODE_THUMB) { \
326 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
327 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
328 case REGION_BIOS: \
329 case REGION_OAM: \
330 /* This isn't right half the time, but we don't have $+6 handy */ \
331 value <<= 16; \
332 value |= cpu->prefetch[0]; \
333 break; \
334 case REGION_WORKING_IRAM: \
335 /* This doesn't handle prefetch clobbering */ \
336 if (cpu->gprs[ARM_PC] & 2) { \
337 value |= cpu->prefetch[0] << 16; \
338 } else { \
339 value <<= 16; \
340 value |= cpu->prefetch[0]; \
341 } \
342 default: \
343 value |= value << 16; \
344 } \
345 } \
346 }
347
348#define LOAD_BIOS \
349 if (address < SIZE_BIOS) { \
350 if (memory->activeRegion == REGION_BIOS) { \
351 LOAD_32(value, address & -4, memory->bios); \
352 } else { \
353 mLOG(GBA_MEM, GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
354 value = memory->biosPrefetch; \
355 } \
356 } else { \
357 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
358 LOAD_BAD; \
359 }
360
361#define LOAD_WORKING_RAM \
362 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
363 wait += waitstatesRegion[REGION_WORKING_RAM];
364
365#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
366#define LOAD_IO value = GBAIORead(gba, address & OFFSET_MASK & ~2) | (GBAIORead(gba, (address & OFFSET_MASK) | 2) << 16);
367
368#define LOAD_PALETTE_RAM \
369 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
370 wait += waitstatesRegion[REGION_PALETTE_RAM];
371
372#define LOAD_VRAM \
373 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
374 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
375 } else { \
376 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
377 } \
378 wait += waitstatesRegion[REGION_VRAM];
379
380#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
381
382#define LOAD_CART \
383 wait += waitstatesRegion[address >> BASE_OFFSET]; \
384 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
385 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
386 } else if (memory->mirroring && (address & memory->romMask) < memory->romSize) { \
387 LOAD_32(value, address & memory->romMask & -4, memory->rom); \
388 } else if (memory->vfame.cartType) { \
389 value = GBAVFameGetPatternValue(address, 32); \
390 } else { \
391 mLOG(GBA_MEM, GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
392 value = ((address & ~3) >> 1) & 0xFFFF; \
393 value |= (((address & ~3) + 2) >> 1) << 16; \
394 }
395
396#define LOAD_SRAM \
397 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
398 value = GBALoad8(cpu, address, 0); \
399 value |= value << 8; \
400 value |= value << 16;
401
402uint32_t GBALoadBad(struct ARMCore* cpu) {
403 struct GBA* gba = (struct GBA*) cpu->master;
404 uint32_t value = 0;
405 LOAD_BAD;
406 return value;
407}
408
409uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
410 struct GBA* gba = (struct GBA*) cpu->master;
411 struct GBAMemory* memory = &gba->memory;
412 uint32_t value = 0;
413 int wait = 0;
414 char* waitstatesRegion = memory->waitstatesNonseq32;
415
416 switch (address >> BASE_OFFSET) {
417 case REGION_BIOS:
418 LOAD_BIOS;
419 break;
420 case REGION_WORKING_RAM:
421 LOAD_WORKING_RAM;
422 break;
423 case REGION_WORKING_IRAM:
424 LOAD_WORKING_IRAM;
425 break;
426 case REGION_IO:
427 LOAD_IO;
428 break;
429 case REGION_PALETTE_RAM:
430 LOAD_PALETTE_RAM;
431 break;
432 case REGION_VRAM:
433 LOAD_VRAM;
434 break;
435 case REGION_OAM:
436 LOAD_OAM;
437 break;
438 case REGION_CART0:
439 case REGION_CART0_EX:
440 case REGION_CART1:
441 case REGION_CART1_EX:
442 case REGION_CART2:
443 case REGION_CART2_EX:
444 LOAD_CART;
445 break;
446 case REGION_CART_SRAM:
447 case REGION_CART_SRAM_MIRROR:
448 LOAD_SRAM;
449 break;
450 default:
451 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load32: 0x%08X", address);
452 LOAD_BAD;
453 break;
454 }
455
456 if (cycleCounter) {
457 wait += 2;
458 if (address >> BASE_OFFSET < REGION_CART0) {
459 wait = GBAMemoryStall(cpu, wait);
460 }
461 *cycleCounter += wait;
462 }
463 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
464 int rotate = (address & 3) << 3;
465 return ROR(value, rotate);
466}
467
468uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
469 struct GBA* gba = (struct GBA*) cpu->master;
470 struct GBAMemory* memory = &gba->memory;
471 uint32_t value = 0;
472 int wait = 0;
473
474 switch (address >> BASE_OFFSET) {
475 case REGION_BIOS:
476 if (address < SIZE_BIOS) {
477 if (memory->activeRegion == REGION_BIOS) {
478 LOAD_16(value, address & -2, memory->bios);
479 } else {
480 mLOG(GBA_MEM, GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
481 value = (memory->biosPrefetch >> ((address & 2) * 8)) & 0xFFFF;
482 }
483 } else {
484 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load16: 0x%08X", address);
485 LOAD_BAD;
486 value = (value >> ((address & 2) * 8)) & 0xFFFF;
487 }
488 break;
489 case REGION_WORKING_RAM:
490 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
491 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
492 break;
493 case REGION_WORKING_IRAM:
494 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
495 break;
496 case REGION_IO:
497 value = GBAIORead(gba, address & (OFFSET_MASK - 1));
498 break;
499 case REGION_PALETTE_RAM:
500 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
501 break;
502 case REGION_VRAM:
503 if ((address & 0x0001FFFF) < SIZE_VRAM) {
504 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
505 } else {
506 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
507 }
508 break;
509 case REGION_OAM:
510 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
511 break;
512 case REGION_CART0:
513 case REGION_CART0_EX:
514 case REGION_CART1:
515 case REGION_CART1_EX:
516 case REGION_CART2:
517 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
518 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
519 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
520 } else if (memory->mirroring && (address & memory->romMask) < memory->romSize) {
521 LOAD_16(value, address & memory->romMask, memory->rom);
522 } else if (memory->vfame.cartType) {
523 value = GBAVFameGetPatternValue(address, 16);
524 } else {
525 mLOG(GBA_MEM, GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
526 value = (address >> 1) & 0xFFFF;
527 }
528 break;
529 case REGION_CART2_EX:
530 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
531 if (memory->savedata.type == SAVEDATA_EEPROM) {
532 value = GBASavedataReadEEPROM(&memory->savedata);
533 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
534 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
535 } else if (memory->mirroring && (address & memory->romMask) < memory->romSize) {
536 LOAD_16(value, address & memory->romMask, memory->rom);
537 } else if (memory->vfame.cartType) {
538 value = GBAVFameGetPatternValue(address, 16);
539 } else {
540 mLOG(GBA_MEM, GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
541 value = (address >> 1) & 0xFFFF;
542 }
543 break;
544 case REGION_CART_SRAM:
545 case REGION_CART_SRAM_MIRROR:
546 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
547 value = GBALoad8(cpu, address, 0);
548 value |= value << 8;
549 break;
550 default:
551 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load16: 0x%08X", address);
552 LOAD_BAD;
553 value = (value >> ((address & 2) * 8)) & 0xFFFF;
554 break;
555 }
556
557 if (cycleCounter) {
558 wait += 2;
559 if (address >> BASE_OFFSET < REGION_CART0) {
560 wait = GBAMemoryStall(cpu, wait);
561 }
562 *cycleCounter += wait;
563 }
564 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
565 int rotate = (address & 1) << 3;
566 return ROR(value, rotate);
567}
568
569uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
570 struct GBA* gba = (struct GBA*) cpu->master;
571 struct GBAMemory* memory = &gba->memory;
572 uint32_t value = 0;
573 int wait = 0;
574
575 switch (address >> BASE_OFFSET) {
576 case REGION_BIOS:
577 if (address < SIZE_BIOS) {
578 if (memory->activeRegion == REGION_BIOS) {
579 value = ((uint8_t*) memory->bios)[address];
580 } else {
581 mLOG(GBA_MEM, GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
582 value = (memory->biosPrefetch >> ((address & 3) * 8)) & 0xFF;
583 }
584 } else {
585 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load8: 0x%08x", address);
586 LOAD_BAD;
587 value = (value >> ((address & 3) * 8)) & 0xFF;
588 }
589 break;
590 case REGION_WORKING_RAM:
591 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
592 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
593 break;
594 case REGION_WORKING_IRAM:
595 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
596 break;
597 case REGION_IO:
598 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
599 break;
600 case REGION_PALETTE_RAM:
601 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
602 break;
603 case REGION_VRAM:
604 if ((address & 0x0001FFFF) < SIZE_VRAM) {
605 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
606 } else {
607 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
608 }
609 break;
610 case REGION_OAM:
611 value = ((uint8_t*) gba->video.oam.raw)[address & (SIZE_OAM - 1)];
612 break;
613 case REGION_CART0:
614 case REGION_CART0_EX:
615 case REGION_CART1:
616 case REGION_CART1_EX:
617 case REGION_CART2:
618 case REGION_CART2_EX:
619 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
620 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
621 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
622 } else if (memory->mirroring && (address & memory->romMask) < memory->romSize) {
623 value = ((uint8_t*) memory->rom)[address & memory->romMask];
624 } else if (memory->vfame.cartType) {
625 value = GBAVFameGetPatternValue(address, 8);
626 } else {
627 mLOG(GBA_MEM, GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
628 value = (address >> 1) & 0xFF;
629 }
630 break;
631 case REGION_CART_SRAM:
632 case REGION_CART_SRAM_MIRROR:
633 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
634 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
635 mLOG(GBA_MEM, INFO, "Detected SRAM savegame");
636 GBASavedataInitSRAM(&memory->savedata);
637 }
638 if (gba->performingDMA == 1) {
639 break;
640 }
641 if (memory->savedata.type == SAVEDATA_SRAM) {
642 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
643 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
644 value = GBASavedataReadFlash(&memory->savedata, address);
645 } else if (memory->hw.devices & HW_TILT) {
646 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
647 } else {
648 mLOG(GBA_MEM, GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
649 value = 0xFF;
650 }
651 value &= 0xFF;
652 break;
653 default:
654 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Load8: 0x%08x", address);
655 LOAD_BAD;
656 value = (value >> ((address & 3) * 8)) & 0xFF;
657 break;
658 }
659
660 if (cycleCounter) {
661 wait += 2;
662 if (address >> BASE_OFFSET < REGION_CART0) {
663 wait = GBAMemoryStall(cpu, wait);
664 }
665 *cycleCounter += wait;
666 }
667 return value;
668}
669
670#define STORE_WORKING_RAM \
671 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
672 wait += waitstatesRegion[REGION_WORKING_RAM];
673
674#define STORE_WORKING_IRAM \
675 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
676
677#define STORE_IO \
678 GBAIOWrite32(gba, address & (OFFSET_MASK - 3), value);
679
680#define STORE_PALETTE_RAM \
681 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
682 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
683 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
684 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
685
686#define STORE_VRAM \
687 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
688 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
689 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC) + 2); \
690 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC)); \
691 } else { \
692 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
693 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC) + 2); \
694 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC)); \
695 } \
696 wait += waitstatesRegion[REGION_VRAM];
697
698#define STORE_OAM \
699 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
700 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
701 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
702
703#define STORE_CART \
704 wait += waitstatesRegion[address >> BASE_OFFSET]; \
705 mLOG(GBA_MEM, STUB, "Unimplemented memory Store32: 0x%08X", address);
706
707#define STORE_SRAM \
708 if (address & 0x3) { \
709 mLOG(GBA_MEM, GAME_ERROR, "Unaligned SRAM Store32: 0x%08X", address); \
710 value = 0; \
711 } \
712 GBAStore8(cpu, address & ~0x3, value, cycleCounter); \
713 GBAStore8(cpu, (address & ~0x3) | 1, value, cycleCounter); \
714 GBAStore8(cpu, (address & ~0x3) | 2, value, cycleCounter); \
715 GBAStore8(cpu, (address & ~0x3) | 3, value, cycleCounter);
716
717#define STORE_BAD \
718 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Store32: 0x%08X", address);
719
720void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
721 struct GBA* gba = (struct GBA*) cpu->master;
722 struct GBAMemory* memory = &gba->memory;
723 int wait = 0;
724 char* waitstatesRegion = memory->waitstatesNonseq32;
725
726 switch (address >> BASE_OFFSET) {
727 case REGION_WORKING_RAM:
728 STORE_WORKING_RAM;
729 break;
730 case REGION_WORKING_IRAM:
731 STORE_WORKING_IRAM
732 break;
733 case REGION_IO:
734 STORE_IO;
735 break;
736 case REGION_PALETTE_RAM:
737 STORE_PALETTE_RAM;
738 break;
739 case REGION_VRAM:
740 STORE_VRAM;
741 break;
742 case REGION_OAM:
743 STORE_OAM;
744 break;
745 case REGION_CART0:
746 case REGION_CART0_EX:
747 case REGION_CART1:
748 case REGION_CART1_EX:
749 case REGION_CART2:
750 case REGION_CART2_EX:
751 STORE_CART;
752 break;
753 case REGION_CART_SRAM:
754 case REGION_CART_SRAM_MIRROR:
755 STORE_SRAM;
756 break;
757 default:
758 STORE_BAD;
759 break;
760 }
761
762 if (cycleCounter) {
763 ++wait;
764 if (address >> BASE_OFFSET < REGION_CART0) {
765 wait = GBAMemoryStall(cpu, wait);
766 }
767 *cycleCounter += wait;
768 }
769}
770
771void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
772 struct GBA* gba = (struct GBA*) cpu->master;
773 struct GBAMemory* memory = &gba->memory;
774 int wait = 0;
775
776 switch (address >> BASE_OFFSET) {
777 case REGION_WORKING_RAM:
778 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
779 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
780 break;
781 case REGION_WORKING_IRAM:
782 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
783 break;
784 case REGION_IO:
785 GBAIOWrite(gba, address & (OFFSET_MASK - 1), value);
786 break;
787 case REGION_PALETTE_RAM:
788 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
789 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
790 break;
791 case REGION_VRAM:
792 if ((address & 0x0001FFFF) < SIZE_VRAM) {
793 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
794 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
795 } else {
796 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
797 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x00017FFE);
798 }
799 break;
800 case REGION_OAM:
801 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
802 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
803 break;
804 case REGION_CART0:
805 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
806 uint32_t reg = address & 0xFFFFFE;
807 GBAHardwareGPIOWrite(&memory->hw, reg, value);
808 } else {
809 mLOG(GBA_MEM, GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
810 }
811 break;
812 case REGION_CART2_EX:
813 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
814 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
815 GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
816 }
817 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
818 break;
819 case REGION_CART_SRAM:
820 case REGION_CART_SRAM_MIRROR:
821 GBAStore8(cpu, (address & ~0x1), value, cycleCounter);
822 GBAStore8(cpu, (address & ~0x1) | 1, value, cycleCounter);
823 break;
824 default:
825 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Store16: 0x%08X", address);
826 break;
827 }
828
829 if (cycleCounter) {
830 ++wait;
831 if (address >> BASE_OFFSET < REGION_CART0) {
832 wait = GBAMemoryStall(cpu, wait);
833 }
834 *cycleCounter += wait;
835 }
836}
837
838void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
839 struct GBA* gba = (struct GBA*) cpu->master;
840 struct GBAMemory* memory = &gba->memory;
841 int wait = 0;
842
843 switch (address >> BASE_OFFSET) {
844 case REGION_WORKING_RAM:
845 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
846 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
847 break;
848 case REGION_WORKING_IRAM:
849 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
850 break;
851 case REGION_IO:
852 GBAIOWrite8(gba, address & OFFSET_MASK, value);
853 break;
854 case REGION_PALETTE_RAM:
855 GBAStore16(cpu, address & ~1, ((uint8_t) value) | ((uint8_t) value << 8), cycleCounter);
856 break;
857 case REGION_VRAM:
858 if ((address & 0x0001FFFF) >= ((GBARegisterDISPCNTGetMode(gba->memory.io[REG_DISPCNT >> 1]) == 4) ? 0x00014000 : 0x00010000)) {
859 // TODO: check BG mode
860 mLOG(GBA_MEM, GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
861 break;
862 }
863 gba->video.renderer->vram[(address & 0x1FFFE) >> 1] = ((uint8_t) value) | (value << 8);
864 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
865 break;
866 case REGION_OAM:
867 mLOG(GBA_MEM, GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
868 break;
869 case REGION_CART0:
870 mLOG(GBA_MEM, STUB, "Unimplemented memory Store8: 0x%08X", address);
871 break;
872 case REGION_CART_SRAM:
873 case REGION_CART_SRAM_MIRROR:
874 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
875 if (address == SAVEDATA_FLASH_BASE) {
876 mLOG(GBA_MEM, INFO, "Detected Flash savegame");
877 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
878 } else {
879 mLOG(GBA_MEM, INFO, "Detected SRAM savegame");
880 GBASavedataInitSRAM(&memory->savedata);
881 }
882 }
883 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
884 GBASavedataWriteFlash(&memory->savedata, address, value);
885 } else if (memory->savedata.type == SAVEDATA_SRAM) {
886 if (memory->vfame.cartType) {
887 GBAVFameSramWrite(&memory->vfame, address, value, memory->savedata.data);
888 } else {
889 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
890 }
891 memory->savedata.dirty |= SAVEDATA_DIRT_NEW;
892 } else if (memory->hw.devices & HW_TILT) {
893 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
894 } else {
895 mLOG(GBA_MEM, GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
896 }
897 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
898 break;
899 default:
900 mLOG(GBA_MEM, GAME_ERROR, "Bad memory Store8: 0x%08X", address);
901 break;
902 }
903
904 if (cycleCounter) {
905 ++wait;
906 if (address >> BASE_OFFSET < REGION_CART0) {
907 wait = GBAMemoryStall(cpu, wait);
908 }
909 *cycleCounter += wait;
910 }
911}
912
913uint32_t GBAView32(struct ARMCore* cpu, uint32_t address) {
914 struct GBA* gba = (struct GBA*) cpu->master;
915 uint32_t value = 0;
916 address &= ~3;
917 switch (address >> BASE_OFFSET) {
918 case REGION_BIOS:
919 if (address < SIZE_BIOS) {
920 LOAD_32(value, address, gba->memory.bios);
921 }
922 break;
923 case REGION_WORKING_RAM:
924 case REGION_WORKING_IRAM:
925 case REGION_PALETTE_RAM:
926 case REGION_VRAM:
927 case REGION_OAM:
928 case REGION_CART0:
929 case REGION_CART0_EX:
930 case REGION_CART1:
931 case REGION_CART1_EX:
932 case REGION_CART2:
933 case REGION_CART2_EX:
934 value = GBALoad32(cpu, address, 0);
935 break;
936 case REGION_IO:
937 if ((address & OFFSET_MASK) < REG_MAX) {
938 value = gba->memory.io[(address & OFFSET_MASK) >> 1];
939 value |= gba->memory.io[((address & OFFSET_MASK) >> 1) + 1] << 16;
940 }
941 break;
942 case REGION_CART_SRAM:
943 value = GBALoad8(cpu, address, 0);
944 value |= GBALoad8(cpu, address + 1, 0) << 8;
945 value |= GBALoad8(cpu, address + 2, 0) << 16;
946 value |= GBALoad8(cpu, address + 3, 0) << 24;
947 break;
948 default:
949 break;
950 }
951 return value;
952}
953
954uint16_t GBAView16(struct ARMCore* cpu, uint32_t address) {
955 struct GBA* gba = (struct GBA*) cpu->master;
956 uint16_t value = 0;
957 address &= ~1;
958 switch (address >> BASE_OFFSET) {
959 case REGION_BIOS:
960 if (address < SIZE_BIOS) {
961 LOAD_16(value, address, gba->memory.bios);
962 }
963 break;
964 case REGION_WORKING_RAM:
965 case REGION_WORKING_IRAM:
966 case REGION_PALETTE_RAM:
967 case REGION_VRAM:
968 case REGION_OAM:
969 case REGION_CART0:
970 case REGION_CART0_EX:
971 case REGION_CART1:
972 case REGION_CART1_EX:
973 case REGION_CART2:
974 case REGION_CART2_EX:
975 value = GBALoad16(cpu, address, 0);
976 break;
977 case REGION_IO:
978 if ((address & OFFSET_MASK) < REG_MAX) {
979 value = gba->memory.io[(address & OFFSET_MASK) >> 1];
980 }
981 break;
982 case REGION_CART_SRAM:
983 value = GBALoad8(cpu, address, 0);
984 value |= GBALoad8(cpu, address + 1, 0) << 8;
985 break;
986 default:
987 break;
988 }
989 return value;
990}
991
992uint8_t GBAView8(struct ARMCore* cpu, uint32_t address) {
993 struct GBA* gba = (struct GBA*) cpu->master;
994 uint8_t value = 0;
995 switch (address >> BASE_OFFSET) {
996 case REGION_BIOS:
997 if (address < SIZE_BIOS) {
998 value = ((uint8_t*) gba->memory.bios)[address];
999 }
1000 break;
1001 case REGION_WORKING_RAM:
1002 case REGION_WORKING_IRAM:
1003 case REGION_CART0:
1004 case REGION_CART0_EX:
1005 case REGION_CART1:
1006 case REGION_CART1_EX:
1007 case REGION_CART2:
1008 case REGION_CART2_EX:
1009 case REGION_CART_SRAM:
1010 value = GBALoad8(cpu, address, 0);
1011 break;
1012 case REGION_IO:
1013 case REGION_PALETTE_RAM:
1014 case REGION_VRAM:
1015 case REGION_OAM:
1016 value = GBAView16(cpu, address) >> ((address & 1) * 8);
1017 break;
1018 default:
1019 break;
1020 }
1021 return value;
1022}
1023
1024void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
1025 struct GBA* gba = (struct GBA*) cpu->master;
1026 struct GBAMemory* memory = &gba->memory;
1027 int32_t oldValue = -1;
1028
1029 switch (address >> BASE_OFFSET) {
1030 case REGION_WORKING_RAM:
1031 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
1032 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
1033 break;
1034 case REGION_WORKING_IRAM:
1035 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
1036 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
1037 break;
1038 case REGION_IO:
1039 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch32: 0x%08X", address);
1040 break;
1041 case REGION_PALETTE_RAM:
1042 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
1043 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
1044 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
1045 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
1046 break;
1047 case REGION_VRAM:
1048 if ((address & 0x0001FFFF) < SIZE_VRAM) {
1049 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
1050 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
1051 } else {
1052 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
1053 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
1054 }
1055 break;
1056 case REGION_OAM:
1057 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
1058 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
1059 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
1060 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
1061 break;
1062 case REGION_CART0:
1063 case REGION_CART0_EX:
1064 case REGION_CART1:
1065 case REGION_CART1_EX:
1066 case REGION_CART2:
1067 case REGION_CART2_EX:
1068 _pristineCow(gba);
1069 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
1070 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
1071 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1072 }
1073 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
1074 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
1075 break;
1076 case REGION_CART_SRAM:
1077 case REGION_CART_SRAM_MIRROR:
1078 if (memory->savedata.type == SAVEDATA_SRAM) {
1079 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
1080 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
1081 } else {
1082 mLOG(GBA_MEM, GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1083 }
1084 break;
1085 default:
1086 mLOG(GBA_MEM, WARN, "Bad memory Patch16: 0x%08X", address);
1087 break;
1088 }
1089 if (old) {
1090 *old = oldValue;
1091 }
1092}
1093
1094void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
1095 struct GBA* gba = (struct GBA*) cpu->master;
1096 struct GBAMemory* memory = &gba->memory;
1097 int16_t oldValue = -1;
1098
1099 switch (address >> BASE_OFFSET) {
1100 case REGION_WORKING_RAM:
1101 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
1102 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
1103 break;
1104 case REGION_WORKING_IRAM:
1105 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
1106 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
1107 break;
1108 case REGION_IO:
1109 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch16: 0x%08X", address);
1110 break;
1111 case REGION_PALETTE_RAM:
1112 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
1113 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
1114 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
1115 break;
1116 case REGION_VRAM:
1117 if ((address & 0x0001FFFF) < SIZE_VRAM) {
1118 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
1119 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
1120 } else {
1121 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
1122 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
1123 }
1124 break;
1125 case REGION_OAM:
1126 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
1127 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
1128 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
1129 break;
1130 case REGION_CART0:
1131 case REGION_CART0_EX:
1132 case REGION_CART1:
1133 case REGION_CART1_EX:
1134 case REGION_CART2:
1135 case REGION_CART2_EX:
1136 _pristineCow(gba);
1137 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1138 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1139 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1140 }
1141 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
1142 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
1143 break;
1144 case REGION_CART_SRAM:
1145 case REGION_CART_SRAM_MIRROR:
1146 if (memory->savedata.type == SAVEDATA_SRAM) {
1147 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
1148 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
1149 } else {
1150 mLOG(GBA_MEM, GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1151 }
1152 break;
1153 default:
1154 mLOG(GBA_MEM, WARN, "Bad memory Patch16: 0x%08X", address);
1155 break;
1156 }
1157 if (old) {
1158 *old = oldValue;
1159 }
1160}
1161
1162void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
1163 struct GBA* gba = (struct GBA*) cpu->master;
1164 struct GBAMemory* memory = &gba->memory;
1165 int8_t oldValue = -1;
1166
1167 switch (address >> BASE_OFFSET) {
1168 case REGION_WORKING_RAM:
1169 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
1170 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
1171 break;
1172 case REGION_WORKING_IRAM:
1173 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
1174 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
1175 break;
1176 case REGION_IO:
1177 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
1178 break;
1179 case REGION_PALETTE_RAM:
1180 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
1181 break;
1182 case REGION_VRAM:
1183 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
1184 break;
1185 case REGION_OAM:
1186 mLOG(GBA_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
1187 break;
1188 case REGION_CART0:
1189 case REGION_CART0_EX:
1190 case REGION_CART1:
1191 case REGION_CART1_EX:
1192 case REGION_CART2:
1193 case REGION_CART2_EX:
1194 _pristineCow(gba);
1195 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1196 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1197 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1198 }
1199 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1200 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1201 break;
1202 case REGION_CART_SRAM:
1203 case REGION_CART_SRAM_MIRROR:
1204 if (memory->savedata.type == SAVEDATA_SRAM) {
1205 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1206 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1207 } else {
1208 mLOG(GBA_MEM, GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1209 }
1210 break;
1211 default:
1212 mLOG(GBA_MEM, WARN, "Bad memory Patch8: 0x%08X", address);
1213 break;
1214 }
1215 if (old) {
1216 *old = oldValue;
1217 }
1218}
1219
1220#define LDM_LOOP(LDM) \
1221 for (i = 0; i < 16; i += 4) { \
1222 if (UNLIKELY(mask & (1 << i))) { \
1223 LDM; \
1224 cpu->gprs[i] = value; \
1225 ++wait; \
1226 address += 4; \
1227 } \
1228 if (UNLIKELY(mask & (2 << i))) { \
1229 LDM; \
1230 cpu->gprs[i + 1] = value; \
1231 ++wait; \
1232 address += 4; \
1233 } \
1234 if (UNLIKELY(mask & (4 << i))) { \
1235 LDM; \
1236 cpu->gprs[i + 2] = value; \
1237 ++wait; \
1238 address += 4; \
1239 } \
1240 if (UNLIKELY(mask & (8 << i))) { \
1241 LDM; \
1242 cpu->gprs[i + 3] = value; \
1243 ++wait; \
1244 address += 4; \
1245 } \
1246 }
1247
1248uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1249 struct GBA* gba = (struct GBA*) cpu->master;
1250 struct GBAMemory* memory = &gba->memory;
1251 uint32_t value;
1252 char* waitstatesRegion = memory->waitstatesSeq32;
1253
1254 int i;
1255 int offset = 4;
1256 int popcount = 0;
1257 if (direction & LSM_D) {
1258 offset = -4;
1259 popcount = popcount32(mask);
1260 address -= (popcount << 2) - 4;
1261 }
1262
1263 if (direction & LSM_B) {
1264 address += offset;
1265 }
1266
1267 uint32_t addressMisalign = address & 0x3;
1268 int region = address >> BASE_OFFSET;
1269 if (region < REGION_CART_SRAM) {
1270 address &= 0xFFFFFFFC;
1271 }
1272 int wait = memory->waitstatesSeq32[region] - memory->waitstatesNonseq32[region];
1273
1274 switch (region) {
1275 case REGION_BIOS:
1276 LDM_LOOP(LOAD_BIOS);
1277 break;
1278 case REGION_WORKING_RAM:
1279 LDM_LOOP(LOAD_WORKING_RAM);
1280 break;
1281 case REGION_WORKING_IRAM:
1282 LDM_LOOP(LOAD_WORKING_IRAM);
1283 break;
1284 case REGION_IO:
1285 LDM_LOOP(LOAD_IO);
1286 break;
1287 case REGION_PALETTE_RAM:
1288 LDM_LOOP(LOAD_PALETTE_RAM);
1289 break;
1290 case REGION_VRAM:
1291 LDM_LOOP(LOAD_VRAM);
1292 break;
1293 case REGION_OAM:
1294 LDM_LOOP(LOAD_OAM);
1295 break;
1296 case REGION_CART0:
1297 case REGION_CART0_EX:
1298 case REGION_CART1:
1299 case REGION_CART1_EX:
1300 case REGION_CART2:
1301 case REGION_CART2_EX:
1302 LDM_LOOP(LOAD_CART);
1303 break;
1304 case REGION_CART_SRAM:
1305 case REGION_CART_SRAM_MIRROR:
1306 LDM_LOOP(LOAD_SRAM);
1307 break;
1308 default:
1309 LDM_LOOP(LOAD_BAD);
1310 break;
1311 }
1312
1313 if (cycleCounter) {
1314 ++wait;
1315 if (address >> BASE_OFFSET < REGION_CART0) {
1316 wait = GBAMemoryStall(cpu, wait);
1317 }
1318 *cycleCounter += wait;
1319 }
1320
1321 if (direction & LSM_B) {
1322 address -= offset;
1323 }
1324
1325 if (direction & LSM_D) {
1326 address -= (popcount << 2) + 4;
1327 }
1328
1329 return address | addressMisalign;
1330}
1331
1332#define STM_LOOP(STM) \
1333 for (i = 0; i < 16; i += 4) { \
1334 if (UNLIKELY(mask & (1 << i))) { \
1335 value = cpu->gprs[i]; \
1336 STM; \
1337 ++wait; \
1338 address += 4; \
1339 } \
1340 if (UNLIKELY(mask & (2 << i))) { \
1341 value = cpu->gprs[i + 1]; \
1342 STM; \
1343 ++wait; \
1344 address += 4; \
1345 } \
1346 if (UNLIKELY(mask & (4 << i))) { \
1347 value = cpu->gprs[i + 2]; \
1348 STM; \
1349 ++wait; \
1350 address += 4; \
1351 } \
1352 if (UNLIKELY(mask & (8 << i))) { \
1353 value = cpu->gprs[i + 3]; \
1354 if (i + 3 == ARM_PC) { \
1355 value += WORD_SIZE_ARM; \
1356 } \
1357 STM; \
1358 ++wait; \
1359 address += 4; \
1360 } \
1361 }
1362
1363uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1364 struct GBA* gba = (struct GBA*) cpu->master;
1365 struct GBAMemory* memory = &gba->memory;
1366 uint32_t value;
1367 char* waitstatesRegion = memory->waitstatesSeq32;
1368
1369 int i;
1370 int offset = 4;
1371 int popcount = 0;
1372 if (direction & LSM_D) {
1373 offset = -4;
1374 popcount = popcount32(mask);
1375 address -= (popcount << 2) - 4;
1376 }
1377
1378 if (direction & LSM_B) {
1379 address += offset;
1380 }
1381
1382 uint32_t addressMisalign = address & 0x3;
1383 int region = address >> BASE_OFFSET;
1384 if (region < REGION_CART_SRAM) {
1385 address &= 0xFFFFFFFC;
1386 }
1387 int wait = memory->waitstatesSeq32[region] - memory->waitstatesNonseq32[region];
1388
1389 switch (region) {
1390 case REGION_WORKING_RAM:
1391 STM_LOOP(STORE_WORKING_RAM);
1392 break;
1393 case REGION_WORKING_IRAM:
1394 STM_LOOP(STORE_WORKING_IRAM);
1395 break;
1396 case REGION_IO:
1397 STM_LOOP(STORE_IO);
1398 break;
1399 case REGION_PALETTE_RAM:
1400 STM_LOOP(STORE_PALETTE_RAM);
1401 break;
1402 case REGION_VRAM:
1403 STM_LOOP(STORE_VRAM);
1404 break;
1405 case REGION_OAM:
1406 STM_LOOP(STORE_OAM);
1407 break;
1408 case REGION_CART0:
1409 case REGION_CART0_EX:
1410 case REGION_CART1:
1411 case REGION_CART1_EX:
1412 case REGION_CART2:
1413 case REGION_CART2_EX:
1414 STM_LOOP(STORE_CART);
1415 break;
1416 case REGION_CART_SRAM:
1417 case REGION_CART_SRAM_MIRROR:
1418 STM_LOOP(STORE_SRAM);
1419 break;
1420 default:
1421 STM_LOOP(STORE_BAD);
1422 break;
1423 }
1424
1425 if (cycleCounter) {
1426 if (address >> BASE_OFFSET < REGION_CART0) {
1427 wait = GBAMemoryStall(cpu, wait);
1428 }
1429 *cycleCounter += wait;
1430 }
1431
1432 if (direction & LSM_B) {
1433 address -= offset;
1434 }
1435
1436 if (direction & LSM_D) {
1437 address -= (popcount << 2) + 4;
1438 }
1439
1440 return address | addressMisalign;
1441}
1442
1443void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1444 struct GBAMemory* memory = &gba->memory;
1445 struct ARMCore* cpu = gba->cpu;
1446 int sram = parameters & 0x0003;
1447 int ws0 = (parameters & 0x000C) >> 2;
1448 int ws0seq = (parameters & 0x0010) >> 4;
1449 int ws1 = (parameters & 0x0060) >> 5;
1450 int ws1seq = (parameters & 0x0080) >> 7;
1451 int ws2 = (parameters & 0x0300) >> 8;
1452 int ws2seq = (parameters & 0x0400) >> 10;
1453 int prefetch = parameters & 0x4000;
1454
1455 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1456 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1457 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1458 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1459
1460 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1461 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1462 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1463
1464 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1465 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1466 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1467
1468 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1469 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1470 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1471
1472 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1473 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1474 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1475
1476 memory->prefetch = prefetch;
1477
1478 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1479 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1480
1481 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1482 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1483}
1484
1485int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1486 struct GBA* gba = (struct GBA*) cpu->master;
1487 struct GBAMemory* memory = &gba->memory;
1488
1489 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1490 // The wait is the stall
1491 return wait;
1492 }
1493
1494 int32_t previousLoads = 0;
1495
1496 // Don't prefetch too much if we're overlapping with a previous prefetch
1497 uint32_t dist = (memory->lastPrefetchedPc - cpu->gprs[ARM_PC]) >> 1;
1498 if (dist < 8) {
1499 previousLoads = dist;
1500 }
1501
1502 int32_t s = cpu->memory.activeSeqCycles16 + 1;
1503 int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
1504
1505 // Figure out how many sequential loads we can jam in
1506 int32_t stall = s;
1507 int32_t loads = 1;
1508
1509 if (stall > wait && !previousLoads) {
1510 // We might need to stall a bit extra if we haven't finished the first S cycle
1511 wait = stall;
1512 } else {
1513 while (stall < wait) {
1514 stall += s;
1515 ++loads;
1516 }
1517 if (loads + previousLoads > 8) {
1518 loads = 8 - previousLoads;
1519 }
1520 }
1521 // This instruction used to have an N, convert it to an S.
1522 wait -= n2s;
1523
1524 // TODO: Invalidate prefetch on branch
1525 memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * loads;
1526
1527 // The next |loads|S waitstates disappear entirely, so long as they're all in a row
1528 cpu->cycles -= (s - 1) * loads;
1529 return wait;
1530}
1531
1532void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1533 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1534 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1535}
1536
1537void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1538 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1539 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1540}
1541
1542void _pristineCow(struct GBA* gba) {
1543 if (!gba->isPristine) {
1544 return;
1545 }
1546 void* newRom = anonymousMemoryMap(SIZE_CART0);
1547 memcpy(newRom, gba->memory.rom, gba->memory.romSize);
1548 memset(((uint8_t*) newRom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1549 if (gba->romVf) {
1550#ifndef _3DS
1551 gba->romVf->unmap(gba->romVf, gba->memory.rom, gba->memory.romSize);
1552#endif
1553 gba->romVf->close(gba->romVf);
1554 gba->romVf = NULL;
1555 }
1556 gba->memory.rom = newRom;
1557 gba->memory.hw.gpioBase = &((uint16_t*) gba->memory.rom)[GPIO_REG_DATA >> 1];
1558}