src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define APPLY(F, ...) F(__VA_ARGS__)
20
21#define COUNT_1(EMITTER, PREFIX, ...) \
22 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
23 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
24
25#define COUNT_2(EMITTER, PREFIX, ...) \
26 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
27 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
28 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
29
30#define COUNT_3(EMITTER, PREFIX, ...) \
31 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
32 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
33 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
34 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
35 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
36
37#define COUNT_4(EMITTER, PREFIX, ...) \
38 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
39 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
40 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
41 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
42 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
43 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
44 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
45 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
46 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
47
48#define COUNT_5(EMITTER, PREFIX, ...) \
49 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
50 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
51 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
52 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
53 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
54 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
55 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
56 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
57 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
58 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
59 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
60 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
61 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
62 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
63 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
64 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
65 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
66
67#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
68 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
69 BODY; \
70 }
71
72#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
73 DEFINE_INSTRUCTION_THUMB(NAME, \
74 int immediate = IMMEDIATE; \
75 BODY;)
76
77#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
78 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
79
80DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, ARM_STUB)
81DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
82DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
83
84DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
85DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
86DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
87DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, ARM_STUB)
88DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
89DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, ARM_STUB)
90
91#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
92 DEFINE_INSTRUCTION_THUMB(NAME, \
93 int rm = RM; \
94 BODY;)
95
96#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
97 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
98
99DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
100DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
101
102#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
103 DEFINE_INSTRUCTION_THUMB(NAME, \
104 int immediate = IMMEDIATE; \
105 BODY;)
106
107#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
108 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
109
110DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, ARM_STUB)
111DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
112
113#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
114 DEFINE_INSTRUCTION_THUMB(NAME, \
115 int rd = RD; \
116 BODY;)
117
118#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
119 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
120
121DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, ARM_STUB)
122DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
123DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, ARM_STUB)
124DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
125
126#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
127 DEFINE_INSTRUCTION_THUMB(NAME, \
128 int rd = opcode & 0x0007; \
129 int rn = (opcode >> 3) & 0x0007; \
130 BODY;)
131
132DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
133DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
134DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
135DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
136DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
137DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
138DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
139DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
140DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
141DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
142DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
143DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
144DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
145DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
146DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
147DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
148
149#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
150 DEFINE_INSTRUCTION_THUMB(NAME, \
151 int rd = opcode & 0x0007 | H1; \
152 int rm = (opcode >> 3) & 0x0007 | H2; \
153 BODY;)
154
155#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
156 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
157 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
158 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
159 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
160
161DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
162DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
163DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
164
165#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
166 DEFINE_INSTRUCTION_THUMB(NAME, \
167 int rd = RD; \
168 BODY;)
169
170#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
171 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
172
173DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, ARM_STUB)
174DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, ARM_STUB)
175DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, ARM_STUB)
176
177DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
178DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ARM_STUB)
179
180#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
181 DEFINE_INSTRUCTION_THUMB(NAME, \
182 int rm = RM; \
183 BODY;)
184
185#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
186 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
187
188DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
189DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
190DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
191DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
192DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
193DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
194DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
195DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
196
197#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
198 DEFINE_INSTRUCTION_THUMB(NAME, \
199 int rn = (opcode >> 8) & 0x000F; \
200 int rs = RS; \
201 int32_t address = ADDRESS; \
202 int m; \
203 int i; \
204 PRE_BODY; \
205 for LOOP { \
206 if (rs & m) { \
207 BODY; \
208 address OP 4; \
209 } \
210 } \
211 POST_BODY; \
212 WRITEBACK;)
213
214#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
215 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
216
217DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
218 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
219 if (!((1 << rn) & rs)) { \
220 cpu->gprs[rn] = address; \
221 })
222
223DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
224 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
225 cpu->gprs[rn] = address)
226
227#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
228 DEFINE_INSTRUCTION_THUMB(B ## COND, \
229 if (ARM_COND_ ## COND) { \
230 ARM_STUB; \
231 })
232
233DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
234DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
235DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
236DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
237DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
238DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
239DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
240DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
241DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
242DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
243DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
244DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
245DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
246DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
247
248DEFINE_INSTRUCTION_THUMB(ADD7, ARM_STUB)
249DEFINE_INSTRUCTION_THUMB(SUB4, ARM_STUB)
250
251DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
252 opcode & 0x00FF, \
253 cpu->gprs[ARM_SP], \
254 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
255 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
256 +=, \
257 , , \
258 cpu->gprs[ARM_SP] = address)
259
260DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
261 opcode & 0x00FF, \
262 cpu->gprs[ARM_SP], \
263 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
264 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
265 +=, \
266 , \
267 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
268 address += 4;, \
269 cpu->gprs[ARM_SP] = address)
270
271DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
272 opcode & 0x00FF, \
273 cpu->gprs[ARM_SP] - 4, \
274 (m = 0x80, i = 7; m; m >>= 1, --i), \
275 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
276 -=, \
277 , , \
278 cpu->gprs[ARM_SP] = address + 4)
279
280DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
281 opcode & 0x00FF, \
282 cpu->gprs[ARM_SP] - 4, \
283 (m = 0x80, i = 7; m; m >>= 1, --i), \
284 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
285 -=, \
286 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
287 address -= 4;, \
288 , \
289 cpu->gprs[ARM_SP] = address + 4)
290
291DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
292DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
293DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
294DEFINE_INSTRUCTION_THUMB(BL1, \
295 int16_t immediate = (opcode & 0x07FF) << 7; \
296 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 4);)
297
298DEFINE_INSTRUCTION_THUMB(BL2, \
299 uint16_t immediate = (opcode & 0x07FF) << 1; \
300 uint32_t pc = cpu->gprs[ARM_PC]; \
301 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
302 cpu->gprs[ARM_LR] = pc - 1; \
303 THUMB_WRITE_PC;)
304
305DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
306DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
307
308#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
309 EMITTER ## NAME
310
311#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
312 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
313 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
314 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
315 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
316
317#define DUMMY(X, ...) X,
318#define DUMMY_4(...) \
319 DUMMY(__VA_ARGS__) \
320 DUMMY(__VA_ARGS__) \
321 DUMMY(__VA_ARGS__) \
322 DUMMY(__VA_ARGS__)
323
324#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
325 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
326 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
327 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
328 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
329 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
330 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
331 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
332 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
333 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
334 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
335 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
336 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
337 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
338 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
339 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
340 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
341 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
342 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
343 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
344 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
345 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
346 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
347 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
348 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
349 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
350 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
351 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
352 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
353 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
354 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
355 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
356 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
357 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
358 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
359 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
360 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
361 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
362 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
363 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
364 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
365 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
366 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
367 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
368 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
369 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
370 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
371 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
372 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
373 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
374 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
375 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
376 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
377 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
378 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
379 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
380 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
381 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
382 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
383 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
384 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
385 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
386 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
387 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
388 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
389 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
390 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
391 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
392 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
393 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
394 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
395 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
396 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
397 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
398 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
399 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
400 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
401 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
402 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
403 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
404 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
405 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
406 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
407 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
408 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
409 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
410 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
411 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
412 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
413 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
414 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
415 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
416
417static const ThumbInstruction _thumbTable[0x400] = {
418 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
419};