src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
21
22static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
23static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
24
25static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
26static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
27static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
28static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
29static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
30static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
31static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
32
33void GBAMemoryInit(struct GBA* gba) {
34 struct ARMCore* cpu = gba->cpu;
35 cpu->memory.load32 = GBALoad32;
36 cpu->memory.load16 = GBALoad16;
37 cpu->memory.load8 = GBALoad8;
38 cpu->memory.loadMultiple = GBALoadMultiple;
39 cpu->memory.store32 = GBAStore32;
40 cpu->memory.store16 = GBAStore16;
41 cpu->memory.store8 = GBAStore8;
42 cpu->memory.storeMultiple = GBAStoreMultiple;
43
44 gba->memory.bios = (uint32_t*) hleBios;
45 gba->memory.fullBios = 0;
46 gba->memory.wram = 0;
47 gba->memory.iwram = 0;
48 gba->memory.rom = 0;
49 gba->memory.hw.p = gba;
50
51 int i;
52 for (i = 0; i < 16; ++i) {
53 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
54 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
55 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
56 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
57 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
58 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
59 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
60 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
61 }
62 for (; i < 256; ++i) {
63 gba->memory.waitstatesNonseq16[i] = 0;
64 gba->memory.waitstatesSeq16[i] = 0;
65 gba->memory.waitstatesNonseq32[i] = 0;
66 gba->memory.waitstatesSeq32[i] = 0;
67 }
68
69 gba->memory.activeRegion = -1;
70 cpu->memory.activeRegion = 0;
71 cpu->memory.activeMask = 0;
72 cpu->memory.setActiveRegion = GBASetActiveRegion;
73 cpu->memory.activeSeqCycles32 = 0;
74 cpu->memory.activeSeqCycles16 = 0;
75 cpu->memory.activeNonseqCycles32 = 0;
76 cpu->memory.activeNonseqCycles16 = 0;
77 cpu->memory.activeUncachedCycles32 = 0;
78 cpu->memory.activeUncachedCycles16 = 0;
79 gba->memory.biosPrefetch = 0;
80}
81
82void GBAMemoryDeinit(struct GBA* gba) {
83 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
84 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
85 if (gba->memory.rom) {
86 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
87 }
88 GBASavedataDeinit(&gba->memory.savedata);
89}
90
91void GBAMemoryReset(struct GBA* gba) {
92 if (gba->memory.wram) {
93 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
94 }
95 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
96
97 if (gba->memory.iwram) {
98 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
99 }
100 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
101
102 memset(gba->memory.io, 0, sizeof(gba->memory.io));
103 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
104 int i;
105 for (i = 0; i < 4; ++i) {
106 gba->memory.dma[i].count = 0x4000;
107 gba->memory.dma[i].nextEvent = INT_MAX;
108 }
109 gba->memory.dma[3].count = 0x10000;
110 gba->memory.activeDMA = -1;
111 gba->memory.nextDMA = INT_MAX;
112 gba->memory.eventDiff = 0;
113
114 if (!gba->memory.wram || !gba->memory.iwram) {
115 GBAMemoryDeinit(gba);
116 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
117 }
118}
119
120static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
121 struct ARMInstructionInfo info;
122 uint32_t nextAddress = address;
123 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
124 if (cpu->executionMode == MODE_THUMB) {
125 while (true) {
126 uint16_t opcode;
127 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
128 ARMDecodeThumb(opcode, &info);
129 switch (info.branchType) {
130 case ARM_BRANCH_NONE:
131 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
132 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
133 gba->idleDetectionStep = -1;
134 return;
135 }
136 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
137 uint32_t offset = 0;
138 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
139 offset = info.memory.offset.immediate;
140 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
141 int reg = info.memory.offset.reg;
142 if (gba->cachedRegisters[reg]) {
143 gba->idleDetectionStep = -1;
144 return;
145 }
146 offset = gba->cachedRegisters[reg];
147 }
148 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
149 loadAddress -= offset;
150 } else {
151 loadAddress += offset;
152 }
153 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
154 gba->idleDetectionStep = -1;
155 return;
156 }
157 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
158 gba->taintedRegisters[info.op1.reg] = true;
159 } else {
160 switch (info.memory.width) {
161 case 1:
162 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
163 break;
164 case 2:
165 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
166 break;
167 case 4:
168 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
169 break;
170 }
171 }
172 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
173 gba->taintedRegisters[info.op1.reg] = true;
174 }
175 nextAddress += WORD_SIZE_THUMB;
176 break;
177 case ARM_BRANCH:
178 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
179 gba->idleLoop = address;
180 gba->idleOptimization = IDLE_LOOP_REMOVE;
181 }
182 gba->idleDetectionStep = -1;
183 return;
184 default:
185 gba->idleDetectionStep = -1;
186 return;
187 }
188 }
189 } else {
190 gba->idleDetectionStep = -1;
191 }
192}
193
194static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
195 struct GBA* gba = (struct GBA*) cpu->master;
196 struct GBAMemory* memory = &gba->memory;
197
198 int newRegion = address >> BASE_OFFSET;
199 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
200 if (address == gba->idleLoop) {
201 GBAHalt(gba);
202 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
203 if (address == gba->lastJump) {
204 switch (gba->idleDetectionStep) {
205 case 0:
206 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
207 ++gba->idleDetectionStep;
208 break;
209 case 1:
210 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
211 gba->idleDetectionStep = -1;
212 ++gba->idleDetectionFailures;
213 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
214 gba->idleOptimization = IDLE_LOOP_IGNORE;
215 }
216 break;
217 }
218 _analyzeForIdleLoop(gba, cpu, address);
219 break;
220 }
221 } else {
222 gba->idleDetectionStep = 0;
223 }
224 }
225 }
226
227 gba->lastJump = address;
228 if (newRegion == memory->activeRegion) {
229 return;
230 }
231
232 if (memory->activeRegion == REGION_BIOS) {
233 memory->biosPrefetch = cpu->prefetch[1];
234 }
235 memory->activeRegion = newRegion;
236 switch (address & ~OFFSET_MASK) {
237 case BASE_BIOS:
238 cpu->memory.activeRegion = memory->bios;
239 cpu->memory.activeMask = SIZE_BIOS - 1;
240 break;
241 case BASE_WORKING_RAM:
242 cpu->memory.activeRegion = memory->wram;
243 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
244 break;
245 case BASE_WORKING_IRAM:
246 cpu->memory.activeRegion = memory->iwram;
247 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
248 break;
249 case BASE_VRAM:
250 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
251 cpu->memory.activeMask = 0x0000FFFF;
252 break;
253 case BASE_CART0:
254 case BASE_CART0_EX:
255 case BASE_CART1:
256 case BASE_CART1_EX:
257 case BASE_CART2:
258 case BASE_CART2_EX:
259 cpu->memory.activeRegion = memory->rom;
260 cpu->memory.activeMask = SIZE_CART0 - 1;
261 break;
262 default:
263 cpu->memory.activeRegion = _deadbeef;
264 cpu->memory.activeMask = 0;
265 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
266 break;
267 }
268 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
269 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
270 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
271 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
272 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
273 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
274}
275
276#define LOAD_BAD \
277 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
278 if (gba->performingDMA) { \
279 value = gba->bus; \
280 } else { \
281 value = cpu->prefetch[1]; \
282 if (cpu->executionMode == MODE_THUMB) { \
283 value |= value << 16; \
284 } \
285 }
286
287#define LOAD_BIOS \
288 if (address < SIZE_BIOS) { \
289 if (memory->activeRegion == REGION_BIOS) { \
290 LOAD_32(value, address, memory->bios); \
291 } else { \
292 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
293 value = memory->biosPrefetch; \
294 } \
295 } else { \
296 LOAD_BAD; \
297 }
298
299#define LOAD_WORKING_RAM \
300 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
301 wait += waitstatesRegion[REGION_WORKING_RAM];
302
303#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
304#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
305
306#define LOAD_PALETTE_RAM \
307 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
308 ++wait;
309
310#define LOAD_VRAM \
311 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
312 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
313 } else { \
314 LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
315 } \
316 ++wait;
317
318#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
319
320#define LOAD_CART \
321 wait += waitstatesRegion[address >> BASE_OFFSET]; \
322 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
323 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
324 } else { \
325 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
326 value = (address >> 1) & 0xFFFF; \
327 value |= value << 16; \
328 }
329
330#define LOAD_SRAM \
331 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
332 value = GBALoad8(cpu, address, 0); \
333 value |= value << 8; \
334 value |= value << 16;
335
336uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
337 struct GBA* gba = (struct GBA*) cpu->master;
338 struct GBAMemory* memory = &gba->memory;
339 uint32_t value = 0;
340 int wait = 0;
341 char* waitstatesRegion = memory->waitstatesNonseq32;
342
343 switch (address >> BASE_OFFSET) {
344 case REGION_BIOS:
345 LOAD_BIOS;
346 break;
347 case REGION_WORKING_RAM:
348 LOAD_WORKING_RAM;
349 break;
350 case REGION_WORKING_IRAM:
351 LOAD_WORKING_IRAM;
352 break;
353 case REGION_IO:
354 LOAD_IO;
355 break;
356 case REGION_PALETTE_RAM:
357 LOAD_PALETTE_RAM;
358 break;
359 case REGION_VRAM:
360 LOAD_VRAM;
361 break;
362 case REGION_OAM:
363 LOAD_OAM;
364 break;
365 case REGION_CART0:
366 case REGION_CART0_EX:
367 case REGION_CART1:
368 case REGION_CART1_EX:
369 case REGION_CART2:
370 case REGION_CART2_EX:
371 LOAD_CART;
372 break;
373 case REGION_CART_SRAM:
374 case REGION_CART_SRAM_MIRROR:
375 LOAD_SRAM;
376 break;
377 default:
378 LOAD_BAD;
379 break;
380 }
381
382 if (cycleCounter) {
383 *cycleCounter += 2 + wait;
384 }
385 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
386 int rotate = (address & 3) << 3;
387 return ROR(value, rotate);
388}
389
390uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
391 struct GBA* gba = (struct GBA*) cpu->master;
392 struct GBAMemory* memory = &gba->memory;
393 uint32_t value = 0;
394 int wait = 0;
395
396 switch (address >> BASE_OFFSET) {
397 case REGION_BIOS:
398 if (address < SIZE_BIOS) {
399 if (memory->activeRegion == REGION_BIOS) {
400 LOAD_16(value, address, memory->bios);
401 } else {
402 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
403 LOAD_16(value, address & 2, &memory->biosPrefetch);
404 }
405 } else {
406 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
407 if (gba->performingDMA) {
408 LOAD_16(value, address & 2, &gba->bus);
409 } else {
410 uint32_t prefetch = cpu->prefetch[1];
411 if (cpu->executionMode == MODE_THUMB) {
412 prefetch |= prefetch << 16;
413 }
414 LOAD_16(value, address & 2, &prefetch);
415 }
416 }
417 break;
418 case REGION_WORKING_RAM:
419 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
420 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
421 break;
422 case REGION_WORKING_IRAM:
423 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
424 break;
425 case REGION_IO:
426 value = GBAIORead(gba, address & (SIZE_IO - 1));
427 break;
428 case REGION_PALETTE_RAM:
429 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
430 break;
431 case REGION_VRAM:
432 if ((address & 0x0001FFFF) < SIZE_VRAM) {
433 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
434 } else {
435 LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
436 }
437 break;
438 case REGION_OAM:
439 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
440 break;
441 case REGION_CART0:
442 case REGION_CART0_EX:
443 case REGION_CART1:
444 case REGION_CART1_EX:
445 case REGION_CART2:
446 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
447 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
448 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
449 } else {
450 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
451 value = (address >> 1) & 0xFFFF; \
452 }
453 break;
454 case REGION_CART2_EX:
455 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
456 if (memory->savedata.type == SAVEDATA_EEPROM) {
457 value = GBASavedataReadEEPROM(&memory->savedata);
458 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
459 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
460 } else {
461 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
462 value = (address >> 1) & 0xFFFF; \
463 }
464 break;
465 case REGION_CART_SRAM:
466 case REGION_CART_SRAM_MIRROR:
467 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
468 value = GBALoad8(cpu, address, 0);
469 value |= value << 8;
470 break;
471 default:
472 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
473 if (gba->performingDMA) {
474 LOAD_16(value, address & 2, &gba->bus);
475 } else {
476 uint32_t prefetch = cpu->prefetch[1];
477 if (cpu->executionMode == MODE_THUMB) {
478 prefetch |= prefetch << 16;
479 }
480 LOAD_16(value, address & 2, &prefetch);
481 }
482 break;
483 }
484
485 if (cycleCounter) {
486 *cycleCounter += 2 + wait;
487 }
488 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
489 int rotate = (address & 1) << 3;
490 return ROR(value, rotate);
491}
492
493uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
494 struct GBA* gba = (struct GBA*) cpu->master;
495 struct GBAMemory* memory = &gba->memory;
496 uint8_t value = 0;
497 int wait = 0;
498
499 switch (address >> BASE_OFFSET) {
500 case REGION_BIOS:
501 if (address < SIZE_BIOS) {
502 if (memory->activeRegion == REGION_BIOS) {
503 value = ((int8_t*) memory->bios)[address];
504 } else {
505 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
506 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
507 }
508 } else {
509 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
510 if (gba->performingDMA) {
511 value = ((uint8_t*) &gba->bus)[address & 3];
512 } else {
513 uint32_t prefetch = cpu->prefetch[1];
514 if (cpu->executionMode == MODE_THUMB) {
515 prefetch |= prefetch << 16;
516 }
517 value = ((uint8_t*) &prefetch)[address & 3];
518 }
519 }
520 break;
521 case REGION_WORKING_RAM:
522 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
523 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
524 break;
525 case REGION_WORKING_IRAM:
526 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
527 break;
528 case REGION_IO:
529 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
530 break;
531 case REGION_PALETTE_RAM:
532 value = ((int8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
533 break;
534 case REGION_VRAM:
535 if ((address & 0x0001FFFF) < SIZE_VRAM) {
536 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
537 } else {
538 value = ((int8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
539 }
540 break;
541 case REGION_OAM:
542 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
543 break;
544 case REGION_CART0:
545 case REGION_CART0_EX:
546 case REGION_CART1:
547 case REGION_CART1_EX:
548 case REGION_CART2:
549 case REGION_CART2_EX:
550 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
551 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
552 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
553 } else {
554 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
555 value = (address >> 1) & 0xFF; \
556 }
557 break;
558 case REGION_CART_SRAM:
559 case REGION_CART_SRAM_MIRROR:
560 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
561 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
562 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
563 GBASavedataInitSRAM(&memory->savedata);
564 }
565 if (memory->savedata.type == SAVEDATA_SRAM) {
566 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
567 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
568 value = GBASavedataReadFlash(&memory->savedata, address);
569 } else if (memory->hw.devices & HW_TILT) {
570 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
571 } else {
572 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
573 value = 0xFF;
574 }
575 break;
576 default:
577 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
578 if (gba->performingDMA) {
579 value = ((uint8_t*) &gba->bus)[address & 3];
580 } else {
581 uint32_t prefetch = cpu->prefetch[1];
582 if (cpu->executionMode == MODE_THUMB) {
583 prefetch |= prefetch << 16;
584 }
585 value = ((uint8_t*) &prefetch)[address & 3];
586 }
587 break;
588 }
589
590 if (cycleCounter) {
591 *cycleCounter += 2 + wait;
592 }
593 return value;
594}
595
596#define STORE_WORKING_RAM \
597 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
598 wait += waitstatesRegion[REGION_WORKING_RAM];
599
600#define STORE_WORKING_IRAM \
601 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
602
603#define STORE_IO \
604 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
605
606#define STORE_PALETTE_RAM \
607 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
608 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
609 ++wait; \
610 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
611
612#define STORE_VRAM \
613 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
614 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
615 } else { \
616 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
617 } \
618 ++wait;
619
620#define STORE_OAM \
621 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
622 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
623 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
624
625#define STORE_CART \
626 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
627
628#define STORE_SRAM \
629 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
630
631#define STORE_BAD \
632 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
633
634void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
635 struct GBA* gba = (struct GBA*) cpu->master;
636 struct GBAMemory* memory = &gba->memory;
637 int wait = 0;
638 char* waitstatesRegion = memory->waitstatesNonseq32;
639
640 switch (address >> BASE_OFFSET) {
641 case REGION_WORKING_RAM:
642 STORE_WORKING_RAM;
643 break;
644 case REGION_WORKING_IRAM:
645 STORE_WORKING_IRAM
646 break;
647 case REGION_IO:
648 STORE_IO;
649 break;
650 case REGION_PALETTE_RAM:
651 STORE_PALETTE_RAM;
652 break;
653 case REGION_VRAM:
654 STORE_VRAM;
655 break;
656 case REGION_OAM:
657 STORE_OAM;
658 break;
659 case REGION_CART0:
660 case REGION_CART0_EX:
661 case REGION_CART1:
662 case REGION_CART1_EX:
663 case REGION_CART2:
664 case REGION_CART2_EX:
665 STORE_CART;
666 break;
667 case REGION_CART_SRAM:
668 case REGION_CART_SRAM_MIRROR:
669 STORE_SRAM;
670 break;
671 default:
672 STORE_BAD;
673 break;
674 }
675
676 if (cycleCounter) {
677 *cycleCounter += 1 + wait;
678 }
679}
680
681void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
682 struct GBA* gba = (struct GBA*) cpu->master;
683 struct GBAMemory* memory = &gba->memory;
684 int wait = 0;
685
686 switch (address >> BASE_OFFSET) {
687 case REGION_WORKING_RAM:
688 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
689 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
690 break;
691 case REGION_WORKING_IRAM:
692 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
693 break;
694 case REGION_IO:
695 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
696 break;
697 case REGION_PALETTE_RAM:
698 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
699 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
700 break;
701 case REGION_VRAM:
702 if ((address & 0x0001FFFF) < SIZE_VRAM) {
703 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
704 } else {
705 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
706 }
707 break;
708 case REGION_OAM:
709 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
710 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
711 break;
712 case REGION_CART0:
713 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
714 uint32_t reg = address & 0xFFFFFF;
715 GBAHardwareGPIOWrite(&memory->hw, reg, value);
716 } else {
717 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
718 }
719 break;
720 case REGION_CART2_EX:
721 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
722 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
723 GBASavedataInitEEPROM(&memory->savedata);
724 }
725 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
726 break;
727 case REGION_CART_SRAM:
728 case REGION_CART_SRAM_MIRROR:
729 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
730 break;
731 default:
732 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
733 break;
734 }
735
736 if (cycleCounter) {
737 *cycleCounter += 1 + wait;
738 }
739}
740
741void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
742 struct GBA* gba = (struct GBA*) cpu->master;
743 struct GBAMemory* memory = &gba->memory;
744 int wait = 0;
745
746 switch (address >> BASE_OFFSET) {
747 case REGION_WORKING_RAM:
748 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
749 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
750 break;
751 case REGION_WORKING_IRAM:
752 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
753 break;
754 case REGION_IO:
755 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
756 break;
757 case REGION_PALETTE_RAM:
758 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
759 break;
760 case REGION_VRAM:
761 if (address >= 0x06018000) {
762 // TODO: check BG mode
763 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
764 break;
765 }
766 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
767 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
768 break;
769 case REGION_OAM:
770 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
771 break;
772 case REGION_CART0:
773 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
774 break;
775 case REGION_CART_SRAM:
776 case REGION_CART_SRAM_MIRROR:
777 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
778 if (address == SAVEDATA_FLASH_BASE) {
779 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
780 GBASavedataInitFlash(&memory->savedata);
781 } else {
782 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
783 GBASavedataInitSRAM(&memory->savedata);
784 }
785 }
786 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
787 GBASavedataWriteFlash(&memory->savedata, address, value);
788 } else if (memory->savedata.type == SAVEDATA_SRAM) {
789 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
790 } else if (memory->hw.devices & HW_TILT) {
791 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
792 } else {
793 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
794 }
795 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
796 break;
797 default:
798 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
799 break;
800 }
801
802 if (cycleCounter) {
803 *cycleCounter += 1 + wait;
804 }
805}
806
807void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
808 struct GBA* gba = (struct GBA*) cpu->master;
809 struct GBAMemory* memory = &gba->memory;
810 int32_t oldValue = -1;
811
812 switch (address >> BASE_OFFSET) {
813 case REGION_WORKING_RAM:
814 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
815 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
816 break;
817 case REGION_WORKING_IRAM:
818 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
819 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
820 break;
821 case REGION_IO:
822 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
823 break;
824 case REGION_PALETTE_RAM:
825 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
826 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
827 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
828 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
829 break;
830 case REGION_VRAM:
831 if ((address & 0x0001FFFF) < SIZE_VRAM) {
832 LOAD_32(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
833 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
834 } else {
835 LOAD_32(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
836 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
837 }
838 break;
839 case REGION_OAM:
840 LOAD_32(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
841 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
842 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
843 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 1)) + 2) >> 1);
844 break;
845 case REGION_CART0:
846 case REGION_CART0_EX:
847 case REGION_CART1:
848 case REGION_CART1_EX:
849 case REGION_CART2:
850 case REGION_CART2_EX:
851 if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
852 LOAD_32(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
853 STORE_32(value, address & (SIZE_CART0 - 1), gba->memory.rom);
854 } else {
855 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch32: 0x%08X", address);
856 }
857 break;
858 case REGION_CART_SRAM:
859 case REGION_CART_SRAM_MIRROR:
860 if (memory->savedata.type == SAVEDATA_SRAM) {
861 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
862 STORE_32(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
863 } else {
864 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
865 }
866 break;
867 default:
868 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
869 break;
870 }
871 if (old) {
872 *old = oldValue;
873 }
874}
875
876void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
877 struct GBA* gba = (struct GBA*) cpu->master;
878 struct GBAMemory* memory = &gba->memory;
879 int16_t oldValue = -1;
880
881 switch (address >> BASE_OFFSET) {
882 case REGION_WORKING_RAM:
883 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
884 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
885 break;
886 case REGION_WORKING_IRAM:
887 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
888 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
889 break;
890 case REGION_IO:
891 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
892 break;
893 case REGION_PALETTE_RAM:
894 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
895 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
896 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
897 break;
898 case REGION_VRAM:
899 if ((address & 0x0001FFFF) < SIZE_VRAM) {
900 LOAD_16(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
901 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
902 } else {
903 LOAD_16(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
904 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
905 }
906 break;
907 case REGION_OAM:
908 LOAD_16(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
909 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
910 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
911 break;
912 case REGION_CART0:
913 case REGION_CART0_EX:
914 case REGION_CART1:
915 case REGION_CART1_EX:
916 case REGION_CART2:
917 case REGION_CART2_EX:
918 if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
919 LOAD_16(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
920 STORE_16(value, address & (SIZE_CART0 - 1), gba->memory.rom);
921 } else {
922 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
923 }
924 break;
925 case REGION_CART_SRAM:
926 case REGION_CART_SRAM_MIRROR:
927 if (memory->savedata.type == SAVEDATA_SRAM) {
928 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
929 STORE_16(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
930 } else {
931 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
932 }
933 break;
934 default:
935 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
936 break;
937 }
938 if (old) {
939 *old = oldValue;
940 }
941}
942
943#define LDM_LOOP(LDM) \
944 for (i = 0; i < 16; i += 4) { \
945 if (UNLIKELY(mask & (1 << i))) { \
946 LDM; \
947 waitstatesRegion = memory->waitstatesSeq32; \
948 cpu->gprs[i] = value; \
949 ++wait; \
950 address += 4; \
951 } \
952 if (UNLIKELY(mask & (2 << i))) { \
953 LDM; \
954 waitstatesRegion = memory->waitstatesSeq32; \
955 cpu->gprs[i + 1] = value; \
956 ++wait; \
957 address += 4; \
958 } \
959 if (UNLIKELY(mask & (4 << i))) { \
960 LDM; \
961 waitstatesRegion = memory->waitstatesSeq32; \
962 cpu->gprs[i + 2] = value; \
963 ++wait; \
964 address += 4; \
965 } \
966 if (UNLIKELY(mask & (8 << i))) { \
967 LDM; \
968 waitstatesRegion = memory->waitstatesSeq32; \
969 cpu->gprs[i + 3] = value; \
970 ++wait; \
971 address += 4; \
972 } \
973 }
974
975uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
976 struct GBA* gba = (struct GBA*) cpu->master;
977 struct GBAMemory* memory = &gba->memory;
978 uint32_t value;
979 int wait = 0;
980 char* waitstatesRegion = memory->waitstatesNonseq32;
981
982 int i;
983 int offset = 4;
984 int popcount = 0;
985 if (direction & LSM_D) {
986 offset = -4;
987 popcount = _popcount32(mask);
988 address -= (popcount << 2) - 4;
989 }
990
991 if (direction & LSM_B) {
992 address += offset;
993 }
994
995 uint32_t addressMisalign = address & 0x3;
996 address &= 0xFFFFFFFC;
997
998 switch (address >> BASE_OFFSET) {
999 case REGION_BIOS:
1000 LDM_LOOP(LOAD_BIOS);
1001 break;
1002 case REGION_WORKING_RAM:
1003 LDM_LOOP(LOAD_WORKING_RAM);
1004 break;
1005 case REGION_WORKING_IRAM:
1006 LDM_LOOP(LOAD_WORKING_IRAM);
1007 break;
1008 case REGION_IO:
1009 LDM_LOOP(LOAD_IO);
1010 break;
1011 case REGION_PALETTE_RAM:
1012 LDM_LOOP(LOAD_PALETTE_RAM);
1013 break;
1014 case REGION_VRAM:
1015 LDM_LOOP(LOAD_VRAM);
1016 break;
1017 case REGION_OAM:
1018 LDM_LOOP(LOAD_OAM);
1019 break;
1020 case REGION_CART0:
1021 case REGION_CART0_EX:
1022 case REGION_CART1:
1023 case REGION_CART1_EX:
1024 case REGION_CART2:
1025 case REGION_CART2_EX:
1026 LDM_LOOP(LOAD_CART);
1027 break;
1028 case REGION_CART_SRAM:
1029 case REGION_CART_SRAM_MIRROR:
1030 LDM_LOOP(LOAD_SRAM);
1031 break;
1032 default:
1033 LDM_LOOP(LOAD_BAD);
1034 break;
1035 }
1036
1037 if (cycleCounter) {
1038 *cycleCounter += wait;
1039 }
1040
1041 if (direction & LSM_B) {
1042 address -= offset;
1043 }
1044
1045 if (direction & LSM_D) {
1046 address -= (popcount << 2) + 4;
1047 }
1048
1049 return address | addressMisalign;
1050}
1051
1052#define STM_LOOP(STM) \
1053 for (i = 0; i < 16; i += 4) { \
1054 if (UNLIKELY(mask & (1 << i))) { \
1055 value = cpu->gprs[i]; \
1056 STM; \
1057 waitstatesRegion = memory->waitstatesSeq32; \
1058 ++wait; \
1059 address += 4; \
1060 } \
1061 if (UNLIKELY(mask & (2 << i))) { \
1062 value = cpu->gprs[i + 1]; \
1063 STM; \
1064 waitstatesRegion = memory->waitstatesSeq32; \
1065 ++wait; \
1066 address += 4; \
1067 } \
1068 if (UNLIKELY(mask & (4 << i))) { \
1069 value = cpu->gprs[i + 2]; \
1070 STM; \
1071 waitstatesRegion = memory->waitstatesSeq32; \
1072 ++wait; \
1073 address += 4; \
1074 } \
1075 if (UNLIKELY(mask & (8 << i))) { \
1076 value = cpu->gprs[i + 3]; \
1077 STM; \
1078 waitstatesRegion = memory->waitstatesSeq32; \
1079 ++wait; \
1080 address += 4; \
1081 } \
1082 }
1083
1084uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1085 struct GBA* gba = (struct GBA*) cpu->master;
1086 struct GBAMemory* memory = &gba->memory;
1087 uint32_t value;
1088 int wait = 0;
1089 char* waitstatesRegion = memory->waitstatesNonseq32;
1090
1091 int i;
1092 int offset = 4;
1093 int popcount = 0;
1094 if (direction & LSM_D) {
1095 offset = -4;
1096 popcount = _popcount32(mask);
1097 address -= (popcount << 2) - 4;
1098 }
1099
1100 if (direction & LSM_B) {
1101 address += offset;
1102 }
1103
1104 uint32_t addressMisalign = address & 0x3;
1105 address &= 0xFFFFFFFC;
1106
1107 switch (address >> BASE_OFFSET) {
1108 case REGION_WORKING_RAM:
1109 STM_LOOP(STORE_WORKING_RAM);
1110 break;
1111 case REGION_WORKING_IRAM:
1112 STM_LOOP(STORE_WORKING_IRAM);
1113 break;
1114 case REGION_IO:
1115 STM_LOOP(STORE_IO);
1116 break;
1117 case REGION_PALETTE_RAM:
1118 STM_LOOP(STORE_PALETTE_RAM);
1119 break;
1120 case REGION_VRAM:
1121 STM_LOOP(STORE_VRAM);
1122 break;
1123 case REGION_OAM:
1124 STM_LOOP(STORE_OAM);
1125 break;
1126 case REGION_CART0:
1127 case REGION_CART0_EX:
1128 case REGION_CART1:
1129 case REGION_CART1_EX:
1130 case REGION_CART2:
1131 case REGION_CART2_EX:
1132 STM_LOOP(STORE_CART);
1133 break;
1134 case REGION_CART_SRAM:
1135 case REGION_CART_SRAM_MIRROR:
1136 STM_LOOP(STORE_SRAM);
1137 break;
1138 default:
1139 STM_LOOP(STORE_BAD);
1140 break;
1141 }
1142
1143 if (cycleCounter) {
1144 *cycleCounter += wait;
1145 }
1146
1147 if (direction & LSM_B) {
1148 address -= offset;
1149 }
1150
1151 if (direction & LSM_D) {
1152 address -= (popcount << 2) + 4;
1153 }
1154
1155 return address | addressMisalign;
1156}
1157
1158void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1159 struct GBAMemory* memory = &gba->memory;
1160 struct ARMCore* cpu = gba->cpu;
1161 int sram = parameters & 0x0003;
1162 int ws0 = (parameters & 0x000C) >> 2;
1163 int ws0seq = (parameters & 0x0010) >> 4;
1164 int ws1 = (parameters & 0x0060) >> 5;
1165 int ws1seq = (parameters & 0x0080) >> 7;
1166 int ws2 = (parameters & 0x0300) >> 8;
1167 int ws2seq = (parameters & 0x0400) >> 10;
1168 int prefetch = parameters & 0x4000;
1169
1170 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1171 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1172 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1173 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1174
1175 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1176 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1177 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1178
1179 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1180 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1181 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1182
1183 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1184 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1185 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1186
1187 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1188 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1189 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1190
1191 if (!prefetch) {
1192 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1193 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1194 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1195
1196 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1197 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1198 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1199
1200 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1201 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1202 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1203
1204 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1205 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1206 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1207 } else {
1208 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1209 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1210 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1211
1212 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1213 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1214 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1215
1216 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1217 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1218 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1219
1220 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1221 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1222 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1223 }
1224
1225 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1226 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1227
1228 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1229 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1230
1231 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1232 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1233}
1234
1235void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1236 struct GBAMemory* memory = &gba->memory;
1237 memory->dma[dma].source = address & 0x0FFFFFFE;
1238}
1239
1240void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1241 struct GBAMemory* memory = &gba->memory;
1242 memory->dma[dma].dest = address & 0x0FFFFFFE;
1243}
1244
1245void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1246 struct GBAMemory* memory = &gba->memory;
1247 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1248}
1249
1250uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1251 struct GBAMemory* memory = &gba->memory;
1252 struct GBADMA* currentDma = &memory->dma[dma];
1253 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1254 currentDma->reg = control;
1255
1256 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1257 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1258 }
1259
1260 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1261 currentDma->nextSource = currentDma->source;
1262 currentDma->nextDest = currentDma->dest;
1263 currentDma->nextCount = currentDma->count;
1264 GBAMemoryScheduleDMA(gba, dma, currentDma);
1265 }
1266 // If the DMA has already occurred, this value might have changed since the function started
1267 return currentDma->reg;
1268};
1269
1270void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1271 struct ARMCore* cpu = gba->cpu;
1272 switch (GBADMARegisterGetTiming(info->reg)) {
1273 case DMA_TIMING_NOW:
1274 info->nextEvent = cpu->cycles;
1275 GBAMemoryUpdateDMAs(gba, 0);
1276 break;
1277 case DMA_TIMING_HBLANK:
1278 // Handled implicitly
1279 info->nextEvent = INT_MAX;
1280 break;
1281 case DMA_TIMING_VBLANK:
1282 // Handled implicitly
1283 info->nextEvent = INT_MAX;
1284 break;
1285 case DMA_TIMING_CUSTOM:
1286 info->nextEvent = INT_MAX;
1287 switch (number) {
1288 case 0:
1289 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1290 break;
1291 case 1:
1292 case 2:
1293 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1294 break;
1295 case 3:
1296 // GBAVideoScheduleVCaptureDma(dma, info);
1297 break;
1298 }
1299 }
1300}
1301
1302void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1303 struct GBAMemory* memory = &gba->memory;
1304 struct GBADMA* dma;
1305 int i;
1306 for (i = 0; i < 4; ++i) {
1307 dma = &memory->dma[i];
1308 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1309 dma->nextEvent = cycles;
1310 }
1311 }
1312 GBAMemoryUpdateDMAs(gba, 0);
1313}
1314
1315void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1316 struct GBAMemory* memory = &gba->memory;
1317 struct GBADMA* dma;
1318 int i;
1319 for (i = 0; i < 4; ++i) {
1320 dma = &memory->dma[i];
1321 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1322 dma->nextEvent = cycles;
1323 }
1324 }
1325 GBAMemoryUpdateDMAs(gba, 0);
1326}
1327
1328int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1329 struct GBAMemory* memory = &gba->memory;
1330 if (memory->nextDMA == INT_MAX) {
1331 return INT_MAX;
1332 }
1333 memory->nextDMA -= cycles;
1334 memory->eventDiff += cycles;
1335 if (memory->nextDMA <= 0) {
1336 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1337 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1338 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1339 memory->eventDiff = 0;
1340 }
1341 return memory->nextDMA;
1342}
1343
1344void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1345 int i;
1346 struct GBAMemory* memory = &gba->memory;
1347 struct ARMCore* cpu = gba->cpu;
1348 memory->activeDMA = -1;
1349 memory->nextDMA = INT_MAX;
1350 for (i = 3; i >= 0; --i) {
1351 struct GBADMA* dma = &memory->dma[i];
1352 if (dma->nextEvent != INT_MAX) {
1353 dma->nextEvent -= cycles;
1354 if (GBADMARegisterIsEnable(dma->reg)) {
1355 memory->activeDMA = i;
1356 memory->nextDMA = dma->nextEvent;
1357 }
1358 }
1359 }
1360 if (memory->nextDMA < cpu->nextEvent) {
1361 cpu->nextEvent = memory->nextDMA;
1362 }
1363}
1364
1365void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1366 struct GBAMemory* memory = &gba->memory;
1367 struct ARMCore* cpu = gba->cpu;
1368 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1369 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1370 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1371 int32_t wordsRemaining = info->nextCount;
1372 uint32_t source = info->nextSource;
1373 uint32_t dest = info->nextDest;
1374 uint32_t sourceRegion = source >> BASE_OFFSET;
1375 uint32_t destRegion = dest >> BASE_OFFSET;
1376 int32_t cycles = 2;
1377
1378 if (source == info->source) {
1379 // TODO: support 4 cycles for ROM access
1380 cycles += 2;
1381 if (width == 4) {
1382 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1383 source &= 0xFFFFFFFC;
1384 dest &= 0xFFFFFFFC;
1385 } else {
1386 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1387 }
1388 } else {
1389 if (width == 4) {
1390 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1391 } else {
1392 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1393 }
1394 }
1395
1396 gba->performingDMA = true;
1397 int32_t word;
1398 if (width == 4) {
1399 word = cpu->memory.load32(cpu, source, 0);
1400 gba->bus = word;
1401 cpu->memory.store32(cpu, dest, word, 0);
1402 source += sourceOffset;
1403 dest += destOffset;
1404 --wordsRemaining;
1405 } else {
1406 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1407 word = GBASavedataReadEEPROM(&memory->savedata);
1408 gba->bus = word | (word << 16);
1409 cpu->memory.store16(cpu, dest, word, 0);
1410 source += sourceOffset;
1411 dest += destOffset;
1412 --wordsRemaining;
1413 } else if (destRegion == REGION_CART2_EX) {
1414 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1415 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1416 GBASavedataInitEEPROM(&memory->savedata);
1417 }
1418 word = cpu->memory.load16(cpu, source, 0);
1419 gba->bus = word | (word << 16);
1420 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1421 source += sourceOffset;
1422 dest += destOffset;
1423 --wordsRemaining;
1424 } else {
1425 word = cpu->memory.load16(cpu, source, 0);
1426 gba->bus = word | (word << 16);
1427 cpu->memory.store16(cpu, dest, word, 0);
1428 source += sourceOffset;
1429 dest += destOffset;
1430 --wordsRemaining;
1431 }
1432 }
1433 gba->performingDMA = false;
1434
1435 if (!wordsRemaining) {
1436 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1437 info->reg = GBADMARegisterClearEnable(info->reg);
1438 info->nextEvent = INT_MAX;
1439
1440 // Clear the enable bit in memory
1441 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1442 } else {
1443 info->nextCount = info->count;
1444 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1445 info->nextDest = info->dest;
1446 }
1447 GBAMemoryScheduleDMA(gba, number, info);
1448 }
1449 if (GBADMARegisterIsDoIRQ(info->reg)) {
1450 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1451 }
1452 } else {
1453 info->nextDest = dest;
1454 info->nextCount = wordsRemaining;
1455 }
1456 info->nextSource = source;
1457
1458 if (info->nextEvent != INT_MAX) {
1459 info->nextEvent += cycles;
1460 }
1461 cpu->cycles += cycles;
1462}
1463
1464void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1465 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1466 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1467}
1468
1469void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1470 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1471 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1472}
1473
1474uint32_t _popcount32(unsigned bits) {
1475 bits = bits - ((bits >> 1) & 0x55555555);
1476 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1477 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1478}