all repos — mgba @ 1c93b75b7e22fbe1b00da0214305c1bf2a9d0890

mGBA Game Boy Advance Emulator

src/gba/dma.c (view raw)

  1/* Copyright (c) 2013-2015 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#include "dma.h"
  7
  8#include "gba/gba.h"
  9#include "gba/io.h"
 10
 11static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
 12
 13static void GBADMAService(struct GBA* gba, int number, struct GBADMA* info);
 14
 15static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
 16
 17void GBADMAInit(struct GBA* gba) {
 18	gba->memory.dmaEvent.name = "GBA DMA";
 19	gba->memory.dmaEvent.callback = _dmaEvent;
 20	gba->memory.dmaEvent.context = gba;
 21	gba->memory.dmaEvent.priority = 0x40;
 22}
 23
 24void GBADMAReset(struct GBA* gba) {
 25	memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
 26	int i;
 27	for (i = 0; i < 4; ++i) {
 28		gba->memory.dma[i].count = 0x4000;
 29	}
 30	gba->memory.dma[3].count = 0x10000;
 31	gba->memory.activeDMA = -1;
 32}
 33static bool _isValidDMASAD(int dma, uint32_t address) {
 34	if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
 35		return false;
 36	}
 37	return address >= BASE_WORKING_RAM;
 38}
 39
 40static bool _isValidDMADAD(int dma, uint32_t address) {
 41	return dma == 3 || address < BASE_CART0;
 42}
 43
 44uint32_t GBADMAWriteSAD(struct GBA* gba, int dma, uint32_t address) {
 45	struct GBAMemory* memory = &gba->memory;
 46	address &= 0x0FFFFFFE;
 47	if (_isValidDMASAD(dma, address)) {
 48		memory->dma[dma].source = address;
 49	}
 50	return memory->dma[dma].source;
 51}
 52
 53uint32_t GBADMAWriteDAD(struct GBA* gba, int dma, uint32_t address) {
 54	struct GBAMemory* memory = &gba->memory;
 55	address &= 0x0FFFFFFE;
 56	if (_isValidDMADAD(dma, address)) {
 57		memory->dma[dma].dest = address;
 58	}
 59	return memory->dma[dma].dest;
 60}
 61
 62void GBADMAWriteCNT_LO(struct GBA* gba, int dma, uint16_t count) {
 63	struct GBAMemory* memory = &gba->memory;
 64	memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
 65}
 66
 67uint16_t GBADMAWriteCNT_HI(struct GBA* gba, int dma, uint16_t control) {
 68	struct GBAMemory* memory = &gba->memory;
 69	struct GBADMA* currentDma = &memory->dma[dma];
 70	int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
 71	if (dma < 3) {
 72		control &= 0xF7E0;
 73	} else {
 74		control &= 0xFFE0;
 75	}
 76	currentDma->reg = control;
 77
 78	if (GBADMARegisterIsDRQ(currentDma->reg)) {
 79		mLOG(GBA_MEM, STUB, "DRQ not implemented");
 80	}
 81
 82	if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
 83		currentDma->nextSource = currentDma->source;
 84		currentDma->nextDest = currentDma->dest;
 85		GBADMASchedule(gba, dma, currentDma);
 86	}
 87	// If the DMA has already occurred, this value might have changed since the function started
 88	return currentDma->reg;
 89};
 90
 91void GBADMASchedule(struct GBA* gba, int number, struct GBADMA* info) {
 92	switch (GBADMARegisterGetTiming(info->reg)) {
 93	case DMA_TIMING_NOW:
 94		info->when = mTimingCurrentTime(&gba->timing) + 2 + 1; // XXX: Account for I cycle when writing
 95		info->nextCount = info->count;
 96		break;
 97	case DMA_TIMING_HBLANK:
 98	case DMA_TIMING_VBLANK:
 99		// Handled implicitly
100		return;
101	case DMA_TIMING_CUSTOM:
102		switch (number) {
103		case 0:
104			mLOG(GBA_MEM, WARN, "Discarding invalid DMA0 scheduling");
105			return;
106		case 1:
107		case 2:
108			GBAAudioScheduleFifoDma(&gba->audio, number, info);
109			break;
110		case 3:
111			// GBAVideoScheduleVCaptureDma(dma, info);
112			break;
113		}
114	}
115	GBADMAUpdate(gba);
116}
117
118void GBADMARunHblank(struct GBA* gba, int32_t cycles) {
119	struct GBAMemory* memory = &gba->memory;
120	struct GBADMA* dma;
121	int i;
122	for (i = 0; i < 4; ++i) {
123		dma = &memory->dma[i];
124		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK && !dma->hasStarted) {
125			dma->when = mTimingCurrentTime(&gba->timing) + 2 + cycles;
126			dma->nextCount = dma->count;
127		}
128	}
129	GBADMAUpdate(gba);
130}
131
132void GBADMARunVblank(struct GBA* gba, int32_t cycles) {
133	struct GBAMemory* memory = &gba->memory;
134	struct GBADMA* dma;
135	int i;
136	for (i = 0; i < 4; ++i) {
137		dma = &memory->dma[i];
138		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK && !dma->hasStarted) {
139			dma->when = mTimingCurrentTime(&gba->timing) + 2 + cycles;
140			dma->nextCount = dma->count;
141		}
142	}
143	GBADMAUpdate(gba);
144}
145
146void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
147	UNUSED(timing);
148	UNUSED(cyclesLate);
149	struct GBA* gba = context;
150	struct GBAMemory* memory = &gba->memory;
151	struct GBADMA* dma = &memory->dma[memory->activeDMA];
152	GBADMAService(gba, memory->activeDMA, dma);
153}
154
155void GBADMAUpdate(struct GBA* gba) {
156	int i;
157	struct GBAMemory* memory = &gba->memory;
158	memory->activeDMA = -1;
159	uint32_t currentTime = mTimingCurrentTime(&gba->timing);
160	for (i = 3; i >= 0; --i) {
161		struct GBADMA* dma = &memory->dma[i];
162		if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
163			if (dma->when < currentTime) {
164				dma->when = currentTime;
165			}
166			memory->activeDMA = i;
167		}
168	}
169
170	if (memory->activeDMA >= 0) {
171		mTimingDeschedule(&gba->timing, &memory->dmaEvent);
172		mTimingSchedule(&gba->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
173	} else {
174		gba->cpuBlocked = false;
175	}
176}
177
178void GBADMAService(struct GBA* gba, int number, struct GBADMA* info) {
179	struct GBAMemory* memory = &gba->memory;
180	struct ARMCore* cpu = gba->cpu;
181	uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
182	int32_t wordsRemaining = info->nextCount;
183	uint32_t source = info->nextSource;
184	uint32_t dest = info->nextDest;
185	uint32_t sourceRegion = source >> BASE_OFFSET;
186	uint32_t destRegion = dest >> BASE_OFFSET;
187	int32_t cycles = 2;
188
189	gba->cpuBlocked = true;
190	if (info->hasStarted < 2) {
191		if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
192			cycles += 2;
193		}
194		if (width == 4) {
195			cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
196		} else {
197			cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
198		}
199		if (info->hasStarted < 1) {
200			info->hasStarted = info->count << 1;
201			info->when = mTimingCurrentTime(&gba->timing) + cycles;
202			GBADMAUpdate(gba);
203			return;
204		}
205		info->hasStarted = 2;
206		source &= -width;
207		dest &= -width;
208	} else {
209		if (width == 4) {
210			cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
211		} else {
212			cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
213		}
214	}
215	info->when += cycles;
216
217	gba->performingDMA = 1 | (number << 1);
218	uint32_t word;
219	if (width == 4) {
220		word = cpu->memory.load32(cpu, source, 0);
221		gba->bus = word;
222		cpu->memory.store32(cpu, dest, word, 0);
223	} else {
224		if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
225			word = GBASavedataReadEEPROM(&memory->savedata);
226			cpu->memory.store16(cpu, dest, word, 0);
227		} else if (destRegion == REGION_CART2_EX) {
228			if (memory->savedata.type == SAVEDATA_AUTODETECT) {
229				mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
230				GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
231			}
232			word = cpu->memory.load16(cpu, source, 0);
233			GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
234		} else {
235			word = cpu->memory.load16(cpu, source, 0);
236			cpu->memory.store16(cpu, dest, word, 0);
237		}
238		gba->bus = word | (word << 16);
239	}
240	int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
241	int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
242	source += sourceOffset;
243	dest += destOffset;
244	--wordsRemaining;
245	gba->performingDMA = 0;
246
247	if (!wordsRemaining) {
248		info->hasStarted = 0;
249		if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
250			info->reg = GBADMARegisterClearEnable(info->reg);
251
252			// Clear the enable bit in memory
253			memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
254		}
255		if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
256			info->nextDest = info->dest;
257		}
258		if (GBADMARegisterIsDoIRQ(info->reg)) {
259			GBARaiseIRQ(gba, IRQ_DMA0 + number);
260		}
261	} else {
262		info->nextDest = dest;
263	}
264	info->nextCount = wordsRemaining;
265	info->nextSource = source;
266	GBADMAUpdate(gba);
267}