src/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include "util/common.h"
10
11#include "core/core.h"
12#include "gb/gb.h"
13
14extern const uint32_t GB_SAVESTATE_MAGIC;
15extern const uint32_t GB_SAVESTATE_VERSION;
16
17mLOG_DECLARE_CATEGORY(GB_STATE);
18
19/* Savestate format:
20 * 0x00000 - 0x00003: Version Magic (0x01000001)
21 * 0x00004 - 0x00007: ROM CRC32
22 * 0x00008: Game Boy model
23 * 0x00009 - 0x0000F: Reserved (leave zero)
24 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
25 * 0x00020 - 0x00047: CPU state:
26 * | 0x00020: A register
27 * | 0x00021: F register
28 * | 0x00022: B register
29 * | 0x00023: C register
30 * | 0x00024: D register
31 * | 0x00025: E register
32 * | 0x00026: H register
33 * | 0x00027: L register
34 * | 0x00028 - 0x00029: SP register
35 * | 0x0002A - 0x0002B: PC register
36 * | 0x0002C - 0x0002F: Cycles since last event
37 * | 0x00030 - 0x00033: Cycles until next event
38 * | 0x00034 - 0x00035: Reserved (current instruction)
39 * | 0x00036 - 0x00037: Index address
40 * | 0x00038: Bus value
41 * | 0x00039: Execution state
42 * | 0x0003A - 0x0003B: IRQ vector
43 * | 0x0003C - 0x0003F: EI pending cycles
44 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
45 * | 0x00044 - 0x00047: Flags
46 * | bit 0: Is condition met?
47 * | bit 1: Is condition IRQ pending?
48 * | bit 2: Double speed
49 * | bits 3 - 31: Reserved
50 * 0x00048 - 0x0005B: Audio channel 1/framer state
51 * | 0x00048 - 0x0004B: Envelepe timing
52 * | bits 0 - 6: Remaining length
53 * | bits 7 - 9: Next step
54 * | bits 10 - 20: Shadow frequency register
55 * | bits 21 - 31: Reserved
56 * | 0x0004C - 0x0004F: Next frame
57 * | 0x00050 - 0x00057: Reserved
58 * | 0x00058 - 0x0005B: Next event
59 * 0x0005C - 0x0006B: Audio channel 2 state
60 * | 0x0005C - 0x0005F: Envelepe timing
61 * | bits 0 - 2: Remaining length
62 * | bits 3 - 5: Next step
63 * | bits 6 - 31: Reserved
64 * | 0x00060 - 0x00067: Reserved
65 * | 0x00068 - 0x0006B: Next event
66 * 0x0006C - 0x00093: Audio channel 3 state
67 * | 0x0006C - 0x0008B: Wave banks
68 * | 0x0008C - 0x0008D: Remaining length
69 * | 0x0008E - 0x0008F: Reserved
70 * | 0x00090 - 0x00093: Next event
71 * 0x00094 - 0x000A3: Audio channel 4 state
72 * | 0x00094 - 0x00097: Linear feedback shift register state
73 * | 0x00098 - 0x0009B: Envelepe timing
74 * | bits 0 - 2: Remaining length
75 * | bits 3 - 5: Next step
76 * | bits 6 - 31: Reserved
77 * | 0x00098 - 0x0009F: Reserved
78 * | 0x000A0 - 0x000A3: Next event
79 * 0x000A4 - 0x000B7: Audio miscellaneous state
80 * | TODO: Fix this, they're in big-endian order, but field is little-endian
81 * | 0x000A4: Channel 1 envelope state
82 * | bits 0 - 3: Current volume
83 * | bits 4 - 5: Is dead?
84 * | bit 6: Is high?
85 * | 0x000A5: Channel 2 envelope state
86 * | bits 0 - 3: Current volume
87 * | bits 4 - 5: Is dead?
88 * | bit 6: Is high?
89* | bits 7: Reserved
90 * | 0x000A6: Channel 4 envelope state
91 * | bits 0 - 3: Current volume
92 * | bits 4 - 5: Is dead?
93 * | bit 6: Is high?
94* | bits 7: Reserved
95 * | 0x000A7: Miscellaneous audio flags
96 * | bits 0 - 3: Current frame
97 * | bit 4: Is channel 1 sweep enabled?
98 * | bit 5: Has channel 1 sweep occurred?
99 * | bits 6 - 7: Reserved
100 * | 0x000A8 - 0x000AB: Next event
101 * | 0x000AC - 0x000AF: Event diff
102 * | 0x000B0 - 0x000B3: Next sample
103 * 0x000B4 - 0x000153: Video state
104 * | 0x000B4 - 0x000B5: Current x
105 * | 0x000B6 - 0x000B7: Current y (ly)
106 * | 0x000B8 - 0x000BB: Next event
107 * | 0x000BC - 0x000BF: Event diff
108 * | 0x000C0 - 0x000C3: Next mode
109 * | 0x000C4 - 0x000C7: Dot cycle counter
110 * | 0x000C8 - 0x000CB: Frame counter
111 * | 0x000CC: Current VRAM bank
112 * | 0x000CD: Palette flags
113 * | bit 0: BCP increment
114 * | bit 1: OCP increment
115 * | bits 2 - 3: Mode
116 * | bits 4 - 7: Reserved
117 * | 0x000CE - 0x000CF: Reserved
118 * | 0x000D0 - 0x000D1: BCP index
119 * | 0x000D1 - 0x000D3: OCP index
120 * | 0x000D4 - 0x00153: Palette entries
121 * 0x00154 - 0x000167: Timer state
122 * | 0x00154 - 0x00157: Next event
123 * | 0x00158 - 0x0015B: Event diff
124 * | 0x0015C - 0x0015F: Next DIV
125 * | 0x00160 - 0x00163: Inernal DIV
126 * | 0x00164: TIMA period
127 * | 0x00165: Flags
128 * | bit 0: Is IRQ pending?
129 * | 0x00166 - 0x00167: Reserved
130 * 0x000168 - 0x000197: Memory state
131 * | 0x00168 - 0x00169: Current ROM bank
132 * | 0x0016A: Current WRAM bank
133 * | 0x0016B: Current SRAM bank
134 * | 0x0016C - 0x0016F: Next DMA
135 * | 0x00170 - 0x00171: Next DMA source
136 * | 0x00172 - 0x00173: Next DMA destination
137 * | 0x00174 - 0x00177: Next HDMA
138 * | 0x00178 - 0x00179: Next HDMA source
139 * | 0x0017A - 0x0017B: Next HDMA destination
140 * | 0x0017C - 0x0017D: HDMA remaining
141 * | 0x0017E: DMA remaining
142 * | 0x0017F - 0x00183: RTC registers
143 * | 0x00184 - 0x00193: MBC state (TODO)
144 * | 0x00194 - 0x00195: Flags
145 * | bit 0: SRAM accessable
146 * | bit 1: RTC accessible
147 * | bit 2: RTC latched
148 * | bit 3: IME
149 * | bit 4: Is HDMA active?
150 * | bits 5 - 7: Active RTC register
151 * | 0x00196 - 0x00197: Reserved (leave zero)
152 * 0x00198 - 0x0019F: Savestate creation time (usec since 1970)
153 * 0x001A0 - 0x0025F: Reserved (leave zero)
154 * 0x00260 - 0x002FF: OAM
155 * 0x00300 - 0x0037F: I/O memory
156 * 0x00380 - 0x003FE: HRAM
157 * 0x003FF: Interrupts enabled
158 * 0x00400 - 0x043FF: VRAM
159 * 0x04400 - 0x0C3FF: WRAM
160 * Total size: 0xC400 (50,176) bytes
161*/
162
163DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
164DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
165DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
166DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
167DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
168DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
169DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
170DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
171DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
172DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
173DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
174DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
175
176DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
177DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
178DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
179DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
180
181struct GBSerializedPSGState {
182 struct {
183 GBSerializedAudioEnvelope envelope;
184 int32_t nextFrame;
185 int32_t reserved[2];
186 int32_t nextEvent;
187 } ch1;
188 struct {
189 GBSerializedAudioEnvelope envelope;
190 int32_t reserved[2];
191 int32_t nextEvent;
192 } ch2;
193 struct {
194 uint32_t wavebanks[8];
195 int16_t length;
196 int16_t reserved;
197 int32_t nextEvent;
198 } ch3;
199 struct {
200 int32_t lfsr;
201 GBSerializedAudioEnvelope envelope;
202 int32_t reserved;
203 int32_t nextEvent;
204 } ch4;
205};
206
207DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
208DECL_BIT(GBSerializedCpuFlags, Condition, 0);
209DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
210DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
211
212DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
213DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
214
215DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
216DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
217DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
218DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
219
220DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
221DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
222DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
223
224DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
225DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
226DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
227DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
228DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
229DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
230DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
231
232#pragma pack(push, 1)
233struct GBSerializedState {
234 uint32_t versionMagic;
235 uint32_t romCrc32;
236 uint8_t model;
237 uint8_t reservedHeader[7];
238
239 char title[16];
240
241 struct {
242 uint8_t a;
243 uint8_t f;
244 uint8_t b;
245 uint8_t c;
246 uint8_t d;
247 uint8_t e;
248 uint8_t h;
249 uint8_t l;
250 uint16_t sp;
251 uint16_t pc;
252
253 int32_t cycles;
254 int32_t nextEvent;
255
256 uint16_t reservedInstruction;
257 uint16_t index;
258 uint8_t bus;
259 uint8_t executionState;
260
261 uint16_t irqVector;
262
263 int32_t eiPending;
264 int32_t reservedDiPending;
265 GBSerializedCpuFlags flags;
266 } cpu;
267
268 struct {
269 struct GBSerializedPSGState psg;
270 GBSerializedAudioFlags flags;
271 int32_t nextEvent;
272 int32_t eventDiff;
273 int32_t nextSample;
274 } audio;
275
276 struct {
277 int16_t x;
278 int16_t ly;
279 int32_t nextEvent;
280 int32_t eventDiff;
281 int32_t nextMode;
282 int32_t dotCounter;
283 int32_t frameCounter;
284
285 uint8_t vramCurrentBank;
286 GBSerializedVideoFlags flags;
287 uint16_t reserved;
288
289 uint16_t bcpIndex;
290 uint16_t ocpIndex;
291
292 uint16_t palette[64];
293 } video;
294
295 struct {
296 int32_t nextEvent;
297 int32_t eventDiff;
298
299 int32_t nextDiv;
300 uint32_t internalDiv;
301 uint8_t timaPeriod;
302 GBSerializedTimerFlags flags;
303 uint16_t reserved;
304 } timer;
305
306 struct {
307 uint16_t currentBank;
308 uint8_t wramCurrentBank;
309 uint8_t sramCurrentBank;
310
311 int32_t dmaNext;
312 uint16_t dmaSource;
313 uint16_t dmaDest;
314
315 int32_t hdmaNext;
316 uint16_t hdmaSource;
317 uint16_t hdmaDest;
318
319 uint16_t hdmaRemaining;
320 uint8_t dmaRemaining;
321 uint8_t rtcRegs[5];
322
323 union {
324 struct {
325 uint32_t mode;
326 } mbc1;
327 struct {
328 uint64_t lastLatch;
329 } rtc;
330 struct {
331 int8_t machineState;
332 GBMBC7Field field;
333 int8_t address;
334 uint8_t srBits;
335 uint32_t sr;
336 GBSerializedMBC7Flags flags;
337 } mbc7;
338 struct {
339 uint8_t reserved[16];
340 } padding;
341 };
342
343 GBSerializedMemoryFlags flags;
344 uint16_t reserved;
345 } memory;
346
347 uint64_t creationUsec;
348
349 uint32_t reserved[48];
350
351 uint8_t oam[GB_SIZE_OAM];
352
353 uint8_t io[GB_SIZE_IO];
354 uint8_t hram[GB_SIZE_HRAM];
355 uint8_t ie;
356
357 uint8_t vram[GB_SIZE_VRAM];
358 uint8_t wram[GB_SIZE_WORKING_RAM];
359};
360#pragma pack(pop)
361
362bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
363void GBSerialize(struct GB* gb, struct GBSerializedState* state);
364
365#endif