src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
189 cpu->cpsr.flags = 0;
190 cpu->cpsr.n = ARM_SIGN(d);
191 cpu->cpsr.z = !d;
192 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
193 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
194}
195
196ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
197 cpu->cpsr.flags = 0;
198 cpu->cpsr.n = ARM_SIGN(d);
199 cpu->cpsr.z = !d;
200 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
201 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
202}
203
204ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
205 cpu->cpsr.n = ARM_SIGN(d);
206 cpu->cpsr.z = !d; \
207 cpu->cpsr.c = cpu->shifterCarryOut; \
208}
209
210#define ARM_ADDITION_S(M, N, D) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 _additionS(cpu, M, N, D); \
216 }
217
218#define ARM_SUBTRACTION_S(M, N, D) \
219 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
220 cpu->cpsr = cpu->spsr; \
221 _ARMReadCPSR(cpu); \
222 } else { \
223 _subtractionS(cpu, M, N, D); \
224 }
225
226#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
227 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
228 cpu->cpsr = cpu->spsr; \
229 _ARMReadCPSR(cpu); \
230 } else { \
231 cpu->cpsr.n = ARM_SIGN(D); \
232 cpu->cpsr.z = !(D); \
233 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
234 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
235 }
236
237#define ARM_NEUTRAL_S(M, N, D) \
238 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
239 cpu->cpsr = cpu->spsr; \
240 _ARMReadCPSR(cpu); \
241 } else { \
242 _neutralS(cpu, D); \
243 }
244
245#define ARM_NEUTRAL_HI_S(DLO, DHI) \
246 cpu->cpsr.n = ARM_SIGN(DHI); \
247 cpu->cpsr.z = !((DHI) | (DLO));
248
249#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
250#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
251#define ADDR_MODE_2_ADDRESS (address)
252#define ADDR_MODE_2_RN (cpu->gprs[rn])
253#define ADDR_MODE_2_RM (cpu->gprs[rm])
254#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
255#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
256#define ADDR_MODE_2_WRITEBACK(ADDR) \
257 cpu->gprs[rn] = ADDR; \
258 if (UNLIKELY(rn == ARM_PC)) { \
259 currentCycles += ARMWritePC(cpu); \
260 }
261
262#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
263#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
264#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
265#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
266
267#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
268#define ADDR_MODE_3_RN ADDR_MODE_2_RN
269#define ADDR_MODE_3_RM ADDR_MODE_2_RM
270#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
271#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
272#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
273#define ADDR_MODE_3_WRITEBACK_64(ADDR) ADDR_MODE_2_WRITEBACK(ADDR + 4)
274
275#define ADDR_MODE_4_WRITEBACK_LDM \
276 if (!((1 << rn) & rs)) { \
277 cpu->gprs[rn] = address; \
278 }
279
280#define ADDR_MODE_4_WRITEBACK_LDMv5 \
281 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
282 cpu->gprs[rn] = address; \
283 }
284
285#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
286
287#define ARM_LOAD_POST_BODY \
288 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
289 if (rd == ARM_PC) { \
290 currentCycles += ARMWritePC(cpu); \
291 }
292
293#define ARM_LOAD_POST_BODY_v5 \
294 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
295 if (rd == ARM_PC) { \
296 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
297 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
298 if (cpu->executionMode == MODE_THUMB) { \
299 currentCycles += ThumbWritePC(cpu); \
300 } else { \
301 currentCycles += ARMWritePC(cpu); \
302 } \
303 }
304
305#define ARM_STORE_POST_BODY \
306 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
307
308#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
309 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
310 int currentCycles = ARM_PREFETCH_CYCLES; \
311 BODY; \
312 cpu->cycles += currentCycles; \
313 }
314
315#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
316 DEFINE_INSTRUCTION_ARM(NAME, \
317 int rd = (opcode >> 12) & 0xF; \
318 int rn = (opcode >> 16) & 0xF; \
319 UNUSED(rn); \
320 SHIFTER(cpu, opcode); \
321 BODY; \
322 S_BODY; \
323 if (rd == ARM_PC) { \
324 if (cpu->executionMode == MODE_ARM) { \
325 currentCycles += ARMWritePC(cpu); \
326 } else { \
327 currentCycles += ThumbWritePC(cpu); \
328 } \
329 })
330
331#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
335 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
342
343#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
344 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
345 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
346 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
347 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
348 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
349
350#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
351 DEFINE_INSTRUCTION_ARM(NAME, \
352 int rd = (opcode >> 16) & 0xF; \
353 int rs = (opcode >> 8) & 0xF; \
354 int rm = opcode & 0xF; \
355 if (rd == ARM_PC) { \
356 return; \
357 } \
358 ARM_WAIT_MUL(cpu->gprs[rs]); \
359 BODY; \
360 S_BODY; \
361 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
362
363#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
364 DEFINE_INSTRUCTION_ARM(NAME, \
365 int rd = (opcode >> 12) & 0xF; \
366 int rdHi = (opcode >> 16) & 0xF; \
367 int rs = (opcode >> 8) & 0xF; \
368 int rm = opcode & 0xF; \
369 if (rdHi == ARM_PC || rd == ARM_PC) { \
370 return; \
371 } \
372 currentCycles += cpu->memory.stall(cpu, WAIT); \
373 BODY; \
374 S_BODY; \
375 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
376
377#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
378 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
379 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
380
381#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
382 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
383 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
384
385#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
386 DEFINE_INSTRUCTION_ARM(NAME, \
387 int rd = (opcode >> 16) & 0xF; \
388 int rs = (opcode >> 8) & 0xF; \
389 int rn = (opcode >> 12) & 0xF; \
390 int rm = opcode & 0xF; \
391 UNUSED(rn); \
392 if (rd == ARM_PC) { \
393 return; \
394 } \
395 /* TODO: Timing */ \
396 int32_t x; \
397 int32_t y; \
398 BODY; \
399 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
400
401#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
402 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
403 x = ARM_SXT_16(cpu->gprs[rm]); \
404 y = ARM_SXT_16(cpu->gprs[rs]); \
405 BODY) \
406 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
407 x = ARM_SXT_16(cpu->gprs[rm]); \
408 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
409 BODY) \
410 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
411 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
412 y = ARM_SXT_16(cpu->gprs[rs]); \
413 BODY) \
414 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
415 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
416 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
417 BODY)
418
419#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
420 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
421 UNUSED(x); \
422 y = ARM_SXT_16(cpu->gprs[rs]); \
423 BODY) \
424 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
425 UNUSED(x); \
426 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
427 BODY) \
428
429#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
430 DEFINE_INSTRUCTION_ARM(NAME, \
431 uint32_t address; \
432 int rn = (opcode >> 16) & 0xF; \
433 int rd = (opcode >> 12) & 0xF; \
434 int rm = opcode & 0xF; \
435 UNUSED(rm); \
436 address = ADDRESS; \
437 WRITEBACK; \
438 BODY;)
439
440#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
442 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
443 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
445 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
446 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
447
448#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
459
460#define DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, WRITEBACK) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
473
474#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK)
475#define DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK_64)
476
477#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
479 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
480
481#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
482 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
483 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
484 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
485 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
486 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
487 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
488
489#define ARM_MS_PRE \
490 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
491 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
492
493#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
494
495#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
496 DEFINE_INSTRUCTION_ARM(NAME, \
497 int rn = (opcode >> 16) & 0xF; \
498 int rs = opcode & 0x0000FFFF; \
499 uint32_t address = cpu->gprs[rn]; \
500 S_PRE; \
501 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
502 S_POST; \
503 POST_BODY; \
504 WRITEBACK;)
505
506
507#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
508 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
509 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
510 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
511 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
512 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
513 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
514 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
515 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
516
517#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
518 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
519 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
520 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
521 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
522 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
523 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
524 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
525 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
526 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
527
528// Begin ALU definitions
529
530DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
531 int32_t n = cpu->gprs[rn];
532 cpu->gprs[rd] = n + cpu->shifterOperand;)
533
534DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
535 int32_t n = cpu->gprs[rn];
536 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
537
538DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
539 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
540
541DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
542 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
543
544DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
545 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
546
547DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
548 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
549
550DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
551 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
552
553DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
554 cpu->gprs[rd] = cpu->shifterOperand;)
555
556DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
557 cpu->gprs[rd] = ~cpu->shifterOperand;)
558
559DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
560 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
561
562DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
563 int32_t n = cpu->gprs[rn];
564 cpu->gprs[rd] = cpu->shifterOperand - n;)
565
566DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
567 int32_t n = cpu->gprs[rn];
568 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
569
570DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
571 int32_t n = cpu->gprs[rn];
572 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
573
574DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
575 int32_t n = cpu->gprs[rn];
576 cpu->gprs[rd] = n - cpu->shifterOperand;)
577
578DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
579 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
580
581DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
582 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
583
584// End ALU definitions
585
586// Begin multiply definitions
587
588DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
589DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
590
591DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
592 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
593 int32_t dm = cpu->gprs[rd];
594 int32_t dn = d;
595 cpu->gprs[rd] = dm + dn;
596 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
597 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
598
599DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
600 int32_t dn = cpu->gprs[rn]; \
601 int32_t d = x * y; \
602 cpu->gprs[rd] = d + dn; \
603 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
604
605DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
606
607DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
608 int32_t dn = cpu->gprs[rn]; \
609 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
610 cpu->gprs[rd] = d + dn; \
611 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
612
613DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
614
615DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
616 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
617 cpu->gprs[rd] = d;
618 cpu->gprs[rdHi] = d >> 32;,
619 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
620
621DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
622 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
623 int32_t dm = cpu->gprs[rd];
624 int32_t dn = d;
625 cpu->gprs[rd] = dm + dn;
626 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
627 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
628
629DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
630 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
631 cpu->gprs[rd] = d;
632 cpu->gprs[rdHi] = d >> 32;,
633 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
634
635// End multiply definitions
636
637// Begin load/store definitions
638
639DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
640DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
641DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
642DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(LDRD, cpu->gprs[rd & ~1] = cpu->memory.load32(cpu, address, ¤tCycles); cpu->gprs[rd | 1] = cpu->memory.load32(cpu, address + 4, ¤tCycles); ARM_LOAD_POST_BODY;)
643DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
644DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
645DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
646DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
647DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
648DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(STRD, cpu->memory.store32(cpu, address, cpu->gprs[rd & ~1], ¤tCycles); cpu->memory.store32(cpu, address + 4, cpu->gprs[rd | 1], ¤tCycles); ARM_STORE_POST_BODY;)
649DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
650
651DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
652 enum PrivilegeMode priv = cpu->privilegeMode;
653 ARMSetPrivilegeMode(cpu, MODE_USER);
654 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
655 ARMSetPrivilegeMode(cpu, priv);
656 cpu->gprs[rd] = r;
657 ARM_LOAD_POST_BODY;)
658
659DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
660 enum PrivilegeMode priv = cpu->privilegeMode;
661 ARMSetPrivilegeMode(cpu, MODE_USER);
662 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
663 ARMSetPrivilegeMode(cpu, priv);
664 cpu->gprs[rd] = r;
665 ARM_LOAD_POST_BODY;)
666
667DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
668 enum PrivilegeMode priv = cpu->privilegeMode;
669 int32_t r = cpu->gprs[rd];
670 ARMSetPrivilegeMode(cpu, MODE_USER);
671 cpu->memory.store8(cpu, address, r, ¤tCycles);
672 ARMSetPrivilegeMode(cpu, priv);
673 ARM_STORE_POST_BODY;)
674
675DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
676 enum PrivilegeMode priv = cpu->privilegeMode;
677 int32_t r = cpu->gprs[rd];
678 ARMSetPrivilegeMode(cpu, MODE_USER);
679 cpu->memory.store32(cpu, address, r, ¤tCycles);
680 ARMSetPrivilegeMode(cpu, priv);
681 ARM_STORE_POST_BODY;)
682
683DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
684 load,
685 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
686 if (rs & 0x8000) {
687 currentCycles += ARMWritePC(cpu);
688 })
689
690DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
691 load,
692 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
693 if (rs & 0x8000) {
694 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
695 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
696 if (cpu->executionMode == MODE_THUMB) {
697 currentCycles += ThumbWritePC(cpu);
698 } else {
699 currentCycles += ARMWritePC(cpu);
700
701 }
702 })
703
704DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
705 store,
706 ARM_STORE_POST_BODY;)
707
708DEFINE_INSTRUCTION_ARM(SWP,
709 int rm = opcode & 0xF;
710 int rd = (opcode >> 12) & 0xF;
711 int rn = (opcode >> 16) & 0xF;
712 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
713 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
714 cpu->gprs[rd] = d;)
715
716DEFINE_INSTRUCTION_ARM(SWPB,
717 int rm = opcode & 0xF;
718 int rd = (opcode >> 12) & 0xF;
719 int rn = (opcode >> 16) & 0xF;
720 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
721 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
722 cpu->gprs[rd] = d;)
723
724// End load/store definitions
725
726// Begin branch definitions
727
728DEFINE_INSTRUCTION_ARM(B,
729 int32_t offset = opcode << 8;
730 offset >>= 6;
731 cpu->gprs[ARM_PC] += offset;
732 currentCycles += ARMWritePC(cpu);)
733
734DEFINE_INSTRUCTION_ARM(BL,
735 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
736 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
737 cpu->gprs[ARM_PC] += immediate >> 6;
738 currentCycles += ARMWritePC(cpu);)
739
740DEFINE_INSTRUCTION_ARM(BX,
741 int rm = opcode & 0x0000000F;
742 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
743 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
744 if (cpu->executionMode == MODE_THUMB) {
745 currentCycles += ThumbWritePC(cpu);
746 } else {
747 currentCycles += ARMWritePC(cpu);
748
749 })
750
751DEFINE_INSTRUCTION_ARM(BLX,
752 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
753 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
754 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
755 _ARMSetMode(cpu, MODE_THUMB);
756 currentCycles += ThumbWritePC(cpu);)
757
758DEFINE_INSTRUCTION_ARM(BLX2,
759 int rm = opcode & 0x0000000F;
760 int address = cpu->gprs[rm];
761 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
762 _ARMSetMode(cpu, address & 0x00000001);
763 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
764 if (cpu->executionMode == MODE_THUMB) {
765 currentCycles += ThumbWritePC(cpu);
766 } else {
767 currentCycles += ARMWritePC(cpu);
768 })
769
770// End branch definitions
771
772// Begin coprocessor definitions
773
774#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
775 DEFINE_INSTRUCTION_ARM(NAME, \
776 int op1 = (opcode >> 21) & 7; \
777 int op2 = (opcode >> 5) & 7; \
778 int rd = (opcode >> 12) & 0xF; \
779 int cp = (opcode >> 8) & 0xF; \
780 int crn = (opcode >> 16) & 0xF; \
781 int crm = opcode & 0xF; \
782 UNUSED(op1); \
783 UNUSED(op2); \
784 UNUSED(rd); \
785 UNUSED(crn); \
786 UNUSED(crm); \
787 BODY;)
788
789DEFINE_COPROCESSOR_INSTRUCTION(MRC,
790 if (cp == 15 && cpu->irqh.readCP15) {
791 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
792 } else {
793 ARM_STUB;
794 })
795
796DEFINE_COPROCESSOR_INSTRUCTION(MCR,
797 if (cp == 15 && cpu->irqh.writeCP15) {
798 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
799 } else {
800 ARM_STUB;
801 })
802
803DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
804DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
805DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
806
807// Begin miscellaneous definitions
808
809DEFINE_INSTRUCTION_ARM(CLZ,
810 int rm = opcode & 0xF;
811 int rd = (opcode >> 12) & 0xF;
812 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
813
814DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
815DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
816
817DEFINE_INSTRUCTION_ARM(MSR,
818 int c = opcode & 0x00010000;
819 int f = opcode & 0x00080000;
820 int32_t operand = cpu->gprs[opcode & 0x0000000F];
821 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
822 if (mask & PSR_USER_MASK) {
823 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
824 }
825 if (mask & PSR_STATE_MASK) {
826 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
827 }
828 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
829 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
830 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
831 }
832 _ARMReadCPSR(cpu);
833 if (cpu->executionMode == MODE_THUMB) {
834 cpu->prefetch[0] = 0x46C0; // nop
835 cpu->prefetch[1] &= 0xFFFF;
836 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
837 } else {
838 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
839 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
840 })
841
842DEFINE_INSTRUCTION_ARM(MSRR,
843 int c = opcode & 0x00010000;
844 int f = opcode & 0x00080000;
845 int32_t operand = cpu->gprs[opcode & 0x0000000F];
846 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
847 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
848 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
849
850DEFINE_INSTRUCTION_ARM(MRS, \
851 int rd = (opcode >> 12) & 0xF; \
852 cpu->gprs[rd] = cpu->cpsr.packed;)
853
854DEFINE_INSTRUCTION_ARM(MRSR, \
855 int rd = (opcode >> 12) & 0xF; \
856 cpu->gprs[rd] = cpu->spsr.packed;)
857
858DEFINE_INSTRUCTION_ARM(MSRI,
859 int c = opcode & 0x00010000;
860 int f = opcode & 0x00080000;
861 int rotate = (opcode & 0x00000F00) >> 7;
862 int32_t operand = ROR(opcode & 0x000000FF, rotate);
863 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
864 if (mask & PSR_USER_MASK) {
865 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
866 }
867 if (mask & PSR_STATE_MASK) {
868 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
869 }
870 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
871 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
872 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
873 }
874 _ARMReadCPSR(cpu);
875 if (cpu->executionMode == MODE_THUMB) {
876 cpu->prefetch[0] = 0x46C0; // nop
877 cpu->prefetch[1] &= 0xFFFF;
878 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
879 } else {
880 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
881 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
882 })
883
884DEFINE_INSTRUCTION_ARM(MSRRI,
885 int c = opcode & 0x00010000;
886 int f = opcode & 0x00080000;
887 int rotate = (opcode & 0x00000F00) >> 7;
888 int32_t operand = ROR(opcode & 0x000000FF, rotate);
889 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
890 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
891 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
892
893DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
894
895const ARMInstruction _armv4Table[0x1000] = {
896 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
897};
898
899const ARMInstruction _armv5Table[0x1000] = {
900 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
901};
902
903const ARMInstruction _armv4FTable[0x1000] = {
904 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
905};
906
907const ARMInstruction _armv5FTable[0x1000] = {
908 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
909};