src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/memory.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/gb/gb.h>
10#include <mgba/internal/gb/io.h>
11#include <mgba/internal/gb/mbc.h>
12#include <mgba/internal/gb/serialize.h>
13#include <mgba/internal/lr35902/lr35902.h>
14
15#include <mgba-util/memory.h>
16
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory", "gb.memory");
18
19struct OAMBlock {
20 uint16_t low;
21 uint16_t high;
22};
23
24static const struct OAMBlock _oamBlockDMG[] = {
25 { 0xA000, 0xFE00 },
26 { 0xA000, 0xFE00 },
27 { 0xA000, 0xFE00 },
28 { 0xA000, 0xFE00 },
29 { 0x8000, 0xA000 },
30 { 0xA000, 0xFE00 },
31 { 0xA000, 0xFE00 },
32 { 0xA000, 0xFE00 },
33};
34
35static const struct OAMBlock _oamBlockCGB[] = {
36 { 0xA000, 0xC000 },
37 { 0xA000, 0xC000 },
38 { 0xA000, 0xC000 },
39 { 0xA000, 0xC000 },
40 { 0x8000, 0xA000 },
41 { 0xA000, 0xC000 },
42 { 0xC000, 0xFE00 },
43 { 0xA000, 0xC000 },
44};
45
46static void _pristineCow(struct GB* gba);
47
48static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
49 if (UNLIKELY(address >= cpu->memory.activeRegionEnd)) {
50 cpu->memory.setActiveRegion(cpu, address);
51 return cpu->memory.cpuLoad8(cpu, address);
52 }
53 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
54}
55
56static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
57 struct GB* gb = (struct GB*) cpu->master;
58 struct GBMemory* memory = &gb->memory;
59 switch (address >> 12) {
60 case GB_REGION_CART_BANK0:
61 case GB_REGION_CART_BANK0 + 1:
62 case GB_REGION_CART_BANK0 + 2:
63 case GB_REGION_CART_BANK0 + 3:
64 cpu->memory.cpuLoad8 = GBFastLoad8;
65 cpu->memory.activeRegion = memory->romBase;
66 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
67 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
68 break;
69 case GB_REGION_CART_BANK1:
70 case GB_REGION_CART_BANK1 + 1:
71 case GB_REGION_CART_BANK1 + 2:
72 case GB_REGION_CART_BANK1 + 3:
73 cpu->memory.cpuLoad8 = GBFastLoad8;
74 cpu->memory.activeRegion = memory->romBank;
75 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
76 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
77 break;
78 default:
79 cpu->memory.cpuLoad8 = GBLoad8;
80 break;
81 }
82}
83
84static void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
85static void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
86
87void GBMemoryInit(struct GB* gb) {
88 struct LR35902Core* cpu = gb->cpu;
89 cpu->memory.cpuLoad8 = GBLoad8;
90 cpu->memory.load8 = GBLoad8;
91 cpu->memory.store8 = GBStore8;
92 cpu->memory.currentSegment = GBCurrentSegment;
93 cpu->memory.setActiveRegion = GBSetActiveRegion;
94
95 gb->memory.wram = 0;
96 gb->memory.wramBank = 0;
97 gb->memory.rom = 0;
98 gb->memory.romBank = 0;
99 gb->memory.romSize = 0;
100 gb->memory.sram = 0;
101 gb->memory.mbcType = GB_MBC_AUTODETECT;
102 gb->memory.mbcRead = NULL;
103 gb->memory.mbcWrite = NULL;
104
105 gb->memory.rtc = NULL;
106 gb->memory.rotation = NULL;
107 gb->memory.rumble = NULL;
108 gb->memory.cam = NULL;
109
110 GBIOInit(gb);
111}
112
113void GBMemoryDeinit(struct GB* gb) {
114 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
115 if (gb->memory.rom) {
116 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
117 }
118}
119
120void GBMemoryReset(struct GB* gb) {
121 if (gb->memory.wram) {
122 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
123 }
124 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
125 if (gb->model >= GB_MODEL_CGB) {
126 uint32_t* base = (uint32_t*) gb->memory.wram;
127 size_t i;
128 uint32_t pattern = 0;
129 for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
130 if ((i & 0x1FF) == 0) {
131 pattern = ~pattern;
132 }
133 base[i + 0] = pattern;
134 base[i + 1] = pattern;
135 base[i + 2] = ~pattern;
136 base[i + 3] = ~pattern;
137 }
138 }
139 GBMemorySwitchWramBank(&gb->memory, 1);
140 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
141 gb->memory.currentBank = 1;
142 gb->memory.sramCurrentBank = 0;
143
144 gb->memory.ime = false;
145 gb->memory.ie = 0;
146
147 gb->memory.dmaRemaining = 0;
148 gb->memory.dmaSource = 0;
149 gb->memory.dmaDest = 0;
150 gb->memory.hdmaRemaining = 0;
151 gb->memory.hdmaSource = 0;
152 gb->memory.hdmaDest = 0;
153 gb->memory.isHdma = false;
154
155
156 gb->memory.dmaEvent.context = gb;
157 gb->memory.dmaEvent.name = "GB DMA";
158 gb->memory.dmaEvent.callback = _GBMemoryDMAService;
159 gb->memory.dmaEvent.priority = 0x40;
160 gb->memory.hdmaEvent.context = gb;
161 gb->memory.hdmaEvent.name = "GB HDMA";
162 gb->memory.hdmaEvent.callback = _GBMemoryHDMAService;
163 gb->memory.hdmaEvent.priority = 0x41;
164
165 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
166 switch (gb->memory.mbcType) {
167 case GB_MBC1:
168 gb->memory.mbcState.mbc1.mode = 0;
169 break;
170 default:
171 memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
172 }
173
174 GBMBCInit(gb);
175 gb->memory.sramBank = gb->memory.sram;
176
177 if (!gb->memory.wram) {
178 GBMemoryDeinit(gb);
179 }
180}
181
182void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
183 bank &= 7;
184 if (!bank) {
185 bank = 1;
186 }
187 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
188 memory->wramCurrentBank = bank;
189}
190
191uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
192 struct GB* gb = (struct GB*) cpu->master;
193 struct GBMemory* memory = &gb->memory;
194 if (gb->memory.dmaRemaining) {
195 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
196 block = &block[memory->dmaSource >> 13];
197 if (address >= block->low && address < block->high) {
198 return 0xFF;
199 }
200 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
201 return 0xFF;
202 }
203 }
204 switch (address >> 12) {
205 case GB_REGION_CART_BANK0:
206 case GB_REGION_CART_BANK0 + 1:
207 case GB_REGION_CART_BANK0 + 2:
208 case GB_REGION_CART_BANK0 + 3:
209 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
210 case GB_REGION_CART_BANK1:
211 case GB_REGION_CART_BANK1 + 1:
212 case GB_REGION_CART_BANK1 + 2:
213 case GB_REGION_CART_BANK1 + 3:
214 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
215 case GB_REGION_VRAM:
216 case GB_REGION_VRAM + 1:
217 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
218 case GB_REGION_EXTERNAL_RAM:
219 case GB_REGION_EXTERNAL_RAM + 1:
220 if (memory->rtcAccess) {
221 return memory->rtcRegs[memory->activeRtcReg];
222 } else if (memory->mbcRead) {
223 return memory->mbcRead(memory, address);
224 } else if (memory->sramAccess) {
225 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
226 } else if (memory->mbcType == GB_HuC3) {
227 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
228 }
229 return 0xFF;
230 case GB_REGION_WORKING_RAM_BANK0:
231 case GB_REGION_WORKING_RAM_BANK0 + 2:
232 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
233 case GB_REGION_WORKING_RAM_BANK1:
234 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
235 default:
236 if (address < GB_BASE_OAM) {
237 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
238 }
239 if (address < GB_BASE_UNUSABLE) {
240 if (gb->video.mode < 2) {
241 return gb->video.oam.raw[address & 0xFF];
242 }
243 return 0xFF;
244 }
245 if (address < GB_BASE_IO) {
246 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
247 return 0xFF;
248 }
249 if (address < GB_BASE_HRAM) {
250 return GBIORead(gb, address & (GB_SIZE_IO - 1));
251 }
252 if (address < GB_BASE_IE) {
253 return memory->hram[address & GB_SIZE_HRAM];
254 }
255 return GBIORead(gb, REG_IE);
256 }
257}
258
259void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
260 struct GB* gb = (struct GB*) cpu->master;
261 struct GBMemory* memory = &gb->memory;
262 if (gb->memory.dmaRemaining) {
263 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
264 block = &block[memory->dmaSource >> 13];
265 if (address >= block->low && address < block->high) {
266 return;
267 }
268 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
269 return;
270 }
271 }
272 switch (address >> 12) {
273 case GB_REGION_CART_BANK0:
274 case GB_REGION_CART_BANK0 + 1:
275 case GB_REGION_CART_BANK0 + 2:
276 case GB_REGION_CART_BANK0 + 3:
277 case GB_REGION_CART_BANK1:
278 case GB_REGION_CART_BANK1 + 1:
279 case GB_REGION_CART_BANK1 + 2:
280 case GB_REGION_CART_BANK1 + 3:
281 memory->mbcWrite(gb, address, value);
282 cpu->memory.setActiveRegion(cpu, cpu->pc);
283 return;
284 case GB_REGION_VRAM:
285 case GB_REGION_VRAM + 1:
286 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) | (GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank));
287 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
288 return;
289 case GB_REGION_EXTERNAL_RAM:
290 case GB_REGION_EXTERNAL_RAM + 1:
291 if (memory->rtcAccess) {
292 memory->rtcRegs[memory->activeRtcReg] = value;
293 } else if (memory->sramAccess) {
294 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
295 } else {
296 memory->mbcWrite(gb, address, value);
297 }
298 gb->sramDirty |= GB_SRAM_DIRT_NEW;
299 return;
300 case GB_REGION_WORKING_RAM_BANK0:
301 case GB_REGION_WORKING_RAM_BANK0 + 2:
302 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
303 return;
304 case GB_REGION_WORKING_RAM_BANK1:
305 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
306 return;
307 default:
308 if (address < GB_BASE_OAM) {
309 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
310 } else if (address < GB_BASE_UNUSABLE) {
311 if (gb->video.mode < 2) {
312 gb->video.oam.raw[address & 0xFF] = value;
313 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
314 }
315 } else if (address < GB_BASE_IO) {
316 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
317 } else if (address < GB_BASE_HRAM) {
318 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
319 } else if (address < GB_BASE_IE) {
320 memory->hram[address & GB_SIZE_HRAM] = value;
321 } else {
322 GBIOWrite(gb, REG_IE, value);
323 }
324 }
325}
326
327int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address) {
328 struct GB* gb = (struct GB*) cpu->master;
329 struct GBMemory* memory = &gb->memory;
330 switch (address >> 12) {
331 case GB_REGION_CART_BANK0:
332 case GB_REGION_CART_BANK0 + 1:
333 case GB_REGION_CART_BANK0 + 2:
334 case GB_REGION_CART_BANK0 + 3:
335 return 0;
336 case GB_REGION_CART_BANK1:
337 case GB_REGION_CART_BANK1 + 1:
338 case GB_REGION_CART_BANK1 + 2:
339 case GB_REGION_CART_BANK1 + 3:
340 return memory->currentBank;
341 case GB_REGION_VRAM:
342 case GB_REGION_VRAM + 1:
343 return gb->video.vramCurrentBank;
344 case GB_REGION_EXTERNAL_RAM:
345 case GB_REGION_EXTERNAL_RAM + 1:
346 return memory->sramCurrentBank;
347 case GB_REGION_WORKING_RAM_BANK0:
348 case GB_REGION_WORKING_RAM_BANK0 + 2:
349 return 0;
350 case GB_REGION_WORKING_RAM_BANK1:
351 return memory->wramCurrentBank;
352 default:
353 return 0;
354 }
355}
356
357uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) {
358 struct GB* gb = (struct GB*) cpu->master;
359 struct GBMemory* memory = &gb->memory;
360 switch (address >> 12) {
361 case GB_REGION_CART_BANK0:
362 case GB_REGION_CART_BANK0 + 1:
363 case GB_REGION_CART_BANK0 + 2:
364 case GB_REGION_CART_BANK0 + 3:
365 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
366 case GB_REGION_CART_BANK1:
367 case GB_REGION_CART_BANK1 + 1:
368 case GB_REGION_CART_BANK1 + 2:
369 case GB_REGION_CART_BANK1 + 3:
370 if (segment < 0) {
371 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
372 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
373 return memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
374 } else {
375 return 0xFF;
376 }
377 case GB_REGION_VRAM:
378 case GB_REGION_VRAM + 1:
379 if (segment < 0) {
380 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
381 } else if (segment < 2) {
382 return gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment *GB_SIZE_VRAM_BANK0];
383 } else {
384 return 0xFF;
385 }
386 case GB_REGION_EXTERNAL_RAM:
387 case GB_REGION_EXTERNAL_RAM + 1:
388 if (memory->rtcAccess) {
389 return memory->rtcRegs[memory->activeRtcReg];
390 } else if (memory->sramAccess) {
391 if (segment < 0) {
392 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
393 } else if ((size_t) segment * GB_SIZE_EXTERNAL_RAM < gb->sramSize) {
394 return memory->sram[(address & (GB_SIZE_EXTERNAL_RAM - 1)) + segment *GB_SIZE_EXTERNAL_RAM];
395 } else {
396 return 0xFF;
397 }
398 } else if (memory->mbcRead) {
399 return memory->mbcRead(memory, address);
400 } else if (memory->mbcType == GB_HuC3) {
401 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
402 }
403 return 0xFF;
404 case GB_REGION_WORKING_RAM_BANK0:
405 case GB_REGION_WORKING_RAM_BANK0 + 2:
406 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
407 case GB_REGION_WORKING_RAM_BANK1:
408 if (segment < 0) {
409 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
410 } else if (segment < 8) {
411 return memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment *GB_SIZE_WORKING_RAM_BANK0];
412 } else {
413 return 0xFF;
414 }
415 default:
416 if (address < GB_BASE_OAM) {
417 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
418 }
419 if (address < GB_BASE_UNUSABLE) {
420 if (gb->video.mode < 2) {
421 return gb->video.oam.raw[address & 0xFF];
422 }
423 return 0xFF;
424 }
425 if (address < GB_BASE_IO) {
426 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
427 return 0xFF;
428 }
429 if (address < GB_BASE_HRAM) {
430 return GBIORead(gb, address & (GB_SIZE_IO - 1));
431 }
432 if (address < GB_BASE_IE) {
433 return memory->hram[address & GB_SIZE_HRAM];
434 }
435 return GBIORead(gb, REG_IE);
436 }
437}
438
439void GBMemoryDMA(struct GB* gb, uint16_t base) {
440 if (base > 0xF100) {
441 return;
442 }
443 mTimingDeschedule(&gb->timing, &gb->memory.dmaEvent);
444 mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8);
445 if (gb->cpu->cycles + 8 < gb->cpu->nextEvent) {
446 gb->cpu->nextEvent = gb->cpu->cycles + 8;
447 }
448 gb->memory.dmaSource = base;
449 gb->memory.dmaDest = 0;
450 gb->memory.dmaRemaining = 0xA0;
451}
452
453void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
454 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
455 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
456 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
457 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
458 gb->memory.hdmaSource &= 0xFFF0;
459 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
460 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
461 return;
462 }
463 gb->memory.hdmaDest &= 0x1FF0;
464 gb->memory.hdmaDest |= 0x8000;
465 bool wasHdma = gb->memory.isHdma;
466 gb->memory.isHdma = value & 0x80;
467 if ((!wasHdma && !gb->memory.isHdma) || gb->video.mode == 0) {
468 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
469 gb->cpuBlocked = true;
470 mTimingSchedule(&gb->timing, &gb->memory.hdmaEvent, 0);
471 gb->cpu->nextEvent = gb->cpu->cycles;
472 }
473}
474
475void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
476 struct GB* gb = context;
477 int dmaRemaining = gb->memory.dmaRemaining;
478 gb->memory.dmaRemaining = 0;
479 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
480 // TODO: Can DMA write OAM during modes 2-3?
481 gb->video.oam.raw[gb->memory.dmaDest] = b;
482 gb->video.renderer->writeOAM(gb->video.renderer, gb->memory.dmaDest);
483 ++gb->memory.dmaSource;
484 ++gb->memory.dmaDest;
485 gb->memory.dmaRemaining = dmaRemaining - 1;
486 if (gb->memory.dmaRemaining) {
487 mTimingSchedule(timing, &gb->memory.dmaEvent, 4 - cyclesLate);
488 }
489}
490
491void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
492 struct GB* gb = context;
493 gb->cpuBlocked = true;
494 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
495 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
496 ++gb->memory.hdmaSource;
497 ++gb->memory.hdmaDest;
498 --gb->memory.hdmaRemaining;
499 if (gb->memory.hdmaRemaining) {
500 mTimingDeschedule(timing, &gb->memory.hdmaEvent);
501 mTimingSchedule(timing, &gb->memory.hdmaEvent, 2 - cyclesLate);
502 } else {
503 gb->cpuBlocked = false;
504 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
505 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
506 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
507 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
508 if (gb->memory.isHdma) {
509 --gb->memory.io[REG_HDMA5];
510 if (gb->memory.io[REG_HDMA5] == 0xFF) {
511 gb->memory.isHdma = false;
512 }
513 } else {
514 gb->memory.io[REG_HDMA5] = 0xFF;
515 }
516 }
517}
518
519void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment) {
520 struct GB* gb = (struct GB*) cpu->master;
521 struct GBMemory* memory = &gb->memory;
522 int8_t oldValue = -1;
523
524 switch (address >> 12) {
525 case GB_REGION_CART_BANK0:
526 case GB_REGION_CART_BANK0 + 1:
527 case GB_REGION_CART_BANK0 + 2:
528 case GB_REGION_CART_BANK0 + 3:
529 _pristineCow(gb);
530 oldValue = memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
531 memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)] = value;
532 break;
533 case GB_REGION_CART_BANK1:
534 case GB_REGION_CART_BANK1 + 1:
535 case GB_REGION_CART_BANK1 + 2:
536 case GB_REGION_CART_BANK1 + 3:
537 _pristineCow(gb);
538 if (segment < 0) {
539 oldValue = memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
540 memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)] = value;
541 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
542 oldValue = memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
543 memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0] = value;
544 } else {
545 return;
546 }
547 break;
548 case GB_REGION_VRAM:
549 case GB_REGION_VRAM + 1:
550 if (segment < 0) {
551 oldValue = gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
552 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
553 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank);
554 } else if (segment < 2) {
555 oldValue = gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0];
556 gb->video.vramBank[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0] = value;
557 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0);
558 } else {
559 return;
560 }
561 break;
562 case GB_REGION_EXTERNAL_RAM:
563 case GB_REGION_EXTERNAL_RAM + 1:
564 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
565 return;
566 case GB_REGION_WORKING_RAM_BANK0:
567 case GB_REGION_WORKING_RAM_BANK0 + 2:
568 oldValue = memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
569 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
570 break;
571 case GB_REGION_WORKING_RAM_BANK1:
572 if (segment < 0) {
573 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
574 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
575 } else if (segment < 8) {
576 oldValue = memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0];
577 memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0] = value;
578 } else {
579 return;
580 }
581 break;
582 default:
583 if (address < GB_BASE_OAM) {
584 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
585 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
586 } else if (address < GB_BASE_UNUSABLE) {
587 oldValue = gb->video.oam.raw[address & 0xFF];
588 gb->video.oam.raw[address & 0xFF] = value;
589 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
590 } else if (address < GB_BASE_HRAM) {
591 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
592 return;
593 } else if (address < GB_BASE_IE) {
594 oldValue = memory->hram[address & GB_SIZE_HRAM];
595 memory->hram[address & GB_SIZE_HRAM] = value;
596 } else {
597 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
598 return;
599 }
600 }
601 if (old) {
602 *old = oldValue;
603 }
604}
605
606void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
607 const struct GBMemory* memory = &gb->memory;
608 memcpy(state->wram, memory->wram, GB_SIZE_WORKING_RAM);
609 memcpy(state->hram, memory->hram, GB_SIZE_HRAM);
610 STORE_16LE(memory->currentBank, 0, &state->memory.currentBank);
611 state->memory.wramCurrentBank = memory->wramCurrentBank;
612 state->memory.sramCurrentBank = memory->sramCurrentBank;
613
614 STORE_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
615 STORE_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
616
617 STORE_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
618 STORE_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
619
620 STORE_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
621 state->memory.dmaRemaining = memory->dmaRemaining;
622 memcpy(state->memory.rtcRegs, memory->rtcRegs, sizeof(state->memory.rtcRegs));
623
624 STORE_32LE(memory->dmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.dmaNext);
625 STORE_32LE(memory->hdmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.hdmaNext);
626
627 GBSerializedMemoryFlags flags = 0;
628 flags = GBSerializedMemoryFlagsSetSramAccess(flags, memory->sramAccess);
629 flags = GBSerializedMemoryFlagsSetRtcAccess(flags, memory->rtcAccess);
630 flags = GBSerializedMemoryFlagsSetRtcLatched(flags, memory->rtcLatched);
631 flags = GBSerializedMemoryFlagsSetIme(flags, memory->ime);
632 flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
633 flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
634 STORE_16LE(flags, 0, &state->memory.flags);
635
636 switch (memory->mbcType) {
637 case GB_MBC1:
638 state->memory.mbc1.mode = memory->mbcState.mbc1.mode;
639 state->memory.mbc1.multicartStride = memory->mbcState.mbc1.multicartStride;
640 break;
641 case GB_MBC3_RTC:
642 STORE_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
643 break;
644 case GB_MBC7:
645 state->memory.mbc7.state = memory->mbcState.mbc7.state;
646 state->memory.mbc7.eeprom = memory->mbcState.mbc7.eeprom;
647 state->memory.mbc7.address = memory->mbcState.mbc7.address;
648 state->memory.mbc7.access = memory->mbcState.mbc7.access;
649 state->memory.mbc7.latch = memory->mbcState.mbc7.latch;
650 state->memory.mbc7.srBits = memory->mbcState.mbc7.srBits;
651 STORE_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
652 STORE_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
653 break;
654 default:
655 break;
656 }
657}
658
659void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
660 struct GBMemory* memory = &gb->memory;
661 memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
662 memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
663 LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
664 memory->wramCurrentBank = state->memory.wramCurrentBank;
665 memory->sramCurrentBank = state->memory.sramCurrentBank;
666
667 GBMBCSwitchBank(gb, memory->currentBank);
668 GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
669 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
670
671 LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
672 LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
673
674 LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
675 LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
676
677 LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
678 memory->dmaRemaining = state->memory.dmaRemaining;
679 memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
680
681 uint32_t when;
682 LOAD_32LE(when, 0, &state->memory.dmaNext);
683 if (memory->dmaRemaining) {
684 mTimingSchedule(&gb->timing, &memory->dmaEvent, when);
685 }
686 LOAD_32LE(when, 0, &state->memory.hdmaNext);
687 if (memory->hdmaRemaining) {
688 mTimingSchedule(&gb->timing, &memory->hdmaEvent, when);
689 }
690
691 GBSerializedMemoryFlags flags;
692 LOAD_16LE(flags, 0, &state->memory.flags);
693 memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
694 memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
695 memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
696 memory->ime = GBSerializedMemoryFlagsGetIme(flags);
697 memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
698 memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
699
700 switch (memory->mbcType) {
701 case GB_MBC1:
702 memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
703 memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
704 if (memory->mbcState.mbc1.mode) {
705 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
706 }
707 break;
708 case GB_MBC3_RTC:
709 // TODO?
710 //LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
711 break;
712 case GB_MBC7:
713 memory->mbcState.mbc7.state = state->memory.mbc7.state;
714 memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
715 memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
716 memory->mbcState.mbc7.access = state->memory.mbc7.access;
717 memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
718 memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
719 LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
720 LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
721 break;
722 default:
723 break;
724 }
725}
726
727void _pristineCow(struct GB* gb) {
728 if (!gb->isPristine) {
729 return;
730 }
731 void* newRom = anonymousMemoryMap(GB_SIZE_CART_MAX);
732 memcpy(newRom, gb->memory.rom, gb->memory.romSize);
733 memset(((uint8_t*) newRom) + gb->memory.romSize, 0xFF, GB_SIZE_CART_MAX - gb->memory.romSize);
734 if (gb->memory.rom == gb->memory.romBase) {
735 gb->memory.romBase = newRom;
736 }
737 gb->memory.rom = newRom;
738 GBMBCSwitchBank(gb, gb->memory.currentBank);
739 gb->isPristine = false;
740}