src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/math.h"
16#include "util/memory.h"
17
18#define IDLE_LOOP_THRESHOLD 10000
19
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.romMask = 0;
54 gba->memory.hw.p = gba;
55
56 int i;
57 for (i = 0; i < 16; ++i) {
58 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
59 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
60 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
61 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
62 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
63 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
64 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
65 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
66 }
67 for (; i < 256; ++i) {
68 gba->memory.waitstatesNonseq16[i] = 0;
69 gba->memory.waitstatesSeq16[i] = 0;
70 gba->memory.waitstatesNonseq32[i] = 0;
71 gba->memory.waitstatesSeq32[i] = 0;
72 }
73
74 gba->memory.activeRegion = -1;
75 cpu->memory.activeRegion = 0;
76 cpu->memory.activeMask = 0;
77 cpu->memory.setActiveRegion = GBASetActiveRegion;
78 cpu->memory.activeSeqCycles32 = 0;
79 cpu->memory.activeSeqCycles16 = 0;
80 cpu->memory.activeNonseqCycles32 = 0;
81 cpu->memory.activeNonseqCycles16 = 0;
82 gba->memory.biosPrefetch = 0;
83}
84
85void GBAMemoryDeinit(struct GBA* gba) {
86 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
87 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
88 if (gba->memory.rom) {
89 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
90 }
91 GBASavedataDeinit(&gba->memory.savedata);
92}
93
94void GBAMemoryReset(struct GBA* gba) {
95 if (gba->memory.wram) {
96 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
97 }
98 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
99 if (gba->pristineRom && !gba->memory.rom) {
100 // Multiboot
101 memcpy(gba->memory.wram, gba->pristineRom, gba->pristineRomSize);
102 }
103
104 if (gba->memory.iwram) {
105 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
106 }
107 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
108
109 memset(gba->memory.io, 0, sizeof(gba->memory.io));
110 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
111 int i;
112 for (i = 0; i < 4; ++i) {
113 gba->memory.dma[i].count = 0x4000;
114 gba->memory.dma[i].nextEvent = INT_MAX;
115 }
116 gba->memory.dma[3].count = 0x10000;
117 gba->memory.activeDMA = -1;
118 gba->memory.nextDMA = INT_MAX;
119 gba->memory.eventDiff = 0;
120
121 gba->memory.prefetch = false;
122 gba->memory.lastPrefetchedPc = 0;
123
124 if (!gba->memory.wram || !gba->memory.iwram) {
125 GBAMemoryDeinit(gba);
126 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
127 }
128}
129
130static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
131 struct ARMInstructionInfo info;
132 uint32_t nextAddress = address;
133 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
134 if (cpu->executionMode == MODE_THUMB) {
135 while (true) {
136 uint16_t opcode;
137 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
138 ARMDecodeThumb(opcode, &info);
139 switch (info.branchType) {
140 case ARM_BRANCH_NONE:
141 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
142 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
143 gba->idleDetectionStep = -1;
144 return;
145 }
146 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
147 uint32_t offset = 0;
148 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
149 offset = info.memory.offset.immediate;
150 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
151 int reg = info.memory.offset.reg;
152 if (gba->cachedRegisters[reg]) {
153 gba->idleDetectionStep = -1;
154 return;
155 }
156 offset = gba->cachedRegisters[reg];
157 }
158 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
159 loadAddress -= offset;
160 } else {
161 loadAddress += offset;
162 }
163 if ((loadAddress >> BASE_OFFSET) == REGION_IO && !GBAIOIsReadConstant(loadAddress)) {
164 gba->idleDetectionStep = -1;
165 return;
166 }
167 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
168 gba->taintedRegisters[info.op1.reg] = true;
169 } else {
170 switch (info.memory.width) {
171 case 1:
172 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
173 break;
174 case 2:
175 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
176 break;
177 case 4:
178 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
179 break;
180 }
181 }
182 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
183 gba->taintedRegisters[info.op1.reg] = true;
184 }
185 nextAddress += WORD_SIZE_THUMB;
186 break;
187 case ARM_BRANCH:
188 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
189 gba->idleLoop = address;
190 gba->idleOptimization = IDLE_LOOP_REMOVE;
191 }
192 gba->idleDetectionStep = -1;
193 return;
194 default:
195 gba->idleDetectionStep = -1;
196 return;
197 }
198 }
199 } else {
200 gba->idleDetectionStep = -1;
201 }
202}
203
204static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
205 struct GBA* gba = (struct GBA*) cpu->master;
206 struct GBAMemory* memory = &gba->memory;
207
208 int newRegion = address >> BASE_OFFSET;
209 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
210 if (address == gba->idleLoop) {
211 if (gba->haltPending) {
212 gba->haltPending = false;
213 GBAHalt(gba);
214 } else {
215 gba->haltPending = true;
216 }
217 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
218 if (address == gba->lastJump) {
219 switch (gba->idleDetectionStep) {
220 case 0:
221 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
222 ++gba->idleDetectionStep;
223 break;
224 case 1:
225 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
226 gba->idleDetectionStep = -1;
227 ++gba->idleDetectionFailures;
228 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
229 gba->idleOptimization = IDLE_LOOP_IGNORE;
230 }
231 break;
232 }
233 _analyzeForIdleLoop(gba, cpu, address);
234 break;
235 }
236 } else {
237 gba->idleDetectionStep = 0;
238 }
239 }
240 }
241
242 gba->lastJump = address;
243 memory->lastPrefetchedPc = 0;
244 memory->lastPrefetchedLoads = 0;
245 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
246 return;
247 }
248
249 if (memory->activeRegion == REGION_BIOS) {
250 memory->biosPrefetch = cpu->prefetch[1];
251 }
252 memory->activeRegion = newRegion;
253 switch (newRegion) {
254 case REGION_BIOS:
255 cpu->memory.activeRegion = memory->bios;
256 cpu->memory.activeMask = SIZE_BIOS - 1;
257 break;
258 case REGION_WORKING_RAM:
259 cpu->memory.activeRegion = memory->wram;
260 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
261 break;
262 case REGION_WORKING_IRAM:
263 cpu->memory.activeRegion = memory->iwram;
264 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
265 break;
266 case REGION_PALETTE_RAM:
267 cpu->memory.activeRegion = (uint32_t*) gba->video.palette;
268 cpu->memory.activeMask = SIZE_PALETTE_RAM - 1;
269 break;
270 case REGION_VRAM:
271 if (address < 0x06010000) {
272 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
273 cpu->memory.activeMask = 0x0000FFFF;
274 } else {
275 cpu->memory.activeRegion = (uint32_t*) &gba->video.renderer->vram[0x8000];
276 cpu->memory.activeMask = 0x00007FFF;
277 }
278 break;
279 case REGION_OAM:
280 cpu->memory.activeRegion = (uint32_t*) gba->video.oam.raw;
281 cpu->memory.activeMask = SIZE_OAM - 1;
282 break;
283 case REGION_CART0:
284 case REGION_CART0_EX:
285 case REGION_CART1:
286 case REGION_CART1_EX:
287 case REGION_CART2:
288 case REGION_CART2_EX:
289 cpu->memory.activeRegion = memory->rom;
290 cpu->memory.activeMask = memory->romMask;
291 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
292 break;
293 }
294 // Fall through
295 default:
296 memory->activeRegion = -1;
297 cpu->memory.activeRegion = _deadbeef;
298 cpu->memory.activeMask = 0;
299 enum GBALogLevel errorLevel = GBA_LOG_FATAL;
300 if (gba->yankedRomSize || !gba->hardCrash) {
301 errorLevel = GBA_LOG_GAME_ERROR;
302 }
303 GBALog(gba, errorLevel, "Jumped to invalid address: %08X", address);
304 return;
305 }
306 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
307 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
308 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
309 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
310}
311
312#define LOAD_BAD \
313 if (gba->performingDMA) { \
314 value = gba->bus; \
315 } else { \
316 value = cpu->prefetch[1]; \
317 if (cpu->executionMode == MODE_THUMB) { \
318 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
319 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
320 case REGION_BIOS: \
321 case REGION_OAM: \
322 /* This isn't right half the time, but we don't have $+6 handy */ \
323 value <<= 16; \
324 value |= cpu->prefetch[0]; \
325 break; \
326 case REGION_WORKING_IRAM: \
327 /* This doesn't handle prefetch clobbering */ \
328 if (cpu->gprs[ARM_PC] & 2) { \
329 value |= cpu->prefetch[0] << 16; \
330 } else { \
331 value <<= 16; \
332 value |= cpu->prefetch[0]; \
333 } \
334 default: \
335 value |= value << 16; \
336 } \
337 } \
338 }
339
340#define LOAD_BIOS \
341 if (address < SIZE_BIOS) { \
342 if (memory->activeRegion == REGION_BIOS) { \
343 LOAD_32(value, address, memory->bios); \
344 } else { \
345 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
346 value = memory->biosPrefetch; \
347 } \
348 } else { \
349 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
350 LOAD_BAD; \
351 }
352
353#define LOAD_WORKING_RAM \
354 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
355 wait += waitstatesRegion[REGION_WORKING_RAM];
356
357#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
358#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
359
360#define LOAD_PALETTE_RAM \
361 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
362 wait += waitstatesRegion[REGION_PALETTE_RAM];
363
364#define LOAD_VRAM \
365 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
366 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
367 } else { \
368 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
369 } \
370 wait += waitstatesRegion[REGION_VRAM];
371
372#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
373
374#define LOAD_CART \
375 wait += waitstatesRegion[address >> BASE_OFFSET]; \
376 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
377 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
378 } else { \
379 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
380 value = ((address & ~3) >> 1) & 0xFFFF; \
381 value |= (((address & ~3) + 2) >> 1) << 16; \
382 }
383
384#define LOAD_SRAM \
385 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
386 value = GBALoad8(cpu, address, 0); \
387 value |= value << 8; \
388 value |= value << 16;
389
390uint32_t GBALoadBad(struct ARMCore* cpu) {
391 struct GBA* gba = (struct GBA*) cpu->master;
392 uint32_t value = 0;
393 LOAD_BAD;
394 return value;
395}
396
397uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
398 struct GBA* gba = (struct GBA*) cpu->master;
399 struct GBAMemory* memory = &gba->memory;
400 uint32_t value = 0;
401 int wait = 0;
402 char* waitstatesRegion = memory->waitstatesNonseq32;
403
404 switch (address >> BASE_OFFSET) {
405 case REGION_BIOS:
406 LOAD_BIOS;
407 break;
408 case REGION_WORKING_RAM:
409 LOAD_WORKING_RAM;
410 break;
411 case REGION_WORKING_IRAM:
412 LOAD_WORKING_IRAM;
413 break;
414 case REGION_IO:
415 LOAD_IO;
416 break;
417 case REGION_PALETTE_RAM:
418 LOAD_PALETTE_RAM;
419 break;
420 case REGION_VRAM:
421 LOAD_VRAM;
422 break;
423 case REGION_OAM:
424 LOAD_OAM;
425 break;
426 case REGION_CART0:
427 case REGION_CART0_EX:
428 case REGION_CART1:
429 case REGION_CART1_EX:
430 case REGION_CART2:
431 case REGION_CART2_EX:
432 LOAD_CART;
433 break;
434 case REGION_CART_SRAM:
435 case REGION_CART_SRAM_MIRROR:
436 LOAD_SRAM;
437 break;
438 default:
439 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
440 LOAD_BAD;
441 break;
442 }
443
444 if (cycleCounter) {
445 wait += 2;
446 if (address >> BASE_OFFSET < REGION_CART0) {
447 wait = GBAMemoryStall(cpu, wait);
448 }
449 *cycleCounter += wait;
450 }
451 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
452 int rotate = (address & 3) << 3;
453 return ROR(value, rotate);
454}
455
456uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
457 struct GBA* gba = (struct GBA*) cpu->master;
458 struct GBAMemory* memory = &gba->memory;
459 uint32_t value = 0;
460 int wait = 0;
461
462 switch (address >> BASE_OFFSET) {
463 case REGION_BIOS:
464 if (address < SIZE_BIOS) {
465 if (memory->activeRegion == REGION_BIOS) {
466 LOAD_16(value, address, memory->bios);
467 } else {
468 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
469 value = (memory->biosPrefetch >> ((address & 2) * 8)) & 0xFFFF;
470 }
471 } else {
472 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
473 LOAD_BAD;
474 value = (value >> ((address & 2) * 8)) & 0xFFFF;
475 }
476 break;
477 case REGION_WORKING_RAM:
478 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
479 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
480 break;
481 case REGION_WORKING_IRAM:
482 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
483 break;
484 case REGION_IO:
485 value = GBAIORead(gba, address & (SIZE_IO - 2));
486 break;
487 case REGION_PALETTE_RAM:
488 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
489 break;
490 case REGION_VRAM:
491 if ((address & 0x0001FFFF) < SIZE_VRAM) {
492 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
493 } else {
494 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
495 }
496 break;
497 case REGION_OAM:
498 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
499 break;
500 case REGION_CART0:
501 case REGION_CART0_EX:
502 case REGION_CART1:
503 case REGION_CART1_EX:
504 case REGION_CART2:
505 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
506 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
507 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
508 } else {
509 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
510 value = (address >> 1) & 0xFFFF;
511 }
512 break;
513 case REGION_CART2_EX:
514 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
515 if (memory->savedata.type == SAVEDATA_EEPROM) {
516 value = GBASavedataReadEEPROM(&memory->savedata);
517 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
518 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
519 } else {
520 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
521 value = (address >> 1) & 0xFFFF;
522 }
523 break;
524 case REGION_CART_SRAM:
525 case REGION_CART_SRAM_MIRROR:
526 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
527 value = GBALoad8(cpu, address, 0);
528 value |= value << 8;
529 break;
530 default:
531 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
532 LOAD_BAD;
533 value = (value >> ((address & 2) * 8)) & 0xFFFF;
534 break;
535 }
536
537 if (cycleCounter) {
538 wait += 2;
539 if (address >> BASE_OFFSET < REGION_CART0) {
540 wait = GBAMemoryStall(cpu, wait);
541 }
542 *cycleCounter += wait;
543 }
544 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
545 int rotate = (address & 1) << 3;
546 return ROR(value, rotate);
547}
548
549uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
550 struct GBA* gba = (struct GBA*) cpu->master;
551 struct GBAMemory* memory = &gba->memory;
552 uint32_t value = 0;
553 int wait = 0;
554
555 switch (address >> BASE_OFFSET) {
556 case REGION_BIOS:
557 if (address < SIZE_BIOS) {
558 if (memory->activeRegion == REGION_BIOS) {
559 value = ((uint8_t*) memory->bios)[address];
560 } else {
561 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
562 value = (memory->biosPrefetch >> ((address & 3) * 8)) & 0xFF;
563 }
564 } else {
565 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
566 LOAD_BAD;
567 value = (value >> ((address & 3) * 8)) & 0xFF;
568 }
569 break;
570 case REGION_WORKING_RAM:
571 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
572 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
573 break;
574 case REGION_WORKING_IRAM:
575 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
576 break;
577 case REGION_IO:
578 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
579 break;
580 case REGION_PALETTE_RAM:
581 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
582 break;
583 case REGION_VRAM:
584 if ((address & 0x0001FFFF) < SIZE_VRAM) {
585 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
586 } else {
587 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
588 }
589 break;
590 case REGION_OAM:
591 value = ((uint8_t*) gba->video.oam.raw)[address & (SIZE_OAM - 1)];
592 break;
593 case REGION_CART0:
594 case REGION_CART0_EX:
595 case REGION_CART1:
596 case REGION_CART1_EX:
597 case REGION_CART2:
598 case REGION_CART2_EX:
599 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
600 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
601 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
602 } else {
603 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
604 value = (address >> 1) & 0xFF;
605 }
606 break;
607 case REGION_CART_SRAM:
608 case REGION_CART_SRAM_MIRROR:
609 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
610 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
611 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
612 GBASavedataInitSRAM(&memory->savedata);
613 }
614 if (gba->performingDMA == 1) {
615 break;
616 }
617 if (memory->savedata.type == SAVEDATA_SRAM) {
618 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
619 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
620 value = GBASavedataReadFlash(&memory->savedata, address);
621 } else if (memory->hw.devices & HW_TILT) {
622 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
623 } else {
624 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
625 value = 0xFF;
626 }
627 value &= 0xFF;
628 break;
629 default:
630 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
631 LOAD_BAD;
632 value = (value >> ((address & 3) * 8)) & 0xFF;
633 break;
634 }
635
636 if (cycleCounter) {
637 wait += 2;
638 if (address >> BASE_OFFSET < REGION_CART0) {
639 wait = GBAMemoryStall(cpu, wait);
640 }
641 *cycleCounter += wait;
642 }
643 return value;
644}
645
646#define STORE_WORKING_RAM \
647 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
648 wait += waitstatesRegion[REGION_WORKING_RAM];
649
650#define STORE_WORKING_IRAM \
651 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
652
653#define STORE_IO \
654 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
655
656#define STORE_PALETTE_RAM \
657 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
658 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
659 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
660 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
661
662#define STORE_VRAM \
663 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
664 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
665 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC) + 2); \
666 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC)); \
667 } else { \
668 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
669 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC) + 2); \
670 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC)); \
671 } \
672 wait += waitstatesRegion[REGION_VRAM];
673
674#define STORE_OAM \
675 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
676 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
677 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
678
679#define STORE_CART \
680 wait += waitstatesRegion[address >> BASE_OFFSET]; \
681 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
682
683#define STORE_SRAM \
684 if (address & 0x3) { \
685 GBALog(gba, GBA_LOG_GAME_ERROR, "Unaligned SRAM Store32: 0x%08X", address); \
686 value = 0; \
687 } \
688 GBAStore8(cpu, address & ~0x3, value, cycleCounter); \
689 GBAStore8(cpu, (address & ~0x3) | 1, value, cycleCounter); \
690 GBAStore8(cpu, (address & ~0x3) | 2, value, cycleCounter); \
691 GBAStore8(cpu, (address & ~0x3) | 3, value, cycleCounter);
692
693#define STORE_BAD \
694 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
695
696void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
697 struct GBA* gba = (struct GBA*) cpu->master;
698 struct GBAMemory* memory = &gba->memory;
699 int wait = 0;
700 char* waitstatesRegion = memory->waitstatesNonseq32;
701
702 switch (address >> BASE_OFFSET) {
703 case REGION_WORKING_RAM:
704 STORE_WORKING_RAM;
705 break;
706 case REGION_WORKING_IRAM:
707 STORE_WORKING_IRAM
708 break;
709 case REGION_IO:
710 STORE_IO;
711 break;
712 case REGION_PALETTE_RAM:
713 STORE_PALETTE_RAM;
714 break;
715 case REGION_VRAM:
716 STORE_VRAM;
717 break;
718 case REGION_OAM:
719 STORE_OAM;
720 break;
721 case REGION_CART0:
722 case REGION_CART0_EX:
723 case REGION_CART1:
724 case REGION_CART1_EX:
725 case REGION_CART2:
726 case REGION_CART2_EX:
727 STORE_CART;
728 break;
729 case REGION_CART_SRAM:
730 case REGION_CART_SRAM_MIRROR:
731 STORE_SRAM;
732 break;
733 default:
734 STORE_BAD;
735 break;
736 }
737
738 if (cycleCounter) {
739 ++wait;
740 if (address >> BASE_OFFSET < REGION_CART0) {
741 wait = GBAMemoryStall(cpu, wait);
742 }
743 *cycleCounter += wait;
744 }
745}
746
747void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
748 struct GBA* gba = (struct GBA*) cpu->master;
749 struct GBAMemory* memory = &gba->memory;
750 int wait = 0;
751
752 switch (address >> BASE_OFFSET) {
753 case REGION_WORKING_RAM:
754 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
755 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
756 break;
757 case REGION_WORKING_IRAM:
758 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
759 break;
760 case REGION_IO:
761 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
762 break;
763 case REGION_PALETTE_RAM:
764 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
765 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
766 break;
767 case REGION_VRAM:
768 if ((address & 0x0001FFFF) < SIZE_VRAM) {
769 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
770 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
771 } else {
772 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
773 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x00017FFE);
774 }
775 break;
776 case REGION_OAM:
777 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
778 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
779 break;
780 case REGION_CART0:
781 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
782 uint32_t reg = address & 0xFFFFFE;
783 GBAHardwareGPIOWrite(&memory->hw, reg, value);
784 } else {
785 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
786 }
787 break;
788 case REGION_CART2_EX:
789 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
790 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
791 GBASavedataInitEEPROM(&memory->savedata);
792 }
793 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
794 break;
795 case REGION_CART_SRAM:
796 case REGION_CART_SRAM_MIRROR:
797 GBAStore8(cpu, (address & ~0x1), value, cycleCounter);
798 GBAStore8(cpu, (address & ~0x1) | 1, value, cycleCounter);
799 break;
800 default:
801 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
802 break;
803 }
804
805 if (cycleCounter) {
806 ++wait;
807 if (address >> BASE_OFFSET < REGION_CART0) {
808 wait = GBAMemoryStall(cpu, wait);
809 }
810 *cycleCounter += wait;
811 }
812}
813
814void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
815 struct GBA* gba = (struct GBA*) cpu->master;
816 struct GBAMemory* memory = &gba->memory;
817 int wait = 0;
818
819 switch (address >> BASE_OFFSET) {
820 case REGION_WORKING_RAM:
821 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
822 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
823 break;
824 case REGION_WORKING_IRAM:
825 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
826 break;
827 case REGION_IO:
828 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
829 break;
830 case REGION_PALETTE_RAM:
831 GBAStore16(cpu, address & ~1, ((uint8_t) value) | ((uint8_t) value << 8), cycleCounter);
832 break;
833 case REGION_VRAM:
834 if ((address & 0x0001FFFF) >= ((GBARegisterDISPCNTGetMode(gba->memory.io[REG_DISPCNT >> 1]) == 4) ? 0x00014000 : 0x00010000)) {
835 // TODO: check BG mode
836 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
837 break;
838 }
839 gba->video.renderer->vram[(address & 0x1FFFE) >> 1] = ((uint8_t) value) | (value << 8);
840 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
841 break;
842 case REGION_OAM:
843 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
844 break;
845 case REGION_CART0:
846 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
847 break;
848 case REGION_CART_SRAM:
849 case REGION_CART_SRAM_MIRROR:
850 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
851 if (address == SAVEDATA_FLASH_BASE) {
852 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
853 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
854 } else {
855 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
856 GBASavedataInitSRAM(&memory->savedata);
857 }
858 }
859 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
860 GBASavedataWriteFlash(&memory->savedata, address, value);
861 } else if (memory->savedata.type == SAVEDATA_SRAM) {
862 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
863 memory->savedata.dirty |= SAVEDATA_DIRT_NEW;
864 } else if (memory->hw.devices & HW_TILT) {
865 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
866 } else {
867 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
868 }
869 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
870 break;
871 default:
872 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
873 break;
874 }
875
876 if (cycleCounter) {
877 ++wait;
878 if (address >> BASE_OFFSET < REGION_CART0) {
879 wait = GBAMemoryStall(cpu, wait);
880 }
881 *cycleCounter += wait;
882 }
883}
884
885uint32_t GBAView32(struct ARMCore* cpu, uint32_t address) {
886 struct GBA* gba = (struct GBA*) cpu->master;
887 uint32_t value = 0;
888 address &= ~3;
889 switch (address >> BASE_OFFSET) {
890 case REGION_BIOS:
891 if (address < SIZE_BIOS) {
892 LOAD_32(value, address, gba->memory.bios);
893 }
894 break;
895 case REGION_WORKING_RAM:
896 case REGION_WORKING_IRAM:
897 case REGION_PALETTE_RAM:
898 case REGION_VRAM:
899 case REGION_OAM:
900 case REGION_CART0:
901 case REGION_CART0_EX:
902 case REGION_CART1:
903 case REGION_CART1_EX:
904 case REGION_CART2:
905 case REGION_CART2_EX:
906 value = GBALoad32(cpu, address, 0);
907 break;
908 case REGION_IO:
909 if ((address & OFFSET_MASK) < REG_MAX) {
910 value = gba->memory.io[(address & OFFSET_MASK) >> 1];
911 value |= gba->memory.io[((address & OFFSET_MASK) >> 1) + 1] << 16;
912 }
913 break;
914 case REGION_CART_SRAM:
915 value = GBALoad8(cpu, address, 0);
916 value |= GBALoad8(cpu, address + 1, 0) << 8;
917 value |= GBALoad8(cpu, address + 2, 0) << 16;
918 value |= GBALoad8(cpu, address + 3, 0) << 24;
919 break;
920 default:
921 break;
922 }
923 return value;
924}
925
926uint16_t GBAView16(struct ARMCore* cpu, uint32_t address) {
927 struct GBA* gba = (struct GBA*) cpu->master;
928 uint16_t value = 0;
929 address &= ~1;
930 switch (address >> BASE_OFFSET) {
931 case REGION_BIOS:
932 if (address < SIZE_BIOS) {
933 LOAD_16(value, address, gba->memory.bios);
934 }
935 break;
936 case REGION_WORKING_RAM:
937 case REGION_WORKING_IRAM:
938 case REGION_PALETTE_RAM:
939 case REGION_VRAM:
940 case REGION_OAM:
941 case REGION_CART0:
942 case REGION_CART0_EX:
943 case REGION_CART1:
944 case REGION_CART1_EX:
945 case REGION_CART2:
946 case REGION_CART2_EX:
947 value = GBALoad16(cpu, address, 0);
948 break;
949 case REGION_IO:
950 if ((address & OFFSET_MASK) < REG_MAX) {
951 value = gba->memory.io[(address & OFFSET_MASK) >> 1];
952 }
953 break;
954 case REGION_CART_SRAM:
955 value = GBALoad8(cpu, address, 0);
956 value |= GBALoad8(cpu, address + 1, 0) << 8;
957 break;
958 default:
959 break;
960 }
961 return value;
962}
963
964uint8_t GBAView8(struct ARMCore* cpu, uint32_t address) {
965 struct GBA* gba = (struct GBA*) cpu->master;
966 uint8_t value = 0;
967 switch (address >> BASE_OFFSET) {
968 case REGION_BIOS:
969 if (address < SIZE_BIOS) {
970 value = ((uint8_t*) gba->memory.bios)[address];
971 }
972 break;
973 case REGION_WORKING_RAM:
974 case REGION_WORKING_IRAM:
975 case REGION_CART0:
976 case REGION_CART0_EX:
977 case REGION_CART1:
978 case REGION_CART1_EX:
979 case REGION_CART2:
980 case REGION_CART2_EX:
981 case REGION_CART_SRAM:
982 value = GBALoad8(cpu, address, 0);
983 break;
984 case REGION_IO:
985 case REGION_PALETTE_RAM:
986 case REGION_VRAM:
987 case REGION_OAM:
988 value = GBAView16(cpu, address) >> ((address & 1) * 8);
989 break;
990 default:
991 break;
992 }
993 return value;
994}
995
996void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
997 struct GBA* gba = (struct GBA*) cpu->master;
998 struct GBAMemory* memory = &gba->memory;
999 int32_t oldValue = -1;
1000
1001 switch (address >> BASE_OFFSET) {
1002 case REGION_WORKING_RAM:
1003 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
1004 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
1005 break;
1006 case REGION_WORKING_IRAM:
1007 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
1008 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
1009 break;
1010 case REGION_IO:
1011 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
1012 break;
1013 case REGION_PALETTE_RAM:
1014 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
1015 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
1016 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
1017 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
1018 break;
1019 case REGION_VRAM:
1020 if ((address & 0x0001FFFF) < SIZE_VRAM) {
1021 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
1022 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
1023 } else {
1024 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
1025 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
1026 }
1027 break;
1028 case REGION_OAM:
1029 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
1030 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
1031 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
1032 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
1033 break;
1034 case REGION_CART0:
1035 case REGION_CART0_EX:
1036 case REGION_CART1:
1037 case REGION_CART1_EX:
1038 case REGION_CART2:
1039 case REGION_CART2_EX:
1040 _pristineCow(gba);
1041 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
1042 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
1043 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1044 }
1045 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
1046 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
1047 break;
1048 case REGION_CART_SRAM:
1049 case REGION_CART_SRAM_MIRROR:
1050 if (memory->savedata.type == SAVEDATA_SRAM) {
1051 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
1052 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
1053 } else {
1054 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1055 }
1056 break;
1057 default:
1058 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
1059 break;
1060 }
1061 if (old) {
1062 *old = oldValue;
1063 }
1064}
1065
1066void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
1067 struct GBA* gba = (struct GBA*) cpu->master;
1068 struct GBAMemory* memory = &gba->memory;
1069 int16_t oldValue = -1;
1070
1071 switch (address >> BASE_OFFSET) {
1072 case REGION_WORKING_RAM:
1073 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
1074 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
1075 break;
1076 case REGION_WORKING_IRAM:
1077 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
1078 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
1079 break;
1080 case REGION_IO:
1081 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
1082 break;
1083 case REGION_PALETTE_RAM:
1084 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
1085 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
1086 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
1087 break;
1088 case REGION_VRAM:
1089 if ((address & 0x0001FFFF) < SIZE_VRAM) {
1090 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
1091 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
1092 } else {
1093 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
1094 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
1095 }
1096 break;
1097 case REGION_OAM:
1098 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
1099 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
1100 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
1101 break;
1102 case REGION_CART0:
1103 case REGION_CART0_EX:
1104 case REGION_CART1:
1105 case REGION_CART1_EX:
1106 case REGION_CART2:
1107 case REGION_CART2_EX:
1108 _pristineCow(gba);
1109 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1110 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1111 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1112 }
1113 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
1114 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
1115 break;
1116 case REGION_CART_SRAM:
1117 case REGION_CART_SRAM_MIRROR:
1118 if (memory->savedata.type == SAVEDATA_SRAM) {
1119 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
1120 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
1121 } else {
1122 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1123 }
1124 break;
1125 default:
1126 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
1127 break;
1128 }
1129 if (old) {
1130 *old = oldValue;
1131 }
1132}
1133
1134void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
1135 struct GBA* gba = (struct GBA*) cpu->master;
1136 struct GBAMemory* memory = &gba->memory;
1137 int8_t oldValue = -1;
1138
1139 switch (address >> BASE_OFFSET) {
1140 case REGION_WORKING_RAM:
1141 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
1142 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
1143 break;
1144 case REGION_WORKING_IRAM:
1145 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
1146 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
1147 break;
1148 case REGION_IO:
1149 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1150 break;
1151 case REGION_PALETTE_RAM:
1152 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1153 break;
1154 case REGION_VRAM:
1155 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1156 break;
1157 case REGION_OAM:
1158 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1159 break;
1160 case REGION_CART0:
1161 case REGION_CART0_EX:
1162 case REGION_CART1:
1163 case REGION_CART1_EX:
1164 case REGION_CART2:
1165 case REGION_CART2_EX:
1166 _pristineCow(gba);
1167 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1168 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1169 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1170 }
1171 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1172 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1173 break;
1174 case REGION_CART_SRAM:
1175 case REGION_CART_SRAM_MIRROR:
1176 if (memory->savedata.type == SAVEDATA_SRAM) {
1177 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1178 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1179 } else {
1180 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1181 }
1182 break;
1183 default:
1184 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1185 break;
1186 }
1187 if (old) {
1188 *old = oldValue;
1189 }
1190}
1191
1192#define LDM_LOOP(LDM) \
1193 for (i = 0; i < 16; i += 4) { \
1194 if (UNLIKELY(mask & (1 << i))) { \
1195 LDM; \
1196 waitstatesRegion = memory->waitstatesSeq32; \
1197 cpu->gprs[i] = value; \
1198 ++wait; \
1199 address += 4; \
1200 } \
1201 if (UNLIKELY(mask & (2 << i))) { \
1202 LDM; \
1203 waitstatesRegion = memory->waitstatesSeq32; \
1204 cpu->gprs[i + 1] = value; \
1205 ++wait; \
1206 address += 4; \
1207 } \
1208 if (UNLIKELY(mask & (4 << i))) { \
1209 LDM; \
1210 waitstatesRegion = memory->waitstatesSeq32; \
1211 cpu->gprs[i + 2] = value; \
1212 ++wait; \
1213 address += 4; \
1214 } \
1215 if (UNLIKELY(mask & (8 << i))) { \
1216 LDM; \
1217 waitstatesRegion = memory->waitstatesSeq32; \
1218 cpu->gprs[i + 3] = value; \
1219 ++wait; \
1220 address += 4; \
1221 } \
1222 }
1223
1224uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1225 struct GBA* gba = (struct GBA*) cpu->master;
1226 struct GBAMemory* memory = &gba->memory;
1227 uint32_t value;
1228 int wait = 0;
1229 char* waitstatesRegion = memory->waitstatesNonseq32;
1230
1231 int i;
1232 int offset = 4;
1233 int popcount = 0;
1234 if (direction & LSM_D) {
1235 offset = -4;
1236 popcount = popcount32(mask);
1237 address -= (popcount << 2) - 4;
1238 }
1239
1240 if (direction & LSM_B) {
1241 address += offset;
1242 }
1243
1244 uint32_t addressMisalign = address & 0x3;
1245 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1246 address &= 0xFFFFFFFC;
1247 }
1248
1249 switch (address >> BASE_OFFSET) {
1250 case REGION_BIOS:
1251 LDM_LOOP(LOAD_BIOS);
1252 break;
1253 case REGION_WORKING_RAM:
1254 LDM_LOOP(LOAD_WORKING_RAM);
1255 break;
1256 case REGION_WORKING_IRAM:
1257 LDM_LOOP(LOAD_WORKING_IRAM);
1258 break;
1259 case REGION_IO:
1260 LDM_LOOP(LOAD_IO);
1261 break;
1262 case REGION_PALETTE_RAM:
1263 LDM_LOOP(LOAD_PALETTE_RAM);
1264 break;
1265 case REGION_VRAM:
1266 LDM_LOOP(LOAD_VRAM);
1267 break;
1268 case REGION_OAM:
1269 LDM_LOOP(LOAD_OAM);
1270 break;
1271 case REGION_CART0:
1272 case REGION_CART0_EX:
1273 case REGION_CART1:
1274 case REGION_CART1_EX:
1275 case REGION_CART2:
1276 case REGION_CART2_EX:
1277 LDM_LOOP(LOAD_CART);
1278 break;
1279 case REGION_CART_SRAM:
1280 case REGION_CART_SRAM_MIRROR:
1281 LDM_LOOP(LOAD_SRAM);
1282 break;
1283 default:
1284 LDM_LOOP(LOAD_BAD);
1285 break;
1286 }
1287
1288 if (cycleCounter) {
1289 ++wait;
1290 if (address >> BASE_OFFSET < REGION_CART0) {
1291 wait = GBAMemoryStall(cpu, wait);
1292 }
1293 *cycleCounter += wait;
1294 }
1295
1296 if (direction & LSM_B) {
1297 address -= offset;
1298 }
1299
1300 if (direction & LSM_D) {
1301 address -= (popcount << 2) + 4;
1302 }
1303
1304 return address | addressMisalign;
1305}
1306
1307#define STM_LOOP(STM) \
1308 for (i = 0; i < 16; i += 4) { \
1309 if (UNLIKELY(mask & (1 << i))) { \
1310 value = cpu->gprs[i]; \
1311 STM; \
1312 waitstatesRegion = memory->waitstatesSeq32; \
1313 ++wait; \
1314 address += 4; \
1315 } \
1316 if (UNLIKELY(mask & (2 << i))) { \
1317 value = cpu->gprs[i + 1]; \
1318 STM; \
1319 waitstatesRegion = memory->waitstatesSeq32; \
1320 ++wait; \
1321 address += 4; \
1322 } \
1323 if (UNLIKELY(mask & (4 << i))) { \
1324 value = cpu->gprs[i + 2]; \
1325 STM; \
1326 waitstatesRegion = memory->waitstatesSeq32; \
1327 ++wait; \
1328 address += 4; \
1329 } \
1330 if (UNLIKELY(mask & (8 << i))) { \
1331 value = cpu->gprs[i + 3]; \
1332 STM; \
1333 waitstatesRegion = memory->waitstatesSeq32; \
1334 ++wait; \
1335 address += 4; \
1336 } \
1337 }
1338
1339uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1340 struct GBA* gba = (struct GBA*) cpu->master;
1341 struct GBAMemory* memory = &gba->memory;
1342 uint32_t value;
1343 int wait = 0;
1344 char* waitstatesRegion = memory->waitstatesNonseq32;
1345
1346 int i;
1347 int offset = 4;
1348 int popcount = 0;
1349 if (direction & LSM_D) {
1350 offset = -4;
1351 popcount = popcount32(mask);
1352 address -= (popcount << 2) - 4;
1353 }
1354
1355 if (direction & LSM_B) {
1356 address += offset;
1357 }
1358
1359 uint32_t addressMisalign = address & 0x3;
1360 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1361 address &= 0xFFFFFFFC;
1362 }
1363
1364 switch (address >> BASE_OFFSET) {
1365 case REGION_WORKING_RAM:
1366 STM_LOOP(STORE_WORKING_RAM);
1367 break;
1368 case REGION_WORKING_IRAM:
1369 STM_LOOP(STORE_WORKING_IRAM);
1370 break;
1371 case REGION_IO:
1372 STM_LOOP(STORE_IO);
1373 break;
1374 case REGION_PALETTE_RAM:
1375 STM_LOOP(STORE_PALETTE_RAM);
1376 break;
1377 case REGION_VRAM:
1378 STM_LOOP(STORE_VRAM);
1379 break;
1380 case REGION_OAM:
1381 STM_LOOP(STORE_OAM);
1382 break;
1383 case REGION_CART0:
1384 case REGION_CART0_EX:
1385 case REGION_CART1:
1386 case REGION_CART1_EX:
1387 case REGION_CART2:
1388 case REGION_CART2_EX:
1389 STM_LOOP(STORE_CART);
1390 break;
1391 case REGION_CART_SRAM:
1392 case REGION_CART_SRAM_MIRROR:
1393 STM_LOOP(STORE_SRAM);
1394 break;
1395 default:
1396 STM_LOOP(STORE_BAD);
1397 break;
1398 }
1399
1400 if (cycleCounter) {
1401 if (address >> BASE_OFFSET < REGION_CART0) {
1402 wait = GBAMemoryStall(cpu, wait);
1403 }
1404 *cycleCounter += wait;
1405 }
1406
1407 if (direction & LSM_B) {
1408 address -= offset;
1409 }
1410
1411 if (direction & LSM_D) {
1412 address -= (popcount << 2) + 4;
1413 }
1414
1415 return address | addressMisalign;
1416}
1417
1418void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1419 struct GBAMemory* memory = &gba->memory;
1420 struct ARMCore* cpu = gba->cpu;
1421 int sram = parameters & 0x0003;
1422 int ws0 = (parameters & 0x000C) >> 2;
1423 int ws0seq = (parameters & 0x0010) >> 4;
1424 int ws1 = (parameters & 0x0060) >> 5;
1425 int ws1seq = (parameters & 0x0080) >> 7;
1426 int ws2 = (parameters & 0x0300) >> 8;
1427 int ws2seq = (parameters & 0x0400) >> 10;
1428 int prefetch = parameters & 0x4000;
1429
1430 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1431 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1432 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1433 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1434
1435 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1436 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1437 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1438
1439 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1440 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1441 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1442
1443 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1444 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1445 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1446
1447 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1448 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1449 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1450
1451 memory->prefetch = prefetch;
1452
1453 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1454 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1455
1456 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1457 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1458}
1459
1460static bool _isValidDMASAD(int dma, uint32_t address) {
1461 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
1462 return false;
1463 }
1464 return address >= BASE_WORKING_RAM;
1465}
1466
1467static bool _isValidDMADAD(int dma, uint32_t address) {
1468 return dma == 3 || address < BASE_CART0;
1469}
1470
1471uint32_t GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1472 struct GBAMemory* memory = &gba->memory;
1473 address &= 0x0FFFFFFE;
1474 if (_isValidDMASAD(dma, address)) {
1475 memory->dma[dma].source = address;
1476 }
1477 return memory->dma[dma].source;
1478}
1479
1480uint32_t GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1481 struct GBAMemory* memory = &gba->memory;
1482 address &= 0x0FFFFFFE;
1483 if (_isValidDMADAD(dma, address)) {
1484 memory->dma[dma].dest = address;
1485 }
1486 return memory->dma[dma].dest;
1487}
1488
1489void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1490 struct GBAMemory* memory = &gba->memory;
1491 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1492}
1493
1494uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1495 struct GBAMemory* memory = &gba->memory;
1496 struct GBADMA* currentDma = &memory->dma[dma];
1497 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1498 if (dma < 3) {
1499 control &= 0xF7E0;
1500 } else {
1501 control &= 0xFFE0;
1502 }
1503 currentDma->reg = control;
1504
1505 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1506 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1507 }
1508
1509 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1510 currentDma->nextSource = currentDma->source;
1511 currentDma->nextDest = currentDma->dest;
1512 currentDma->nextCount = currentDma->count;
1513 GBAMemoryScheduleDMA(gba, dma, currentDma);
1514 }
1515 // If the DMA has already occurred, this value might have changed since the function started
1516 return currentDma->reg;
1517};
1518
1519void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1520 struct ARMCore* cpu = gba->cpu;
1521 switch (GBADMARegisterGetTiming(info->reg)) {
1522 case DMA_TIMING_NOW:
1523 info->nextEvent = cpu->cycles + 2;
1524 GBAMemoryUpdateDMAs(gba, -1);
1525 break;
1526 case DMA_TIMING_HBLANK:
1527 // Handled implicitly
1528 info->nextEvent = INT_MAX;
1529 break;
1530 case DMA_TIMING_VBLANK:
1531 // Handled implicitly
1532 info->nextEvent = INT_MAX;
1533 break;
1534 case DMA_TIMING_CUSTOM:
1535 info->nextEvent = INT_MAX;
1536 switch (number) {
1537 case 0:
1538 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1539 break;
1540 case 1:
1541 case 2:
1542 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1543 break;
1544 case 3:
1545 // GBAVideoScheduleVCaptureDma(dma, info);
1546 break;
1547 }
1548 }
1549}
1550
1551void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1552 struct GBAMemory* memory = &gba->memory;
1553 struct GBADMA* dma;
1554 int i;
1555 for (i = 0; i < 4; ++i) {
1556 dma = &memory->dma[i];
1557 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1558 dma->nextEvent = cycles;
1559 }
1560 }
1561 GBAMemoryUpdateDMAs(gba, 0);
1562}
1563
1564void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1565 struct GBAMemory* memory = &gba->memory;
1566 struct GBADMA* dma;
1567 int i;
1568 for (i = 0; i < 4; ++i) {
1569 dma = &memory->dma[i];
1570 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1571 dma->nextEvent = cycles;
1572 }
1573 }
1574 GBAMemoryUpdateDMAs(gba, 0);
1575}
1576
1577int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1578 struct GBAMemory* memory = &gba->memory;
1579 if (memory->nextDMA == INT_MAX) {
1580 return INT_MAX;
1581 }
1582 memory->nextDMA -= cycles;
1583 memory->eventDiff += cycles;
1584 while (memory->nextDMA <= 0) {
1585 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1586 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1587 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1588 memory->eventDiff = 0;
1589 }
1590 return memory->nextDMA;
1591}
1592
1593void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1594 int i;
1595 struct GBAMemory* memory = &gba->memory;
1596 struct ARMCore* cpu = gba->cpu;
1597 memory->activeDMA = -1;
1598 memory->nextDMA = INT_MAX;
1599 for (i = 3; i >= 0; --i) {
1600 struct GBADMA* dma = &memory->dma[i];
1601 if (dma->nextEvent != INT_MAX) {
1602 dma->nextEvent -= cycles;
1603 if (GBADMARegisterIsEnable(dma->reg)) {
1604 memory->activeDMA = i;
1605 memory->nextDMA = dma->nextEvent;
1606 }
1607 }
1608 }
1609 if (memory->nextDMA < cpu->nextEvent) {
1610 cpu->nextEvent = memory->nextDMA;
1611 }
1612}
1613
1614void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1615 struct GBAMemory* memory = &gba->memory;
1616 struct ARMCore* cpu = gba->cpu;
1617 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1618 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1619 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1620 int32_t wordsRemaining = info->nextCount;
1621 uint32_t source = info->nextSource;
1622 uint32_t dest = info->nextDest;
1623 uint32_t sourceRegion = source >> BASE_OFFSET;
1624 uint32_t destRegion = dest >> BASE_OFFSET;
1625 int32_t cycles = 2;
1626
1627 if (source == info->source && dest == info->dest && wordsRemaining == info->count) {
1628 if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
1629 cycles += 2;
1630 }
1631 if (width == 4) {
1632 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1633 source &= 0xFFFFFFFC;
1634 dest &= 0xFFFFFFFC;
1635 } else {
1636 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1637 }
1638 } else {
1639 if (width == 4) {
1640 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1641 } else {
1642 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1643 }
1644 }
1645
1646 gba->performingDMA = 1 | (number << 1);
1647 int32_t word;
1648 if (width == 4) {
1649 word = cpu->memory.load32(cpu, source, 0);
1650 gba->bus = word;
1651 cpu->memory.store32(cpu, dest, word, 0);
1652 source += sourceOffset;
1653 dest += destOffset;
1654 --wordsRemaining;
1655 } else {
1656 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1657 word = GBASavedataReadEEPROM(&memory->savedata);
1658 gba->bus = word | (word << 16);
1659 cpu->memory.store16(cpu, dest, word, 0);
1660 source += sourceOffset;
1661 dest += destOffset;
1662 --wordsRemaining;
1663 } else if (destRegion == REGION_CART2_EX) {
1664 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1665 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1666 GBASavedataInitEEPROM(&memory->savedata);
1667 }
1668 word = cpu->memory.load16(cpu, source, 0);
1669 gba->bus = word | (word << 16);
1670 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1671 source += sourceOffset;
1672 dest += destOffset;
1673 --wordsRemaining;
1674 } else {
1675 word = cpu->memory.load16(cpu, source, 0);
1676 gba->bus = word | (word << 16);
1677 cpu->memory.store16(cpu, dest, word, 0);
1678 source += sourceOffset;
1679 dest += destOffset;
1680 --wordsRemaining;
1681 }
1682 }
1683 gba->performingDMA = 0;
1684
1685 if (!wordsRemaining) {
1686 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1687 info->reg = GBADMARegisterClearEnable(info->reg);
1688 info->nextEvent = INT_MAX;
1689
1690 // Clear the enable bit in memory
1691 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1692 } else {
1693 info->nextCount = info->count;
1694 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1695 info->nextDest = info->dest;
1696 }
1697 GBAMemoryScheduleDMA(gba, number, info);
1698 }
1699 if (GBADMARegisterIsDoIRQ(info->reg)) {
1700 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1701 }
1702 } else {
1703 info->nextDest = dest;
1704 info->nextCount = wordsRemaining;
1705 }
1706 info->nextSource = source;
1707
1708 if (info->nextEvent != INT_MAX) {
1709 info->nextEvent += cycles;
1710 }
1711 cpu->cycles += cycles;
1712}
1713
1714int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1715 struct GBA* gba = (struct GBA*) cpu->master;
1716 struct GBAMemory* memory = &gba->memory;
1717
1718 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1719 // The wait is the stall
1720 return wait;
1721 }
1722
1723 int32_t s = cpu->memory.activeSeqCycles16 + 1;
1724 int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
1725
1726 // Figure out how many sequential loads we can jam in
1727 int32_t stall = s;
1728 int32_t loads = 1;
1729 int32_t previousLoads = 0;
1730
1731 // Don't prefetch too much if we're overlapping with a previous prefetch
1732 uint32_t dist = (memory->lastPrefetchedPc - cpu->gprs[ARM_PC]) >> 1;
1733 if (dist < memory->lastPrefetchedLoads) {
1734 previousLoads = dist;
1735 }
1736 while (stall < wait) {
1737 stall += s;
1738 ++loads;
1739 }
1740 if (loads + previousLoads > 8) {
1741 int diff = (loads + previousLoads) - 8;
1742 loads -= diff;
1743 stall -= s * diff;
1744 } else if (stall > wait && loads == 1) {
1745 // We might need to stall a bit extra if we haven't finished the first S cycle
1746 wait = stall;
1747 }
1748 // This instruction used to have an N, convert it to an S.
1749 wait -= n2s;
1750
1751 // TODO: Invalidate prefetch on branch
1752 memory->lastPrefetchedLoads = loads;
1753 memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * loads;
1754
1755 // The next |loads|S waitstates disappear entirely, so long as they're all in a row
1756 cpu->cycles -= (s - 1) * loads;
1757 return wait;
1758}
1759
1760void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1761 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1762 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1763}
1764
1765void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1766 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1767 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1768}
1769
1770void _pristineCow(struct GBA* gba) {
1771 if (gba->memory.rom != gba->pristineRom) {
1772 return;
1773 }
1774 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1775 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1776 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1777}