src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
41
42static void DS9Reset(struct ARMCore* cpu);
43static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44
45static void DSProcessEvents(struct ARMCore* cpu);
46static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
47static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
48static void DSBreakpoint(struct ARMCore* cpu, int immediate);
49
50void DSCreate(struct DS* ds) {
51 ds->d.id = DS_COMPONENT_MAGIC;
52 ds->d.init = DSInit;
53 ds->d.deinit = NULL;
54 ds->arm7 = NULL;
55 ds->arm9 = NULL;
56}
57
58static void DSInit(void* cpu, struct mCPUComponent* component) {
59 struct DS* ds = (struct DS*) component;
60 struct ARMCore* core = cpu;
61 if (!ds->arm7) {
62 // The ARM7 must get initialized first
63 ds->arm7 = core;
64 ds->debugger = 0;
65 ds->sync = 0;
66 return;
67 }
68 ds->arm9 = cpu;
69
70 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
71
72 DS7InterruptHandlerInit(&ds->arm7->irqh);
73 DS9InterruptHandlerInit(&ds->arm9->irqh);
74 DSMemoryInit(ds);
75
76 ds->video.p = ds;
77
78 ds->springIRQ7 = 0;
79 ds->springIRQ9 = 0;
80 ds->keySource = NULL;
81 ds->rtcSource = NULL;
82 ds->rumble = NULL;
83
84 ds->romVf = NULL;
85
86 ds->keyCallback = NULL;
87}
88
89void DSUnloadROM(struct DS* ds) {
90 if (ds->romVf) {
91 ds->romVf->close(ds->romVf);
92 ds->romVf = NULL;
93 }
94}
95
96void DSDestroy(struct DS* ds) {
97 DSUnloadROM(ds);
98 DSMemoryDeinit(ds);
99}
100
101void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
102 irqh->reset = DS7Reset;
103 irqh->processEvents = DSProcessEvents;
104 irqh->swi16 = NULL;
105 irqh->swi32 = NULL;
106 irqh->hitIllegal = DSIllegal;
107 irqh->readCPSR = NULL;
108 irqh->hitStub = DSHitStub;
109 irqh->bkpt16 = DSBreakpoint;
110 irqh->bkpt32 = DSBreakpoint;
111}
112
113void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
114 irqh->reset = DS9Reset;
115 irqh->processEvents = DSProcessEvents;
116 irqh->swi16 = NULL;
117 irqh->swi32 = NULL;
118 irqh->hitIllegal = DSIllegal;
119 irqh->readCPSR = NULL;
120 irqh->hitStub = DSHitStub;
121 irqh->bkpt16 = DSBreakpoint;
122 irqh->bkpt32 = DSBreakpoint;
123}
124
125void DS7Reset(struct ARMCore* cpu) {
126 ARMSetPrivilegeMode(cpu, MODE_IRQ);
127 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
128 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
129 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
130 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
131 cpu->gprs[ARM_SP] = DS7_SP_BASE;
132
133 struct DS* ds = (struct DS*) cpu->master;
134 DSMemoryReset(ds);
135
136 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
137 if (header) {
138 // TODO: Error check
139 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
140 uint32_t base = header->arm7Base - DS_BASE_RAM;
141 uint32_t* basePointer = &ds->memory.ram[base >> 2];
142 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
143 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
144 }
145 cpu->gprs[12] = header->arm7Entry;
146 cpu->gprs[ARM_LR] = header->arm7Entry;
147 cpu->gprs[ARM_PC] = header->arm7Entry;
148 int currentCycles = 0;
149 ARM_WRITE_PC;
150
151 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
152 }
153}
154
155void DS9Reset(struct ARMCore* cpu) {
156 ARMSetPrivilegeMode(cpu, MODE_IRQ);
157 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
158 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
159 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
160 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
161 cpu->gprs[ARM_SP] = DS9_SP_BASE;
162
163 struct DS* ds = (struct DS*) cpu->master;
164 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
165 if (header) {
166 // TODO: Error check
167 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
168 uint32_t base = header->arm9Base - DS_BASE_RAM;
169 uint32_t* basePointer = &ds->memory.ram[base >> 2];
170 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
171 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
172 }
173 cpu->gprs[12] = header->arm9Entry;
174 cpu->gprs[ARM_LR] = header->arm9Entry;
175 cpu->gprs[ARM_PC] = header->arm9Entry;
176 int currentCycles = 0;
177 ARM_WRITE_PC;
178
179 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
180 }
181}
182
183static void DSProcessEvents(struct ARMCore* cpu) {
184 struct DS* ds = (struct DS*) cpu->master;
185
186 if (ds->springIRQ7) {
187 ARMRaiseIRQ(cpu);
188 ds->springIRQ7 = 0;
189 }
190
191 do {
192 int32_t cycles = cpu->nextEvent;
193 int32_t nextEvent = INT_MAX;
194#ifndef NDEBUG
195 if (cycles < 0) {
196 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
197 }
198#endif
199
200 cpu->cycles -= cycles;
201 cpu->nextEvent = nextEvent;
202
203 if (cpu->halted) {
204 cpu->cycles = cpu->nextEvent;
205 }
206 } while (cpu->cycles >= cpu->nextEvent);
207}
208
209void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
210 ds->debugger = (struct ARMDebugger*) debugger->platform;
211 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
212 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
213 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
214 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
215}
216
217
218void DSDetachDebugger(struct DS* ds) {
219 ds->debugger = NULL;
220 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
221 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
222 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
223 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
224}
225
226bool DSLoadROM(struct DS* ds, struct VFile* vf) {
227 DSUnloadROM(ds);
228 ds->romVf = vf;
229 // TODO: error check
230 return true;
231}
232
233bool DSIsROM(struct VFile* vf) {
234 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
235 return false;
236 }
237 uint8_t signature[sizeof(DS_ROM_MAGIC)];
238 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
239 return false;
240 }
241 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
242}
243
244bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
245 size_t size = vf->size(vf);
246 void* data = NULL;
247 uint32_t crc;
248 if (size == DS7_SIZE_BIOS) {
249 data = vf->map(vf, size, MAP_READ);
250 } else if (size == 0x1000) {
251 data = vf->map(vf, size, MAP_READ);
252 }
253 if (!data) {
254 return false;
255 }
256 crc = doCrc32(data, size);
257 if (crc == DS7_BIOS_CHECKSUM) {
258 ds->bios7Vf = vf;
259 ds->memory.bios7 = data;
260 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
261 } else if (crc == DS9_BIOS_CHECKSUM) {
262 ds->bios9Vf = vf;
263 ds->memory.bios9 = data;
264 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
265 } else {
266 mLOG(DS, WARN, "BIOS checksum incorrect");
267 vf->unmap(vf, data, size);
268 return false;
269 }
270 return true;
271}
272
273void DSGetGameCode(struct DS* ds, char* out) {
274 memset(out, 0, 8);
275 if (!ds->romVf) {
276 return;
277 }
278
279 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
280 memcpy(out, "NTR-", 4);
281 memcpy(&out[4], &cart->id, 4);
282 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
283}
284
285void DSGetGameTitle(struct DS* ds, char* out) {
286 memset(out, 0, 12);
287 if (!ds->romVf) {
288 return;
289 }
290
291 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
292 memcpy(out, &cart->title, 4);
293 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
294}
295
296void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
297 struct DS* ds = (struct DS*) cpu->master;
298 if (ds->debugger) {
299 struct mDebuggerEntryInfo info = {
300 .address = _ARMPCAddress(cpu),
301 .opcode = opcode
302 };
303 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
304 }
305 // TODO: More sensible category?
306 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
307}
308
309void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
310 struct DS* ds = (struct DS*) cpu->master;
311 if (ds->debugger) {
312 struct mDebuggerEntryInfo info = {
313 .address = _ARMPCAddress(cpu),
314 .opcode = opcode
315 };
316 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
317 } else {
318 ARMRaiseUndefined(cpu);
319 }
320}
321
322void DSBreakpoint(struct ARMCore* cpu, int immediate) {
323 struct DS* ds = (struct DS*) cpu->master;
324 if (immediate >= CPU_COMPONENT_MAX) {
325 return;
326 }
327 switch (immediate) {
328 case CPU_COMPONENT_DEBUGGER:
329 if (ds->debugger) {
330 struct mDebuggerEntryInfo info = {
331 .address = _ARMPCAddress(cpu)
332 };
333 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
334 }
335 break;
336 default:
337 break;
338 }
339}