src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_NEUTRAL_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D);
22
23#define APPLY(F, ...) F(__VA_ARGS__)
24
25#define COUNT_1(EMITTER, PREFIX, ...) \
26 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
27 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
28
29#define COUNT_2(EMITTER, PREFIX, ...) \
30 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
31 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
32 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
33
34#define COUNT_3(EMITTER, PREFIX, ...) \
35 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
36 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
37 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
38 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
39 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
40
41#define COUNT_4(EMITTER, PREFIX, ...) \
42 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
43 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
44 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
45 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
46 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
47 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
48 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
49 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
50 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
51
52#define COUNT_5(EMITTER, PREFIX, ...) \
53 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
54 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
55 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
56 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
57 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
58 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
59 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
60 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
61 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
62 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
63 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
64 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
65 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
66 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
67 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
68 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
69 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
70
71#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
72 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
73 BODY; \
74 }
75
76#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
77 DEFINE_INSTRUCTION_THUMB(NAME, \
78 int immediate = IMMEDIATE; \
79 int rd = opcode & 0x0007; \
80 int rm = (opcode >> 3) & 0x0007; \
81 BODY;)
82
83#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
84 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
85
86DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
87 if (!immediate) { \
88 cpu->gprs[rd] = cpu->gprs[rm]; \
89 } else { \
90 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
91 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
92 } \
93 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
94
95DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
96DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
97
98DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
99DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
100DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, ARM_STUB)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
103DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, ARM_STUB)
104
105#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
106 DEFINE_INSTRUCTION_THUMB(NAME, \
107 int rm = RM; \
108 BODY;)
109
110#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
111 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
112
113DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
114DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
115
116#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
117 DEFINE_INSTRUCTION_THUMB(NAME, \
118 int immediate = IMMEDIATE; \
119 BODY;)
120
121#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
122 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
123
124DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, ARM_STUB)
125DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
126
127#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
128 DEFINE_INSTRUCTION_THUMB(NAME, \
129 int rd = RD; \
130 int immediate = opcode & 0x00FF; \
131 BODY;)
132
133#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
134 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
135
136DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, ARM_STUB)
137DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
138DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
139DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
140
141#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
142 DEFINE_INSTRUCTION_THUMB(NAME, \
143 int rd = opcode & 0x0007; \
144 int rn = (opcode >> 3) & 0x0007; \
145 BODY;)
146
147DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
148DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
149DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
150DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
151DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
152DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
153DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
154DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
155DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
156DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
157DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
158DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
159DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
160DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
161DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
162DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
163
164#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
165 DEFINE_INSTRUCTION_THUMB(NAME, \
166 int rd = opcode & 0x0007 | H1; \
167 int rm = (opcode >> 3) & 0x0007 | H2; \
168 BODY;)
169
170#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
171 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
172 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
173 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
174 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
175
176DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
177DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
178DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
179
180#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
181 DEFINE_INSTRUCTION_THUMB(NAME, \
182 int rd = RD; \
183 int immediate = (opcode & 0x00FF) << 2; \
184 BODY;)
185
186#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
187 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
188
189DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, ARM_STUB)
190DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, ARM_STUB)
191DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, ARM_STUB)
192
193DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
194DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
195
196#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
197 DEFINE_INSTRUCTION_THUMB(NAME, \
198 int rm = RM; \
199 BODY;)
200
201#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
202 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
203
204DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
205DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
206DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
207DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
208DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
209DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
210DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
211DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
212
213#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
214 DEFINE_INSTRUCTION_THUMB(NAME, \
215 int rn = (opcode >> 8) & 0x000F; \
216 int rs = RS; \
217 int32_t address = ADDRESS; \
218 int m; \
219 int i; \
220 PRE_BODY; \
221 for LOOP { \
222 if (rs & m) { \
223 BODY; \
224 address OP 4; \
225 } \
226 } \
227 POST_BODY; \
228 WRITEBACK;)
229
230#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
231 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
232
233DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
234 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
235 if (!((1 << rn) & rs)) { \
236 cpu->gprs[rn] = address; \
237 })
238
239DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
240 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
241 cpu->gprs[rn] = address)
242
243#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
244 DEFINE_INSTRUCTION_THUMB(B ## COND, \
245 if (ARM_COND_ ## COND) { \
246 ARM_STUB; \
247 })
248
249DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
250DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
251DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
252DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
253DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
254DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
255DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
256DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
257DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
258DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
259DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
260DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
261DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
262DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
263
264DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
265DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
266
267DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
268 opcode & 0x00FF, \
269 cpu->gprs[ARM_SP], \
270 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
271 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
272 +=, \
273 , , \
274 cpu->gprs[ARM_SP] = address)
275
276DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
277 opcode & 0x00FF, \
278 cpu->gprs[ARM_SP], \
279 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
280 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
281 +=, \
282 , \
283 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
284 address += 4;, \
285 cpu->gprs[ARM_SP] = address)
286
287DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
288 opcode & 0x00FF, \
289 cpu->gprs[ARM_SP] - 4, \
290 (m = 0x80, i = 7; m; m >>= 1, --i), \
291 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
292 -=, \
293 , , \
294 cpu->gprs[ARM_SP] = address + 4)
295
296DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
297 opcode & 0x00FF, \
298 cpu->gprs[ARM_SP] - 4, \
299 (m = 0x80, i = 7; m; m >>= 1, --i), \
300 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
301 -=, \
302 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
303 address -= 4;, \
304 , \
305 cpu->gprs[ARM_SP] = address + 4)
306
307DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
308DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
309DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
310DEFINE_INSTRUCTION_THUMB(BL1, \
311 int16_t immediate = (opcode & 0x07FF) << 7; \
312 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 4);)
313
314DEFINE_INSTRUCTION_THUMB(BL2, \
315 uint16_t immediate = (opcode & 0x07FF) << 1; \
316 uint32_t pc = cpu->gprs[ARM_PC]; \
317 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
318 cpu->gprs[ARM_LR] = pc - 1; \
319 THUMB_WRITE_PC;)
320
321DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
322DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
323
324#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
325 EMITTER ## NAME
326
327#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
328 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
329 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
330 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
331 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
332
333#define DUMMY(X, ...) X,
334#define DUMMY_4(...) \
335 DUMMY(__VA_ARGS__) \
336 DUMMY(__VA_ARGS__) \
337 DUMMY(__VA_ARGS__) \
338 DUMMY(__VA_ARGS__)
339
340#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
341 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
342 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
343 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
344 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
345 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
346 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
347 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
348 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
349 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
350 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
351 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
352 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
353 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
354 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
355 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
356 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
357 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
358 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
359 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
360 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
361 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
362 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
363 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
364 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
365 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
366 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
367 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
368 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
369 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
370 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
371 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
372 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
373 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
374 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
375 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
376 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
377 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
378 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
379 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
380 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
381 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
382 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
383 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
384 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
385 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
386 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
387 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
388 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
389 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
390 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
391 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
392 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
393 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
394 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
395 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
396 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
397 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
398 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
399 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
400 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
401 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
402 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
403 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
404 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
405 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
406 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
407 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
408 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
409 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
410 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
411 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
412 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
413 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
414 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
415 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
416 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
417 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
418 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
419 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
420 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
421 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
422 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
423 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
424 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
425 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
426 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
427 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
428 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
429 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
430 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
431 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
432
433static const ThumbInstruction _thumbTable[0x400] = {
434 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
435};