src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18#define SLICE_CYCLES 2048
19
20mLOG_DEFINE_CATEGORY(DS, "DS");
21
22const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
23const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
24const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
25
26static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
27static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
28
29enum {
30 DS7_SP_BASE = 0x380FD80,
31 DS7_SP_BASE_IRQ = 0x380FF80,
32 DS7_SP_BASE_SVC = 0x380FFC0,
33
34 DS9_SP_BASE = 0x3002F7C,
35 DS9_SP_BASE_IRQ = 0x3003F80,
36 DS9_SP_BASE_SVC = 0x3003FC0,
37};
38
39static void DSInit(void* cpu, struct mCPUComponent* component);
40
41static void DS7Reset(struct ARMCore* cpu);
42static void DS7TestIRQ(struct ARMCore* cpu);
43static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44static void DS7ProcessEvents(struct ARMCore* cpu);
45
46static void DS9Reset(struct ARMCore* cpu);
47static void DS9TestIRQ(struct ARMCore* cpu);
48static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
49static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
50static void DS9ProcessEvents(struct ARMCore* cpu);
51
52static void DSProcessEvents(struct DS* ds, struct mTiming* timing);
53static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
54static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
55static void DSBreakpoint(struct ARMCore* cpu, int immediate);
56
57static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
58 UNUSED(cyclesLate);
59 struct DS* ds = context;
60 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
61 if (ds->activeCpu == ds->arm9) {
62 ds->activeCpu = ds->arm7;
63 ds->cycleDrift += cycles;
64 cycles = ds->cycleDrift >> 1;
65 timing = &ds->timing7;
66 } else {
67 ds->activeCpu = ds->arm9;
68 ds->cycleDrift -= cycles << 1;
69 cycles = ds->cycleDrift + SLICE_CYCLES;
70 timing = &ds->timing9;
71 }
72 mTimingSchedule(timing, &ds->slice, cycles);
73 ds->sliceStart = mTimingCurrentTime(timing);
74}
75
76void DSCreate(struct DS* ds) {
77 ds->d.id = DS_COMPONENT_MAGIC;
78 ds->d.init = DSInit;
79 ds->d.deinit = NULL;
80 ds->arm7 = NULL;
81 ds->arm9 = NULL;
82}
83
84static void DSInit(void* cpu, struct mCPUComponent* component) {
85 struct DS* ds = (struct DS*) component;
86 struct ARMCore* core = cpu;
87 if (!ds->arm7) {
88 // The ARM7 must get initialized first
89 ds->arm7 = core;
90 ds->debugger = 0;
91 ds->sync = 0;
92 return;
93 }
94 ds->arm9 = cpu;
95 ds->activeCpu = NULL;
96
97 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
98
99 ds->slice.name = "DS CPU Time Slicing";
100 ds->slice.callback = _slice;
101 ds->slice.context = ds;
102 ds->slice.priority = UINT_MAX;
103
104 DS7InterruptHandlerInit(&ds->arm7->irqh);
105 DS9InterruptHandlerInit(&ds->arm9->irqh);
106 DSMemoryInit(ds);
107
108 ds->video.p = ds;
109
110 ds->springIRQ7 = 0;
111 ds->springIRQ9 = 0;
112 DSTimerInit(ds);
113 ds->keySource = NULL;
114 ds->rtcSource = NULL;
115 ds->rumble = NULL;
116
117 ds->romVf = NULL;
118
119 ds->keyCallback = NULL;
120
121 mTimingInit(&ds->timing7, &ds->arm7->cycles, &ds->arm7->nextEvent);
122 mTimingInit(&ds->timing9, &ds->arm9->cycles, &ds->arm9->nextEvent);
123}
124
125void DSUnloadROM(struct DS* ds) {
126 if (ds->romVf) {
127 ds->romVf->close(ds->romVf);
128 ds->romVf = NULL;
129 }
130}
131
132void DSDestroy(struct DS* ds) {
133 DSUnloadROM(ds);
134 DSMemoryDeinit(ds);
135 mTimingDeinit(&ds->timing7);
136 mTimingDeinit(&ds->timing9);
137}
138
139void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
140 irqh->reset = DS7Reset;
141 irqh->processEvents = DS7ProcessEvents;
142 irqh->swi16 = DS7Swi16;
143 irqh->swi32 = DS7Swi32;
144 irqh->hitIllegal = DSIllegal;
145 irqh->readCPSR = DS7TestIRQ;
146 irqh->writeCP15 = NULL;
147 irqh->hitStub = DSHitStub;
148 irqh->bkpt16 = DSBreakpoint;
149 irqh->bkpt32 = DSBreakpoint;
150}
151
152void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
153 irqh->reset = DS9Reset;
154 irqh->processEvents = DS9ProcessEvents;
155 irqh->swi16 = NULL;
156 irqh->swi32 = NULL;
157 irqh->hitIllegal = DSIllegal;
158 irqh->readCPSR = DS9TestIRQ;
159 irqh->writeCP15 = DS9WriteCP15;
160 irqh->hitStub = DSHitStub;
161 irqh->bkpt16 = DSBreakpoint;
162 irqh->bkpt32 = DSBreakpoint;
163}
164
165void DS7Reset(struct ARMCore* cpu) {
166 ARMSetPrivilegeMode(cpu, MODE_IRQ);
167 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
168 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
169 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
170 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
171 cpu->gprs[ARM_SP] = DS7_SP_BASE;
172
173 struct DS* ds = (struct DS*) cpu->master;
174 mTimingClear(&ds->timing7);
175 DSMemoryReset(ds);
176 DS7IOInit(ds);
177
178 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
179 if (header) {
180 // TODO: Error check
181 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
182 uint32_t base = header->arm7Base - DS_BASE_RAM;
183 uint32_t* basePointer = &ds->memory.ram[base >> 2];
184 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
185 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
186 }
187 cpu->gprs[12] = header->arm7Entry;
188 cpu->gprs[ARM_LR] = header->arm7Entry;
189 cpu->gprs[ARM_PC] = header->arm7Entry;
190 int currentCycles = 0;
191 ARM_WRITE_PC;
192
193 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
194 }
195}
196
197void DS9Reset(struct ARMCore* cpu) {
198 ARMSetPrivilegeMode(cpu, MODE_IRQ);
199 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
200 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
201 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
202 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
203 cpu->gprs[ARM_SP] = DS9_SP_BASE;
204
205 struct DS* ds = (struct DS*) cpu->master;
206 mTimingClear(&ds->timing9);
207 DS9IOInit(ds);
208
209 ds->activeCpu = cpu;
210 mTimingSchedule(&ds->timing9, &ds->slice, SLICE_CYCLES);
211 ds->cycleDrift = 0;
212 ds->sliceStart = mTimingCurrentTime(&ds->timing9);
213
214 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
215 if (header) {
216 // TODO: Error check
217 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
218 uint32_t base = header->arm9Base - DS_BASE_RAM;
219 uint32_t* basePointer = &ds->memory.ram[base >> 2];
220 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
221 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
222 }
223 cpu->gprs[12] = header->arm9Entry;
224 cpu->gprs[ARM_LR] = header->arm9Entry;
225 cpu->gprs[ARM_PC] = header->arm9Entry;
226 int currentCycles = 0;
227 ARM_WRITE_PC;
228
229 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
230 }
231}
232
233static void DS7ProcessEvents(struct ARMCore* cpu) {
234 struct DS* ds = (struct DS*) cpu->master;
235
236 if (ds->springIRQ7 && !cpu->cpsr.i) {
237 ARMRaiseIRQ(cpu);
238 ds->springIRQ7 = 0;
239 }
240 DSProcessEvents(ds, &ds->timing7);
241}
242
243static void DS9ProcessEvents(struct ARMCore* cpu) {
244 struct DS* ds = (struct DS*) cpu->master;
245
246 if (ds->springIRQ9 && !cpu->cpsr.i) {
247 ARMRaiseIRQ(cpu);
248 ds->springIRQ9 = 0;
249 }
250 DSProcessEvents(ds, &ds->timing9);
251}
252
253static void DSProcessEvents(struct DS* ds, struct mTiming* timing) {
254 struct ARMCore* cpu = ds->activeCpu;
255 int32_t nextEvent = cpu->nextEvent;
256 while (cpu->cycles >= nextEvent) {
257 int32_t cycles = cpu->cycles;
258
259 cpu->cycles = 0;
260 cpu->nextEvent = INT_MAX;
261
262#ifndef NDEBUG
263 if (cycles < 0) {
264 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
265 }
266#endif
267 nextEvent = cycles;
268 do {
269 nextEvent = mTimingTick(timing, nextEvent);
270 } while (ds->cpuBlocked);
271
272 cpu->nextEvent = nextEvent;
273
274 if (ds->earlyExit) {
275 ds->earlyExit = false;
276 break;
277 }
278 if (cpu->halted) {
279 cpu->cycles = nextEvent;
280 }
281#ifndef NDEBUG
282 else if (nextEvent < 0) {
283 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
284 }
285#endif
286 }
287}
288
289void DSRunLoop(struct DS* ds) {
290 if (ds->activeCpu == ds->arm9) {
291 ARMv5RunLoop(ds->arm9);
292 } else {
293 ARMv4RunLoop(ds->arm7);
294 }
295}
296
297void DS7Step(struct DS* ds) {
298 while (ds->activeCpu == ds->arm9) {
299 ARMv5RunLoop(ds->arm9);
300 }
301 ARMv4Run(ds->arm7);
302}
303
304void DS9Step(struct DS* ds) {
305 while (ds->activeCpu == ds->arm7) {
306 ARMv4RunLoop(ds->arm7);
307 }
308 ARMv5Run(ds->arm9);
309}
310
311void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
312 ds->debugger = (struct ARMDebugger*) debugger->platform;
313 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
314 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
315 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
316 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
317}
318
319void DSDetachDebugger(struct DS* ds) {
320 ds->debugger = NULL;
321 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
322 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
323 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
324 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
325}
326
327bool DSLoadROM(struct DS* ds, struct VFile* vf) {
328 DSUnloadROM(ds);
329 ds->romVf = vf;
330 // TODO: error check
331 return true;
332}
333
334bool DSIsROM(struct VFile* vf) {
335 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
336 return false;
337 }
338 uint8_t signature[sizeof(DS_ROM_MAGIC)];
339 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
340 return false;
341 }
342 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
343}
344
345bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
346 size_t size = vf->size(vf);
347 void* data = NULL;
348 uint32_t crc;
349 if (size == DS7_SIZE_BIOS) {
350 data = vf->map(vf, size, MAP_READ);
351 } else if (size == 0x1000) {
352 data = vf->map(vf, size, MAP_READ);
353 }
354 if (!data) {
355 return false;
356 }
357 crc = doCrc32(data, size);
358 if (crc == DS7_BIOS_CHECKSUM) {
359 ds->bios7Vf = vf;
360 ds->memory.bios7 = data;
361 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
362 } else if (crc == DS9_BIOS_CHECKSUM) {
363 ds->bios9Vf = vf;
364 ds->memory.bios9 = data;
365 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
366 } else {
367 mLOG(DS, WARN, "BIOS checksum incorrect");
368 vf->unmap(vf, data, size);
369 return false;
370 }
371 return true;
372}
373
374void DSGetGameCode(struct DS* ds, char* out) {
375 memset(out, 0, 8);
376 if (!ds->romVf) {
377 return;
378 }
379
380 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
381 memcpy(out, "NTR-", 4);
382 memcpy(&out[4], &cart->id, 4);
383 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
384}
385
386void DSGetGameTitle(struct DS* ds, char* out) {
387 memset(out, 0, 12);
388 if (!ds->romVf) {
389 return;
390 }
391
392 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
393 memcpy(out, &cart->title, 4);
394 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
395}
396
397void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
398 struct DS* ds = (struct DS*) cpu->master;
399 if (ds->debugger) {
400 struct mDebuggerEntryInfo info = {
401 .address = _ARMPCAddress(cpu),
402 .opcode = opcode
403 };
404 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
405 }
406 // TODO: More sensible category?
407 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
408}
409
410void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
411 struct DS* ds = (struct DS*) cpu->master;
412 if (ds->debugger) {
413 struct mDebuggerEntryInfo info = {
414 .address = _ARMPCAddress(cpu),
415 .opcode = opcode
416 };
417 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
418 } else {
419 ARMRaiseUndefined(cpu);
420 }
421}
422
423void DSBreakpoint(struct ARMCore* cpu, int immediate) {
424 struct DS* ds = (struct DS*) cpu->master;
425 if (immediate >= CPU_COMPONENT_MAX) {
426 return;
427 }
428 switch (immediate) {
429 case CPU_COMPONENT_DEBUGGER:
430 if (ds->debugger) {
431 struct mDebuggerEntryInfo info = {
432 .address = _ARMPCAddress(cpu)
433 };
434 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
435 }
436 break;
437 default:
438 break;
439 }
440}
441
442void DS7TestIRQ(struct ARMCore* cpu) {
443 struct DS* ds = (struct DS*) cpu->master;
444 if (0) {
445 ds->springIRQ7 = 1;
446 cpu->nextEvent = cpu->cycles;
447 }
448}
449
450void DS9TestIRQ(struct ARMCore* cpu) {
451 struct DS* ds = (struct DS*) cpu->master;
452 if (0) {
453 ds->springIRQ9 = 1;
454 cpu->nextEvent = cpu->cycles;
455 }
456}
457
458static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
459 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
460}
461
462static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
463 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
464 switch (opcode2) {
465 case 0:
466 cpu->cp15.r2.d = value;
467 break;
468 case 1:
469 cpu->cp15.r2.i = value;
470 break;
471 default:
472 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
473 break;
474 }
475}
476
477static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
478 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
479 switch (opcode2) {
480 case 0:
481 cpu->cp15.r3.d = value;
482 break;
483 default:
484 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
485 break;
486 }
487}
488
489static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
490 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
491}
492
493static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
494 cpu->cp15.r6.region[crm] = value;
495 uint32_t base = ARMProtectionGetBase(value) << 12;
496 uint32_t size = 2 << ARMProtectionGetSize(value);
497 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
498}
499
500static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
501 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
502}
503
504static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
505 uint32_t base = ARMTCMControlGetBase(value) << 12;
506 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
507 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
508 switch (opcode2) {
509 case 0:
510 cpu->cp15.r9.d = value;
511 break;
512 case 1:
513 cpu->cp15.r9.i = value;
514 break;
515 default:
516 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
517 break;
518 }
519}
520
521void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
522 switch (crn) {
523 default:
524 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
525 break;
526 case 0:
527 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
528 ARMRaiseUndefined(cpu);
529 break;
530 case 1:
531 _writeSysControl(cpu, crm, opcode2, value);
532 break;
533 case 2:
534 _writeCacheControl(cpu, crm, opcode2, value);
535 break;
536 case 3:
537 _writeWriteBufferControl(cpu, crm, opcode2, value);
538 break;
539 case 5:
540 _writeAccessControl(cpu, crm, opcode2, value);
541 break;
542 case 6:
543 _writeRegionConfiguration(cpu, crm, opcode2, value);
544 break;
545 case 7:
546 _writeCache(cpu, crm, opcode2, value);
547 break;
548 case 9:
549 _writeTCMControl(cpu, crm, opcode2, value);
550 break;
551 }
552}
553
554void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
555 if (io[DS7_REG_IME >> 1] && (value & io[DS7_REG_IF_LO >> 1] || (value >> 16) & io[DS7_REG_IF_HI >> 1])) {
556 ARMRaiseIRQ(cpu);
557 }
558}
559void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
560 if (value && (io[DS7_REG_IE_LO >> 1] & io[DS7_REG_IF_LO >> 1] || io[DS7_REG_IE_HI >> 1] & io[DS7_REG_IF_HI >> 1])) {
561 ARMRaiseIRQ(cpu);
562 }
563}
564
565void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
566 if (irq < 16) {
567 io[DS7_REG_IF_LO >> 1] |= 1 << irq;
568 } else {
569 io[DS7_REG_IF_HI >> 1] |= 1 << (irq - 16);
570 }
571 cpu->halted = 0;
572
573 if (!io[DS7_REG_IME >> 1]) {
574 return;
575 }
576 if (irq < 16 && (io[DS7_REG_IE_LO >> 1] & 1 << irq)) {
577 ARMRaiseIRQ(cpu);
578 } else if (io[DS7_REG_IE_HI >> 1] & 1 << (irq - 16)) {
579 ARMRaiseIRQ(cpu);
580 }
581}