src/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include "util/common.h"
10
11#include "core/core.h"
12#include "gb/gb.h"
13
14extern const uint32_t GB_SAVESTATE_MAGIC;
15extern const uint32_t GB_SAVESTATE_VERSION;
16
17mLOG_DECLARE_CATEGORY(GB_STATE);
18
19/* Savestate format:
20 * 0x00000 - 0x00003: Version Magic (0x01000001)
21 * 0x00004 - 0x00007: ROM CRC32
22 * 0x00008: Game Boy model
23 * 0x00009 - 0x0000F: Reserved (leave zero)
24 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
25 * 0x00020 - 0x00047: CPU state:
26 * | 0x00020: A register
27 * | 0x00021: F register
28 * | 0x00022: B register
29 * | 0x00023: C register
30 * | 0x00024: D register
31 * | 0x00025: E register
32 * | 0x00026: H register
33 * | 0x00027: L register
34 * | 0x00028 - 0z00029: SP register
35 * | 0x0002A - 0z0002B: PC register
36 * | 0x0002C - 0x0002F: Cycles since last event
37 * | 0x00030 - 0x00033: Cycles until next event
38 * | 0x00034 - 0x00035: Reserved (current instruction)
39 * | 0x00036 - 0x00037: Index address
40 * | 0x00038: Bus value
41 * | 0x00039: Execution state
42 * | 0x0003A - 0x0003B: IRQ vector
43 * | 0x0003C - 0x0003F: EI pending cycles
44 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
45 * | 0x00044 - 0x00047: Flags
46 * | bit 0: Is condition met?
47 * | bit 1: Is condition IRQ pending?
48 * | bit 2: Double speed
49 * | bits 3 - 31: Reserved
50 * 0x00048 - 0x0005B: Audio channel 1/framer state
51 * | 0x00048 - 0x0004B: Envelepe timing
52 * | bits 0 - 6: Remaining length
53 * | bits 7 - 9: Next step
54 * | bits 10 - 20: Shadow frequency register
55 * | bits 21 - 31: Reserved
56 * | 0x0004C - 0x0004F: Next frame
57 * | 0x00050 - 0x00057: Reserved
58 * | 0x00058 - 0x0005B: Next event
59 * 0x0005C - 0x0006B: Audio channel 2 state
60 * | 0x0005C - 0x0005F: Envelepe timing
61 * | bits 0 - 2: Remaining length
62 * | bits 3 - 5: Next step
63 * | bits 6 - 31: Reserved
64 * | 0x00060 - 0x00067: Reserved
65 * | 0x00068 - 0x0006B: Next event
66 * 0x0006C - 0x00093: Audio channel 3 state
67 * | 0x0006C - 0x0008B: Wave banks
68 * | 0x0008C - 0x0008D: Remaining length
69 * | 0x0008E - 0x0008F: Reserved
70 * | 0x00090 - 0x00093: Next event
71 * 0x00094 - 0x000A3: Audio channel 4 state
72 * | 0x00094 - 0x00097: Linear feedback shift register state
73 * | 0x00098 - 0x0009B: Envelepe timing
74 * | bits 0 - 2: Remaining length
75 * | bits 3 - 5: Next step
76 * | bits 6 - 31: Reserved
77 * | 0x00098 - 0x0009F: Reserved
78 * | 0x000A0 - 0x000A3: Next event
79 * 0x000A4 - 0x000B7: Audio miscellaneous state
80 * | TODO: Fix this, they're in big-endian order, but field is little-endian
81 * | 0x000A4: Channel 1 envelope state
82 * | bits 0 - 3: Current volume
83 * | bits 4 - 5: Is dead?
84 * | bit 6: Is high?
85 * | 0x000A5: Channel 2 envelope state
86 * | bits 0 - 3: Current volume
87 * | bits 4 - 5: Is dead?
88 * | bit 6: Is high?
89* | bits 7: Reserved
90 * | 0x000A6: Channel 4 envelope state
91 * | bits 0 - 3: Current volume
92 * | bits 4 - 5: Is dead?
93 * | bit 6: Is high?
94* | bits 7: Reserved
95 * | 0x000A7: Miscellaneous audio flags
96 * | bits 0 - 3: Current frame
97 * | bit 4: Is channel 1 sweep enabled?
98 * | bit 5: Has channel 1 sweep occurred?
99 * | bits 6 - 7: Reserved
100 * | 0x000A8 - 0x000AB: Next event
101 * | 0x000AC - 0x000AF: Event diff
102 * | 0x000B0 - 0x000B3: Next sample
103 * 0x000B4 - 0x000153: Video state
104 * | 0x000B4 - 0x000B5: Current x
105 * | 0x000B6 - 0x000B7: Current y (ly)
106 * | 0x000B8 - 0x000BB: Next event
107 * | 0x000BC - 0x000BF: Event diff
108 * | 0x000C0 - 0x000C3: Next mode
109 * | 0x000C4 - 0x000C7: Dot cycle counter
110 * | 0x000C8 - 0x000CB: Frame counter
111 * | 0x000CC: Current VRAM bank
112 * | 0x000CD: Palette flags
113 * | bit 0: BCP increment
114 * | bit 1: OCP increment
115 * | bits 2 - 7: Reserved
116 * | 0x000CE - 0x000CF: Reserved
117 * | 0x000D0 - 0x000D1: BCP index
118 * | 0x000D1 - 0x000D3: OCP index
119 * | 0x000D4 - 0x00153: Palette entries
120 * 0x00154 - 0x000167: Timer state
121 * | 0x00154 - 0x00157: Next event
122 * | 0x00158 - 0x0015B: Event diff
123 * | 0x0015C - 0x0015F: Next DIV
124 * | 0x00160 - 0x00163: Inernal DIV
125 * | 0x00164: TIMA period
126 * | 0x00165: Flags
127 * | bit 0: Is IRQ pending?
128 * | 0x00166 - 0x00167: Reserved
129 * 0x000168 - 0x000197: Memory state
130 * | 0x00168 - 0x00169: Current ROM bank
131 * | 0x0016A: Current WRAM bank
132 * | 0x0016B: Current SRAM bank
133 * | 0x0016C - 0x0016F: Next DMA
134 * | 0x00170 - 0x00171: Next DMA source
135 * | 0x00172 - 0x00173: Next DMA destination
136 * | 0x00174 - 0x00177: Next HDMA
137 * | 0x00178 - 0x00179: Next HDMA source
138 * | 0x0017A - 0x0017B: Next HDMA destination
139 * | 0x0017C - 0x0017D: HDMA remaining
140 * | 0x0017E: DMA remaining
141 * | 0x0017F - 0x00183: RTC registers
142 * | 0x00184 - 0x00193: MBC state (TODO)
143 * | 0x00194 - 0x00195: Flags
144 * | bit 0: SRAM accessable
145 * | bit 1: RTC accessible
146 * | bit 2: RTC latched
147 * | bit 3: IME
148 * | bit 4: Is HDMA active?
149 * | bits 5 - 7: Active RTC register
150 * | 0x00196 - 0x00197: Reserved (leave zero)
151 * 0x00198 - 0x0019F: Savestate creation time (usec since 1970)
152 * 0x001A0 - 0x0025F: Reserved (leave zero)
153 * 0x00260 - 0x002FF: OAM
154 * 0x00300 - 0x0037F: I/O memory
155 * 0x00380 - 0x003FE: HRAM
156 * 0x003FF: Interrupts enabled
157 * 0x00400 - 0x043FF: VRAM
158 * 0x04400 - 0x0C3FF: WRAM
159 * Total size: 0xC400 (50,176) bytes
160*/
161
162DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
163DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
164DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
165DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
166DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
167DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
168DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
169DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
170DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
171DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
172DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
173DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
174
175DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
176DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
177DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
178DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
179
180struct GBSerializedPSGState {
181 struct {
182 GBSerializedAudioEnvelope envelope;
183 int32_t nextFrame;
184 int32_t reserved[2];
185 int32_t nextEvent;
186 } ch1;
187 struct {
188 GBSerializedAudioEnvelope envelope;
189 int32_t reserved[2];
190 int32_t nextEvent;
191 } ch2;
192 struct {
193 uint32_t wavebanks[8];
194 int16_t length;
195 int16_t reserved;
196 int32_t nextEvent;
197 } ch3;
198 struct {
199 int32_t lfsr;
200 GBSerializedAudioEnvelope envelope;
201 int32_t reserved;
202 int32_t nextEvent;
203 } ch4;
204};
205
206DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
207DECL_BIT(GBSerializedCpuFlags, Condition, 0);
208DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
209DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
210
211DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
212DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
213
214DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
215DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
216DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
217
218DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
219DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
220DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
221
222DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
223DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
224DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
225DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
226DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
227DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
228DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
229
230#pragma pack(push, 1)
231struct GBSerializedState {
232 uint32_t versionMagic;
233 uint32_t romCrc32;
234 uint8_t model;
235 uint8_t reservedHeader[7];
236
237 char title[16];
238
239 struct {
240 uint8_t a;
241 uint8_t f;
242 uint8_t b;
243 uint8_t c;
244 uint8_t d;
245 uint8_t e;
246 uint8_t h;
247 uint8_t l;
248 uint16_t sp;
249 uint16_t pc;
250
251 int32_t cycles;
252 int32_t nextEvent;
253
254 uint16_t reservedInstruction;
255 uint16_t index;
256 uint8_t bus;
257 uint8_t executionState;
258
259 uint16_t irqVector;
260
261 int32_t eiPending;
262 int32_t reservedDiPending;
263 GBSerializedCpuFlags flags;
264 } cpu;
265
266 struct {
267 struct GBSerializedPSGState psg;
268 GBSerializedAudioFlags flags;
269 int32_t nextEvent;
270 int32_t eventDiff;
271 int32_t nextSample;
272 } audio;
273
274 struct {
275 int16_t x;
276 int16_t ly;
277 int32_t nextEvent;
278 int32_t eventDiff;
279 int32_t nextMode;
280 int32_t dotCounter;
281 int32_t frameCounter;
282
283 uint8_t vramCurrentBank;
284 GBSerializedVideoFlags flags;
285 uint16_t reserved;
286
287 uint16_t bcpIndex;
288 uint16_t ocpIndex;
289
290 uint16_t palette[64];
291 } video;
292
293 struct {
294 int32_t nextEvent;
295 int32_t eventDiff;
296
297 int32_t nextDiv;
298 uint32_t internalDiv;
299 uint8_t timaPeriod;
300 GBSerializedTimerFlags flags;
301 uint16_t reserved;
302 } timer;
303
304 struct {
305 uint16_t currentBank;
306 uint8_t wramCurrentBank;
307 uint8_t sramCurrentBank;
308
309 int32_t dmaNext;
310 uint16_t dmaSource;
311 uint16_t dmaDest;
312
313 int32_t hdmaNext;
314 uint16_t hdmaSource;
315 uint16_t hdmaDest;
316
317 uint16_t hdmaRemaining;
318 uint8_t dmaRemaining;
319 uint8_t rtcRegs[5];
320
321 union {
322 struct {
323 uint32_t mode;
324 } mbc1;
325 struct {
326 int8_t machineState;
327 GBMBC7Field field;
328 int8_t address;
329 uint8_t srBits;
330 uint32_t sr;
331 GBSerializedMBC7Flags flags;
332 } mbc7;
333 struct {
334 uint8_t reserved[16];
335 } padding;
336 };
337
338 GBSerializedMemoryFlags flags;
339 uint16_t reserved;
340 } memory;
341
342 uint64_t creationUsec;
343
344 uint32_t reserved[48];
345
346 uint8_t oam[GB_SIZE_OAM];
347
348 uint8_t io[GB_SIZE_IO];
349 uint8_t hram[GB_SIZE_HRAM];
350 uint8_t ie;
351
352 uint8_t vram[GB_SIZE_VRAM];
353 uint8_t wram[GB_SIZE_WORKING_RAM];
354};
355#pragma pack(pop)
356
357bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
358void GBSerialize(struct GB* gb, struct GBSerializedState* state);
359
360#endif