src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
17static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
18static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
19
20void GBAMemoryInit(struct GBAMemory* memory) {
21 memory->d.load32 = GBALoad32;
22 memory->d.load16 = GBALoad16;
23 memory->d.loadU16 = GBALoadU16;
24 memory->d.load8 = GBALoad8;
25 memory->d.loadU8 = GBALoadU8;
26 memory->d.store32 = GBAStore32;
27 memory->d.store16 = GBAStore16;
28 memory->d.store8 = GBAStore8;
29
30 memory->bios = (uint32_t*) hleBios;
31 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
32 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
33 memory->rom = 0;
34 memset(memory->io, 0, sizeof(memory->io));
35 memset(memory->dma, 0, sizeof(memory->dma));
36
37 if (!memory->wram || !memory->iwram) {
38 GBAMemoryDeinit(memory);
39 memory->p->errno = GBA_OUT_OF_MEMORY;
40 memory->p->errstr = GBA_CANNOT_MMAP;
41 }
42
43 int i;
44 for (i = 0; i < 16; ++i) {
45 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
46 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
47 memory->waitstates32[i] = GBA_BASE_WAITSTATES[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
48 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
49 }
50 for (; i < 256; ++i) {
51 memory->waitstates16[i] = 0;
52 memory->waitstatesSeq16[i] = 0;
53 memory->waitstates32[i] = 0;
54 memory->waitstatesSeq32[i] = 0;
55 }
56
57 memory->activeRegion = 0;
58 memory->d.activeRegion = 0;
59 memory->d.activeMask = 0;
60 memory->d.setActiveRegion = GBASetActiveRegion;
61 memory->d.activePrefetchCycles32 = 0;
62 memory->d.activePrefetchCycles16 = 0;
63}
64
65void GBAMemoryDeinit(struct GBAMemory* memory) {
66 munmap(memory->wram, SIZE_WORKING_RAM);
67 munmap(memory->iwram, SIZE_WORKING_IRAM);
68}
69
70static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
71 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
72
73 memory->activePrefetchCycles32 = gbaMemory->waitstates32[address >> BASE_OFFSET];
74 memory->activePrefetchCycles16 = gbaMemory->waitstates16[address >> BASE_OFFSET];
75 gbaMemory->activeRegion = address >> BASE_OFFSET;
76 switch (address & ~OFFSET_MASK) {
77 case BASE_BIOS:
78 memory->activeRegion = gbaMemory->bios;
79 memory->activeMask = SIZE_BIOS - 1;
80 break;
81 case BASE_WORKING_RAM:
82 memory->activeRegion = gbaMemory->wram;
83 memory->activeMask = SIZE_WORKING_RAM - 1;
84 break;
85 case BASE_WORKING_IRAM:
86 memory->activeRegion = gbaMemory->iwram;
87 memory->activeMask = SIZE_WORKING_IRAM - 1;
88 break;
89 case BASE_CART0:
90 case BASE_CART0_EX:
91 case BASE_CART1:
92 case BASE_CART1_EX:
93 case BASE_CART2:
94 case BASE_CART2_EX:
95 memory->activeRegion = gbaMemory->rom;
96 memory->activeMask = SIZE_CART0 - 1;
97 break;
98 default:
99 memory->activeRegion = 0;
100 memory->activeMask = 0;
101 break;
102 }
103}
104
105int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
106 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
107
108 switch (address & ~OFFSET_MASK) {
109 case BASE_BIOS:
110 break;
111 case BASE_WORKING_RAM:
112 return gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
113 case BASE_WORKING_IRAM:
114 return gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
115 case BASE_IO:
116 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
117 case BASE_PALETTE_RAM:
118 break;
119 case BASE_VRAM:
120 break;
121 case BASE_OAM:
122 break;
123 case BASE_CART0:
124 case BASE_CART0_EX:
125 case BASE_CART1:
126 case BASE_CART1_EX:
127 case BASE_CART2:
128 case BASE_CART2_EX:
129 return gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
130 case BASE_CART_SRAM:
131 break;
132 default:
133 break;
134 }
135
136 return 0;
137}
138
139int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
140 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
141
142 switch (address & ~OFFSET_MASK) {
143 case BASE_BIOS:
144 break;
145 case BASE_WORKING_RAM:
146 return ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
147 case BASE_WORKING_IRAM:
148 return ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
149 case BASE_IO:
150 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
151 case BASE_PALETTE_RAM:
152 break;
153 case BASE_VRAM:
154 break;
155 case BASE_OAM:
156 break;
157 case BASE_CART0:
158 case BASE_CART0_EX:
159 case BASE_CART1:
160 case BASE_CART1_EX:
161 case BASE_CART2:
162 case BASE_CART2_EX:
163 return ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
164 case BASE_CART_SRAM:
165 break;
166 default:
167 break;
168 }
169
170 return 0;
171}
172
173uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
174 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
175
176 switch (address & ~OFFSET_MASK) {
177 case BASE_BIOS:
178 break;
179 case BASE_WORKING_RAM:
180 return ((uint16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
181 case BASE_WORKING_IRAM:
182 return ((uint16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
183 case BASE_IO:
184 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
185 case BASE_PALETTE_RAM:
186 break;
187 case BASE_VRAM:
188 break;
189 case BASE_OAM:
190 break;
191 case BASE_CART0:
192 case BASE_CART0_EX:
193 case BASE_CART1:
194 case BASE_CART1_EX:
195 case BASE_CART2:
196 case BASE_CART2_EX:
197 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
198 case BASE_CART_SRAM:
199 break;
200 default:
201 break;
202 }
203
204 return 0;
205}
206
207int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
208 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
209
210 switch (address & ~OFFSET_MASK) {
211 case BASE_BIOS:
212 break;
213 case BASE_WORKING_RAM:
214 return ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
215 case BASE_WORKING_IRAM:
216 return ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
217 case BASE_IO:
218 break;
219 case BASE_PALETTE_RAM:
220 break;
221 case BASE_VRAM:
222 break;
223 case BASE_OAM:
224 break;
225 case BASE_CART0:
226 case BASE_CART0_EX:
227 case BASE_CART1:
228 case BASE_CART1_EX:
229 case BASE_CART2:
230 case BASE_CART2_EX:
231 return ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
232 case BASE_CART_SRAM:
233 break;
234 default:
235 break;
236 }
237
238 return 0;
239}
240
241uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
242 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
243
244 switch (address & ~OFFSET_MASK) {
245 case BASE_BIOS:
246 break;
247 case BASE_WORKING_RAM:
248 return ((uint8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
249 break;
250 case BASE_WORKING_IRAM:
251 return ((uint8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
252 break;
253 case BASE_IO:
254 return (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
255 case BASE_PALETTE_RAM:
256 break;
257 case BASE_VRAM:
258 break;
259 case BASE_OAM:
260 break;
261 case BASE_CART0:
262 case BASE_CART0_EX:
263 case BASE_CART1:
264 case BASE_CART1_EX:
265 case BASE_CART2:
266 case BASE_CART2_EX:
267 return ((uint8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
268 case BASE_CART_SRAM:
269 break;
270 default:
271 break;
272 }
273
274 return 0;
275}
276
277void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
278 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
279
280 switch (address & ~OFFSET_MASK) {
281 case BASE_WORKING_RAM:
282 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
283 break;
284 case BASE_WORKING_IRAM:
285 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
286 break;
287 case BASE_IO:
288 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
289 break;
290 case BASE_PALETTE_RAM:
291 break;
292 case BASE_VRAM:
293 break;
294 case BASE_OAM:
295 break;
296 case BASE_CART0:
297 break;
298 case BASE_CART2_EX:
299 break;
300 case BASE_CART_SRAM:
301 break;
302 default:
303 break;
304 }
305}
306
307void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
308 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
309
310 switch (address & ~OFFSET_MASK) {
311 case BASE_WORKING_RAM:
312 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
313 break;
314 case BASE_WORKING_IRAM:
315 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
316 break;
317 case BASE_IO:
318 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
319 break;
320 case BASE_PALETTE_RAM:
321 break;
322 case BASE_VRAM:
323 break;
324 case BASE_OAM:
325 break;
326 case BASE_CART0:
327 break;
328 case BASE_CART2_EX:
329 break;
330 case BASE_CART_SRAM:
331 break;
332 default:
333 break;
334 }
335}
336
337void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
338 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
339
340 switch (address & ~OFFSET_MASK) {
341 case BASE_WORKING_RAM:
342 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
343 break;
344 case BASE_WORKING_IRAM:
345 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
346 break;
347 case BASE_IO:
348 break;
349 case BASE_PALETTE_RAM:
350 break;
351 case BASE_VRAM:
352 break;
353 case BASE_OAM:
354 break;
355 case BASE_CART0:
356 break;
357 case BASE_CART2_EX:
358 break;
359 case BASE_CART_SRAM:
360 break;
361 default:
362 break;
363 }
364}
365
366void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
367 int sram = parameters & 0x0003;
368 int ws0 = (parameters & 0x000C) >> 2;
369 int ws0seq = (parameters & 0x0010) >> 4;
370 int ws1 = (parameters & 0x0060) >> 5;
371 int ws1seq = (parameters & 0x0080) >> 7;
372 int ws2 = (parameters & 0x0300) >> 8;
373 int ws2seq = (parameters & 0x0400) >> 10;
374 int prefetch = parameters & 0x4000;
375
376 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
377 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
378 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
379 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
380
381 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
382 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
383 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
384
385 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
386 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
387 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
388
389 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
390 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
391 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
392
393 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0 + 1] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
394 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1 + 1] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
395 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2 + 1] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
396
397 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
398 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
399}
400
401int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
402 struct GBADMA* dma;
403 int32_t test = INT_MAX;
404
405 dma = &memory->dma[0];
406 dma->nextIRQ -= cycles;
407 if (dma->enable && dma->doIrq && dma->nextIRQ) {
408 if (dma->nextIRQ <= 0) {
409 dma->nextIRQ = INT_MAX;
410 GBARaiseIRQ(memory->p, IRQ_DMA0);
411 } else if (dma->nextIRQ < test) {
412 test = dma->nextIRQ;
413 }
414 }
415
416 dma = &memory->dma[1];
417 dma->nextIRQ -= cycles;
418 if (dma->enable && dma->doIrq && dma->nextIRQ) {
419 if (dma->nextIRQ <= 0) {
420 dma->nextIRQ = INT_MAX;
421 GBARaiseIRQ(memory->p, IRQ_DMA1);
422 } else if (dma->nextIRQ < test) {
423 test = dma->nextIRQ;
424 }
425 }
426
427 dma = &memory->dma[2];
428 dma->nextIRQ -= cycles;
429 if (dma->enable && dma->doIrq && dma->nextIRQ) {
430 if (dma->nextIRQ <= 0) {
431 dma->nextIRQ = INT_MAX;
432 GBARaiseIRQ(memory->p, IRQ_DMA2);
433 } else if (dma->nextIRQ < test) {
434 test = dma->nextIRQ;
435 }
436 }
437
438 dma = &memory->dma[3];
439 dma->nextIRQ -= cycles;
440 if (dma->enable && dma->doIrq && dma->nextIRQ) {
441 if (dma->nextIRQ <= 0) {
442 dma->nextIRQ = INT_MAX;
443 GBARaiseIRQ(memory->p, IRQ_DMA3);
444 } else if (dma->nextIRQ < test) {
445 test = dma->nextIRQ;
446 }
447 }
448
449 return test;
450}
451
452void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
453 memory->dma[dma].source = address & 0xFFFFFFFE;
454}
455
456void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
457 memory->dma[dma].dest = address & 0xFFFFFFFE;
458}
459
460void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
461 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
462}
463
464uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
465 struct GBADMA* currentDma = &memory->dma[dma];
466 int wasEnabled = currentDma->enable;
467 currentDma->packed = control;
468 currentDma->nextIRQ = 0;
469
470 if (currentDma->drq) {
471 GBALog(GBA_LOG_STUB, "DRQ not implemented");
472 }
473
474 if (!wasEnabled && currentDma->enable) {
475 currentDma->nextSource = currentDma->source;
476 currentDma->nextDest = currentDma->dest;
477 currentDma->nextCount = currentDma->count;
478 GBAMemoryScheduleDMA(memory, dma, currentDma);
479 }
480 // If the DMA has already occurred, this value might have changed since the function started
481 return currentDma->packed;
482};
483
484void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
485 switch (info->timing) {
486 case DMA_TIMING_NOW:
487 GBAMemoryServiceDMA(memory, number, info);
488 break;
489 case DMA_TIMING_HBLANK:
490 // Handled implicitly
491 break;
492 case DMA_TIMING_VBLANK:
493 // Handled implicitly
494 break;
495 case DMA_TIMING_CUSTOM:
496 switch (number) {
497 case 0:
498 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
499 break;
500 case 1:
501 case 2:
502 //this.cpu.irq.audio.scheduleFIFODma(number, info);
503 break;
504 case 3:
505 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
506 break;
507 }
508 }
509}
510
511void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
512 struct GBADMA* dma;
513 int i;
514 for (i = 0; i < 4; ++i) {
515 dma = &memory->dma[i];
516 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
517 GBAMemoryServiceDMA(memory, i, dma);
518 }
519 }
520}
521
522void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
523 struct GBADMA* dma;
524 int i;
525 for (i = 0; i < 4; ++i) {
526 dma = &memory->dma[i];
527 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
528 GBAMemoryServiceDMA(memory, i, dma);
529 }
530 }
531}
532
533void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
534 if (!info->enable) {
535 // There was a DMA scheduled that got canceled
536 return;
537 }
538
539 uint32_t width = info->width ? 4 : 2;
540 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
541 int destOffset = DMA_OFFSET[info->dstControl] * width;
542 int32_t wordsRemaining = info->nextCount;
543 uint32_t source = info->nextSource;
544 uint32_t dest = info->nextDest;
545 uint32_t sourceRegion = source >> BASE_OFFSET;
546 uint32_t destRegion = dest >> BASE_OFFSET;
547
548 if (width == 4) {
549 int32_t word;
550 source &= 0xFFFFFFFC;
551 dest &= 0xFFFFFFFC;
552 while (wordsRemaining--) {
553 word = GBALoad32(&memory->d, source);
554 GBAStore32(&memory->d, dest, word);
555 source += sourceOffset;
556 dest += destOffset;
557 }
558 } else {
559 uint16_t word;
560 while (wordsRemaining--) {
561 word = GBALoadU16(&memory->d, source);
562 GBAStore16(&memory->d, dest, word);
563 source += sourceOffset;
564 dest += destOffset;
565 }
566 }
567
568 if (info->doIrq) {
569 info->nextIRQ = memory->p->cpu.cycles + 2;
570 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
571 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
572 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
573 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
574 }
575
576 info->nextSource = source;
577 info->nextDest = dest;
578 info->nextCount = wordsRemaining;
579
580 if (!info->repeat) {
581 info->enable = 0;
582
583 // Clear the enable bit in memory
584 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
585 } else {
586 info->nextCount = info->count;
587 if (info->dstControl == DMA_INCREMENT_RELOAD) {
588 info->nextDest = info->dest;
589 }
590 GBAMemoryScheduleDMA(memory, number, info);
591 }
592}