src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25
26static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
27static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
28static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
29static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
30static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
31static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
32static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
33
34void GBAMemoryInit(struct GBA* gba) {
35 struct ARMCore* cpu = gba->cpu;
36 cpu->memory.load32 = GBALoad32;
37 cpu->memory.load16 = GBALoad16;
38 cpu->memory.load8 = GBALoad8;
39 cpu->memory.loadMultiple = GBALoadMultiple;
40 cpu->memory.store32 = GBAStore32;
41 cpu->memory.store16 = GBAStore16;
42 cpu->memory.store8 = GBAStore8;
43 cpu->memory.storeMultiple = GBAStoreMultiple;
44
45 gba->memory.bios = (uint32_t*) hleBios;
46 gba->memory.fullBios = 0;
47 gba->memory.wram = 0;
48 gba->memory.iwram = 0;
49 gba->memory.rom = 0;
50 gba->memory.romSize = 0;
51 gba->memory.hw.p = gba;
52
53 int i;
54 for (i = 0; i < 16; ++i) {
55 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
56 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
57 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
60 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
61 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 }
64 for (; i < 256; ++i) {
65 gba->memory.waitstatesNonseq16[i] = 0;
66 gba->memory.waitstatesSeq16[i] = 0;
67 gba->memory.waitstatesNonseq32[i] = 0;
68 gba->memory.waitstatesSeq32[i] = 0;
69 }
70
71 gba->memory.activeRegion = -1;
72 cpu->memory.activeRegion = 0;
73 cpu->memory.activeMask = 0;
74 cpu->memory.setActiveRegion = GBASetActiveRegion;
75 cpu->memory.activeSeqCycles32 = 0;
76 cpu->memory.activeSeqCycles16 = 0;
77 cpu->memory.activeNonseqCycles32 = 0;
78 cpu->memory.activeNonseqCycles16 = 0;
79 cpu->memory.activeUncachedCycles32 = 0;
80 cpu->memory.activeUncachedCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 if (!gba->memory.wram || !gba->memory.iwram) {
117 GBAMemoryDeinit(gba);
118 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
119 }
120}
121
122static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
123 struct ARMInstructionInfo info;
124 uint32_t nextAddress = address;
125 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
126 if (cpu->executionMode == MODE_THUMB) {
127 while (true) {
128 uint16_t opcode;
129 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
130 ARMDecodeThumb(opcode, &info);
131 switch (info.branchType) {
132 case ARM_BRANCH_NONE:
133 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
134 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
135 gba->idleDetectionStep = -1;
136 return;
137 }
138 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
139 uint32_t offset = 0;
140 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
141 offset = info.memory.offset.immediate;
142 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
143 int reg = info.memory.offset.reg;
144 if (gba->cachedRegisters[reg]) {
145 gba->idleDetectionStep = -1;
146 return;
147 }
148 offset = gba->cachedRegisters[reg];
149 }
150 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
151 loadAddress -= offset;
152 } else {
153 loadAddress += offset;
154 }
155 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
156 gba->idleDetectionStep = -1;
157 return;
158 }
159 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
160 gba->taintedRegisters[info.op1.reg] = true;
161 } else {
162 switch (info.memory.width) {
163 case 1:
164 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
165 break;
166 case 2:
167 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
168 break;
169 case 4:
170 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
171 break;
172 }
173 }
174 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
175 gba->taintedRegisters[info.op1.reg] = true;
176 }
177 nextAddress += WORD_SIZE_THUMB;
178 break;
179 case ARM_BRANCH:
180 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
181 gba->idleLoop = address;
182 gba->idleOptimization = IDLE_LOOP_REMOVE;
183 }
184 gba->idleDetectionStep = -1;
185 return;
186 default:
187 gba->idleDetectionStep = -1;
188 return;
189 }
190 }
191 } else {
192 gba->idleDetectionStep = -1;
193 }
194}
195
196static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
197 struct GBA* gba = (struct GBA*) cpu->master;
198 struct GBAMemory* memory = &gba->memory;
199
200 int newRegion = address >> BASE_OFFSET;
201 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
202 if (address == gba->idleLoop) {
203 if (gba->haltPending) {
204 gba->haltPending = false;
205 GBAHalt(gba);
206 } else {
207 gba->haltPending = true;
208 }
209 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
210 if (address == gba->lastJump) {
211 switch (gba->idleDetectionStep) {
212 case 0:
213 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
214 ++gba->idleDetectionStep;
215 break;
216 case 1:
217 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
218 gba->idleDetectionStep = -1;
219 ++gba->idleDetectionFailures;
220 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
221 gba->idleOptimization = IDLE_LOOP_IGNORE;
222 }
223 break;
224 }
225 _analyzeForIdleLoop(gba, cpu, address);
226 break;
227 }
228 } else {
229 gba->idleDetectionStep = 0;
230 }
231 }
232 }
233
234 gba->lastJump = address;
235 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
236 return;
237 }
238
239 if (memory->activeRegion == REGION_BIOS) {
240 memory->biosPrefetch = cpu->prefetch[1];
241 }
242 memory->activeRegion = newRegion;
243 switch (newRegion) {
244 case REGION_BIOS:
245 cpu->memory.activeRegion = memory->bios;
246 cpu->memory.activeMask = SIZE_BIOS - 1;
247 break;
248 case REGION_WORKING_RAM:
249 cpu->memory.activeRegion = memory->wram;
250 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
251 break;
252 case REGION_WORKING_IRAM:
253 cpu->memory.activeRegion = memory->iwram;
254 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
255 break;
256 case REGION_VRAM:
257 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
258 cpu->memory.activeMask = 0x0000FFFF;
259 break;
260 case REGION_CART0:
261 case REGION_CART0_EX:
262 case REGION_CART1:
263 case REGION_CART1_EX:
264 case REGION_CART2:
265 case REGION_CART2_EX:
266 cpu->memory.activeRegion = memory->rom;
267 cpu->memory.activeMask = SIZE_CART0 - 1;
268 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
269 break;
270 }
271 // Fall through
272 default:
273 memory->activeRegion = -1;
274 cpu->memory.activeRegion = _deadbeef;
275 cpu->memory.activeMask = 0;
276 if (!gba->yankedRomSize) {
277 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
278 }
279 return;
280 }
281 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[newRegion];
282 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[newRegion];
283 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[newRegion];
284 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[newRegion];
285 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[newRegion];
286 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[newRegion];
287}
288
289#define LOAD_BAD \
290 if (gba->performingDMA) { \
291 value = gba->bus; \
292 } else { \
293 value = cpu->prefetch[1]; \
294 if (cpu->executionMode == MODE_THUMB) { \
295 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
296 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
297 case REGION_BIOS: \
298 case REGION_OAM: \
299 /* This isn't right half the time, but we don't have $+6 handy */ \
300 value <<= 16; \
301 value |= cpu->prefetch[0]; \
302 break; \
303 case REGION_WORKING_IRAM: \
304 /* This doesn't handle prefetch clobbering */ \
305 if (cpu->gprs[ARM_PC] & 2) { \
306 value |= cpu->prefetch[0] << 16; \
307 } else { \
308 value <<= 16; \
309 value |= cpu->prefetch[0]; \
310 } \
311 default: \
312 value |= value << 16; \
313 } \
314 } \
315 }
316
317#define LOAD_BIOS \
318 if (address < SIZE_BIOS) { \
319 if (memory->activeRegion == REGION_BIOS) { \
320 LOAD_32(value, address, memory->bios); \
321 } else { \
322 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
323 value = memory->biosPrefetch; \
324 } \
325 } else { \
326 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
327 LOAD_BAD; \
328 }
329
330#define LOAD_WORKING_RAM \
331 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
332 wait += waitstatesRegion[REGION_WORKING_RAM];
333
334#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
335#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
336
337#define LOAD_PALETTE_RAM \
338 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
339 wait += waitstatesRegion[REGION_PALETTE_RAM];
340
341#define LOAD_VRAM \
342 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
343 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
344 } else { \
345 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
346 } \
347 wait += waitstatesRegion[REGION_VRAM];
348
349#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
350
351#define LOAD_CART \
352 wait += waitstatesRegion[address >> BASE_OFFSET]; \
353 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
354 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
355 } else { \
356 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
357 value = (address >> 1) & 0xFFFF; \
358 value |= ((address + 2) >> 1) << 16; \
359 }
360
361#define LOAD_SRAM \
362 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
363 value = GBALoad8(cpu, address, 0); \
364 value |= value << 8; \
365 value |= value << 16;
366
367uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
368 struct GBA* gba = (struct GBA*) cpu->master;
369 struct GBAMemory* memory = &gba->memory;
370 uint32_t value = 0;
371 int wait = 0;
372 char* waitstatesRegion = memory->waitstatesNonseq32;
373
374 switch (address >> BASE_OFFSET) {
375 case REGION_BIOS:
376 LOAD_BIOS;
377 break;
378 case REGION_WORKING_RAM:
379 LOAD_WORKING_RAM;
380 break;
381 case REGION_WORKING_IRAM:
382 LOAD_WORKING_IRAM;
383 break;
384 case REGION_IO:
385 LOAD_IO;
386 break;
387 case REGION_PALETTE_RAM:
388 LOAD_PALETTE_RAM;
389 break;
390 case REGION_VRAM:
391 LOAD_VRAM;
392 break;
393 case REGION_OAM:
394 LOAD_OAM;
395 break;
396 case REGION_CART0:
397 case REGION_CART0_EX:
398 case REGION_CART1:
399 case REGION_CART1_EX:
400 case REGION_CART2:
401 case REGION_CART2_EX:
402 LOAD_CART;
403 break;
404 case REGION_CART_SRAM:
405 case REGION_CART_SRAM_MIRROR:
406 LOAD_SRAM;
407 break;
408 default:
409 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
410 LOAD_BAD;
411 break;
412 }
413
414 if (cycleCounter) {
415 *cycleCounter += 1 + wait;
416 }
417 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
418 int rotate = (address & 3) << 3;
419 return ROR(value, rotate);
420}
421
422uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
423 struct GBA* gba = (struct GBA*) cpu->master;
424 struct GBAMemory* memory = &gba->memory;
425 uint32_t value = 0;
426 int wait = 0;
427
428 switch (address >> BASE_OFFSET) {
429 case REGION_BIOS:
430 if (address < SIZE_BIOS) {
431 if (memory->activeRegion == REGION_BIOS) {
432 LOAD_16(value, address, memory->bios);
433 } else {
434 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
435 LOAD_16(value, address & 2, &memory->biosPrefetch);
436 }
437 } else {
438 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
439 LOAD_BAD;
440 uint32_t v2 = value;
441 LOAD_16(value, address & 2, &v2);
442 }
443 break;
444 case REGION_WORKING_RAM:
445 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
446 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
447 break;
448 case REGION_WORKING_IRAM:
449 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
450 break;
451 case REGION_IO:
452 value = GBAIORead(gba, address & (SIZE_IO - 2));
453 break;
454 case REGION_PALETTE_RAM:
455 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
456 break;
457 case REGION_VRAM:
458 if ((address & 0x0001FFFF) < SIZE_VRAM) {
459 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
460 } else {
461 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
462 }
463 break;
464 case REGION_OAM:
465 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
466 break;
467 case REGION_CART0:
468 case REGION_CART0_EX:
469 case REGION_CART1:
470 case REGION_CART1_EX:
471 case REGION_CART2:
472 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
473 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
474 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
475 } else {
476 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
477 value = (address >> 1) & 0xFFFF; \
478 }
479 break;
480 case REGION_CART2_EX:
481 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
482 if (memory->savedata.type == SAVEDATA_EEPROM) {
483 value = GBASavedataReadEEPROM(&memory->savedata);
484 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
485 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
486 } else {
487 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
488 value = (address >> 1) & 0xFFFF; \
489 }
490 break;
491 case REGION_CART_SRAM:
492 case REGION_CART_SRAM_MIRROR:
493 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
494 value = GBALoad8(cpu, address, 0);
495 value |= value << 8;
496 break;
497 default:
498 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
499 LOAD_BAD;
500 uint32_t v2 = value;
501 LOAD_16(value, address & 2, &v2);
502 break;
503 }
504
505 if (cycleCounter) {
506 *cycleCounter += 1 + wait;
507 }
508 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
509 int rotate = (address & 1) << 3;
510 return ROR(value, rotate);
511}
512
513uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
514 struct GBA* gba = (struct GBA*) cpu->master;
515 struct GBAMemory* memory = &gba->memory;
516 uint32_t value = 0;
517 int wait = 0;
518
519 switch (address >> BASE_OFFSET) {
520 case REGION_BIOS:
521 if (address < SIZE_BIOS) {
522 if (memory->activeRegion == REGION_BIOS) {
523 value = ((uint8_t*) memory->bios)[address];
524 } else {
525 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
526 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
527 }
528 } else {
529 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
530 LOAD_BAD;
531 value = ((uint8_t*) &value)[address & 3];
532 }
533 break;
534 case REGION_WORKING_RAM:
535 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
536 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
537 break;
538 case REGION_WORKING_IRAM:
539 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
540 break;
541 case REGION_IO:
542 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
543 break;
544 case REGION_PALETTE_RAM:
545 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
546 break;
547 case REGION_VRAM:
548 if ((address & 0x0001FFFF) < SIZE_VRAM) {
549 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
550 } else {
551 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
552 }
553 break;
554 case REGION_OAM:
555 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
556 break;
557 case REGION_CART0:
558 case REGION_CART0_EX:
559 case REGION_CART1:
560 case REGION_CART1_EX:
561 case REGION_CART2:
562 case REGION_CART2_EX:
563 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
564 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
565 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
566 } else {
567 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
568 value = (address >> 1) & 0xFF; \
569 }
570 break;
571 case REGION_CART_SRAM:
572 case REGION_CART_SRAM_MIRROR:
573 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
574 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
575 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
576 GBASavedataInitSRAM(&memory->savedata);
577 }
578 if (memory->savedata.type == SAVEDATA_SRAM) {
579 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
580 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
581 value = GBASavedataReadFlash(&memory->savedata, address);
582 } else if (memory->hw.devices & HW_TILT) {
583 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
584 } else {
585 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
586 value = 0xFF;
587 }
588 value &= 0xFF;
589 break;
590 default:
591 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
592 LOAD_BAD;
593 value = ((uint8_t*) &value)[address & 3];
594 break;
595 }
596
597 if (cycleCounter) {
598 *cycleCounter += 1 + wait;
599 }
600 return value;
601}
602
603#define STORE_WORKING_RAM \
604 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
605 wait += waitstatesRegion[REGION_WORKING_RAM];
606
607#define STORE_WORKING_IRAM \
608 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
609
610#define STORE_IO \
611 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
612
613#define STORE_PALETTE_RAM \
614 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
615 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
616 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
617 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
618
619#define STORE_VRAM \
620 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
621 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
622 } else { \
623 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
624 } \
625 wait += waitstatesRegion[REGION_VRAM];
626
627#define STORE_OAM \
628 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
629 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
630 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
631
632#define STORE_CART \
633 wait += waitstatesRegion[address >> BASE_OFFSET]; \
634 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
635
636#define STORE_SRAM \
637 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
638
639#define STORE_BAD \
640 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
641
642void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
643 struct GBA* gba = (struct GBA*) cpu->master;
644 struct GBAMemory* memory = &gba->memory;
645 int wait = 0;
646 char* waitstatesRegion = memory->waitstatesNonseq32;
647
648 switch (address >> BASE_OFFSET) {
649 case REGION_WORKING_RAM:
650 STORE_WORKING_RAM;
651 break;
652 case REGION_WORKING_IRAM:
653 STORE_WORKING_IRAM
654 break;
655 case REGION_IO:
656 STORE_IO;
657 break;
658 case REGION_PALETTE_RAM:
659 STORE_PALETTE_RAM;
660 break;
661 case REGION_VRAM:
662 STORE_VRAM;
663 break;
664 case REGION_OAM:
665 STORE_OAM;
666 break;
667 case REGION_CART0:
668 case REGION_CART0_EX:
669 case REGION_CART1:
670 case REGION_CART1_EX:
671 case REGION_CART2:
672 case REGION_CART2_EX:
673 STORE_CART;
674 break;
675 case REGION_CART_SRAM:
676 case REGION_CART_SRAM_MIRROR:
677 STORE_SRAM;
678 break;
679 default:
680 STORE_BAD;
681 break;
682 }
683
684 if (cycleCounter) {
685 *cycleCounter += 1 + wait;
686 }
687}
688
689void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
690 struct GBA* gba = (struct GBA*) cpu->master;
691 struct GBAMemory* memory = &gba->memory;
692 int wait = 0;
693
694 switch (address >> BASE_OFFSET) {
695 case REGION_WORKING_RAM:
696 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
697 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
698 break;
699 case REGION_WORKING_IRAM:
700 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
701 break;
702 case REGION_IO:
703 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
704 break;
705 case REGION_PALETTE_RAM:
706 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
707 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
708 break;
709 case REGION_VRAM:
710 if ((address & 0x0001FFFF) < SIZE_VRAM) {
711 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
712 } else {
713 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
714 }
715 break;
716 case REGION_OAM:
717 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
718 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
719 break;
720 case REGION_CART0:
721 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
722 uint32_t reg = address & 0xFFFFFE;
723 GBAHardwareGPIOWrite(&memory->hw, reg, value);
724 } else {
725 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
726 }
727 break;
728 case REGION_CART2_EX:
729 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
730 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
731 GBASavedataInitEEPROM(&memory->savedata);
732 }
733 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
734 break;
735 case REGION_CART_SRAM:
736 case REGION_CART_SRAM_MIRROR:
737 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
738 break;
739 default:
740 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
741 break;
742 }
743
744 if (cycleCounter) {
745 *cycleCounter += 1 + wait;
746 }
747}
748
749void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
750 struct GBA* gba = (struct GBA*) cpu->master;
751 struct GBAMemory* memory = &gba->memory;
752 int wait = 0;
753
754 switch (address >> BASE_OFFSET) {
755 case REGION_WORKING_RAM:
756 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
757 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
758 break;
759 case REGION_WORKING_IRAM:
760 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
761 break;
762 case REGION_IO:
763 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
764 break;
765 case REGION_PALETTE_RAM:
766 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
767 break;
768 case REGION_VRAM:
769 if (address >= 0x06018000) {
770 // TODO: check BG mode
771 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
772 break;
773 }
774 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
775 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
776 break;
777 case REGION_OAM:
778 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
779 break;
780 case REGION_CART0:
781 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
782 break;
783 case REGION_CART_SRAM:
784 case REGION_CART_SRAM_MIRROR:
785 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
786 if (address == SAVEDATA_FLASH_BASE) {
787 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
788 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
789 } else {
790 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
791 GBASavedataInitSRAM(&memory->savedata);
792 }
793 }
794 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
795 GBASavedataWriteFlash(&memory->savedata, address, value);
796 } else if (memory->savedata.type == SAVEDATA_SRAM) {
797 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
798 } else if (memory->hw.devices & HW_TILT) {
799 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
800 } else {
801 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
802 }
803 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
804 break;
805 default:
806 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
807 break;
808 }
809
810 if (cycleCounter) {
811 *cycleCounter += 1 + wait;
812 }
813}
814
815void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
816 struct GBA* gba = (struct GBA*) cpu->master;
817 struct GBAMemory* memory = &gba->memory;
818 int32_t oldValue = -1;
819
820 switch (address >> BASE_OFFSET) {
821 case REGION_WORKING_RAM:
822 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
823 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
824 break;
825 case REGION_WORKING_IRAM:
826 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
827 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
828 break;
829 case REGION_IO:
830 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
831 break;
832 case REGION_PALETTE_RAM:
833 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
834 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
835 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
836 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
837 break;
838 case REGION_VRAM:
839 if ((address & 0x0001FFFF) < SIZE_VRAM) {
840 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
841 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
842 } else {
843 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
844 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
845 }
846 break;
847 case REGION_OAM:
848 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
849 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
850 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
851 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
852 break;
853 case REGION_CART0:
854 case REGION_CART0_EX:
855 case REGION_CART1:
856 case REGION_CART1_EX:
857 case REGION_CART2:
858 case REGION_CART2_EX:
859 _pristineCow(gba);
860 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
861 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
862 }
863 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
864 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
865 break;
866 case REGION_CART_SRAM:
867 case REGION_CART_SRAM_MIRROR:
868 if (memory->savedata.type == SAVEDATA_SRAM) {
869 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
870 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
871 } else {
872 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
873 }
874 break;
875 default:
876 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
877 break;
878 }
879 if (old) {
880 *old = oldValue;
881 }
882}
883
884void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
885 struct GBA* gba = (struct GBA*) cpu->master;
886 struct GBAMemory* memory = &gba->memory;
887 int16_t oldValue = -1;
888
889 switch (address >> BASE_OFFSET) {
890 case REGION_WORKING_RAM:
891 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
892 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
893 break;
894 case REGION_WORKING_IRAM:
895 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
896 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
897 break;
898 case REGION_IO:
899 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
900 break;
901 case REGION_PALETTE_RAM:
902 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
903 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
904 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
905 break;
906 case REGION_VRAM:
907 if ((address & 0x0001FFFF) < SIZE_VRAM) {
908 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
909 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
910 } else {
911 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
912 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
913 }
914 break;
915 case REGION_OAM:
916 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
917 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
918 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
919 break;
920 case REGION_CART0:
921 case REGION_CART0_EX:
922 case REGION_CART1:
923 case REGION_CART1_EX:
924 case REGION_CART2:
925 case REGION_CART2_EX:
926 _pristineCow(gba);
927 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
928 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
929 }
930 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
931 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
932 break;
933 case REGION_CART_SRAM:
934 case REGION_CART_SRAM_MIRROR:
935 if (memory->savedata.type == SAVEDATA_SRAM) {
936 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
937 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
938 } else {
939 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
940 }
941 break;
942 default:
943 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
944 break;
945 }
946 if (old) {
947 *old = oldValue;
948 }
949}
950
951void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
952 struct GBA* gba = (struct GBA*) cpu->master;
953 struct GBAMemory* memory = &gba->memory;
954 int8_t oldValue = -1;
955
956 switch (address >> BASE_OFFSET) {
957 case REGION_WORKING_RAM:
958 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
959 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
960 break;
961 case REGION_WORKING_IRAM:
962 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
963 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
964 break;
965 case REGION_IO:
966 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
967 break;
968 case REGION_PALETTE_RAM:
969 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
970 break;
971 case REGION_VRAM:
972 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
973 break;
974 case REGION_OAM:
975 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
976 break;
977 case REGION_CART0:
978 case REGION_CART0_EX:
979 case REGION_CART1:
980 case REGION_CART1_EX:
981 case REGION_CART2:
982 case REGION_CART2_EX:
983 _pristineCow(gba);
984 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
985 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
986 }
987 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
988 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
989 break;
990 case REGION_CART_SRAM:
991 case REGION_CART_SRAM_MIRROR:
992 if (memory->savedata.type == SAVEDATA_SRAM) {
993 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
994 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
995 } else {
996 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
997 }
998 break;
999 default:
1000 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1001 break;
1002 }
1003 if (old) {
1004 *old = oldValue;
1005 }
1006}
1007
1008#define LDM_LOOP(LDM) \
1009 for (i = 0; i < 16; i += 4) { \
1010 if (UNLIKELY(mask & (1 << i))) { \
1011 LDM; \
1012 waitstatesRegion = memory->waitstatesSeq32; \
1013 cpu->gprs[i] = value; \
1014 ++wait; \
1015 address += 4; \
1016 } \
1017 if (UNLIKELY(mask & (2 << i))) { \
1018 LDM; \
1019 waitstatesRegion = memory->waitstatesSeq32; \
1020 cpu->gprs[i + 1] = value; \
1021 ++wait; \
1022 address += 4; \
1023 } \
1024 if (UNLIKELY(mask & (4 << i))) { \
1025 LDM; \
1026 waitstatesRegion = memory->waitstatesSeq32; \
1027 cpu->gprs[i + 2] = value; \
1028 ++wait; \
1029 address += 4; \
1030 } \
1031 if (UNLIKELY(mask & (8 << i))) { \
1032 LDM; \
1033 waitstatesRegion = memory->waitstatesSeq32; \
1034 cpu->gprs[i + 3] = value; \
1035 ++wait; \
1036 address += 4; \
1037 } \
1038 }
1039
1040uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1041 struct GBA* gba = (struct GBA*) cpu->master;
1042 struct GBAMemory* memory = &gba->memory;
1043 uint32_t value;
1044 int wait = 0;
1045 char* waitstatesRegion = memory->waitstatesNonseq32;
1046
1047 int i;
1048 int offset = 4;
1049 int popcount = 0;
1050 if (direction & LSM_D) {
1051 offset = -4;
1052 popcount = _popcount32(mask);
1053 address -= (popcount << 2) - 4;
1054 }
1055
1056 if (direction & LSM_B) {
1057 address += offset;
1058 }
1059
1060 uint32_t addressMisalign = address & 0x3;
1061 address &= 0xFFFFFFFC;
1062
1063 switch (address >> BASE_OFFSET) {
1064 case REGION_BIOS:
1065 LDM_LOOP(LOAD_BIOS);
1066 break;
1067 case REGION_WORKING_RAM:
1068 LDM_LOOP(LOAD_WORKING_RAM);
1069 break;
1070 case REGION_WORKING_IRAM:
1071 LDM_LOOP(LOAD_WORKING_IRAM);
1072 break;
1073 case REGION_IO:
1074 LDM_LOOP(LOAD_IO);
1075 break;
1076 case REGION_PALETTE_RAM:
1077 LDM_LOOP(LOAD_PALETTE_RAM);
1078 break;
1079 case REGION_VRAM:
1080 LDM_LOOP(LOAD_VRAM);
1081 break;
1082 case REGION_OAM:
1083 LDM_LOOP(LOAD_OAM);
1084 break;
1085 case REGION_CART0:
1086 case REGION_CART0_EX:
1087 case REGION_CART1:
1088 case REGION_CART1_EX:
1089 case REGION_CART2:
1090 case REGION_CART2_EX:
1091 LDM_LOOP(LOAD_CART);
1092 break;
1093 case REGION_CART_SRAM:
1094 case REGION_CART_SRAM_MIRROR:
1095 LDM_LOOP(LOAD_SRAM);
1096 break;
1097 default:
1098 LDM_LOOP(LOAD_BAD);
1099 break;
1100 }
1101
1102 if (cycleCounter) {
1103 *cycleCounter += wait;
1104 }
1105
1106 if (direction & LSM_B) {
1107 address -= offset;
1108 }
1109
1110 if (direction & LSM_D) {
1111 address -= (popcount << 2) + 4;
1112 }
1113
1114 return address | addressMisalign;
1115}
1116
1117#define STM_LOOP(STM) \
1118 for (i = 0; i < 16; i += 4) { \
1119 if (UNLIKELY(mask & (1 << i))) { \
1120 value = cpu->gprs[i]; \
1121 STM; \
1122 waitstatesRegion = memory->waitstatesSeq32; \
1123 ++wait; \
1124 address += 4; \
1125 } \
1126 if (UNLIKELY(mask & (2 << i))) { \
1127 value = cpu->gprs[i + 1]; \
1128 STM; \
1129 waitstatesRegion = memory->waitstatesSeq32; \
1130 ++wait; \
1131 address += 4; \
1132 } \
1133 if (UNLIKELY(mask & (4 << i))) { \
1134 value = cpu->gprs[i + 2]; \
1135 STM; \
1136 waitstatesRegion = memory->waitstatesSeq32; \
1137 ++wait; \
1138 address += 4; \
1139 } \
1140 if (UNLIKELY(mask & (8 << i))) { \
1141 value = cpu->gprs[i + 3]; \
1142 STM; \
1143 waitstatesRegion = memory->waitstatesSeq32; \
1144 ++wait; \
1145 address += 4; \
1146 } \
1147 }
1148
1149uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1150 struct GBA* gba = (struct GBA*) cpu->master;
1151 struct GBAMemory* memory = &gba->memory;
1152 uint32_t value;
1153 int wait = 0;
1154 char* waitstatesRegion = memory->waitstatesNonseq32;
1155
1156 int i;
1157 int offset = 4;
1158 int popcount = 0;
1159 if (direction & LSM_D) {
1160 offset = -4;
1161 popcount = _popcount32(mask);
1162 address -= (popcount << 2) - 4;
1163 }
1164
1165 if (direction & LSM_B) {
1166 address += offset;
1167 }
1168
1169 uint32_t addressMisalign = address & 0x3;
1170 address &= 0xFFFFFFFC;
1171
1172 switch (address >> BASE_OFFSET) {
1173 case REGION_WORKING_RAM:
1174 STM_LOOP(STORE_WORKING_RAM);
1175 break;
1176 case REGION_WORKING_IRAM:
1177 STM_LOOP(STORE_WORKING_IRAM);
1178 break;
1179 case REGION_IO:
1180 STM_LOOP(STORE_IO);
1181 break;
1182 case REGION_PALETTE_RAM:
1183 STM_LOOP(STORE_PALETTE_RAM);
1184 break;
1185 case REGION_VRAM:
1186 STM_LOOP(STORE_VRAM);
1187 break;
1188 case REGION_OAM:
1189 STM_LOOP(STORE_OAM);
1190 break;
1191 case REGION_CART0:
1192 case REGION_CART0_EX:
1193 case REGION_CART1:
1194 case REGION_CART1_EX:
1195 case REGION_CART2:
1196 case REGION_CART2_EX:
1197 STM_LOOP(STORE_CART);
1198 break;
1199 case REGION_CART_SRAM:
1200 case REGION_CART_SRAM_MIRROR:
1201 STM_LOOP(STORE_SRAM);
1202 break;
1203 default:
1204 STM_LOOP(STORE_BAD);
1205 break;
1206 }
1207
1208 if (cycleCounter) {
1209 *cycleCounter += wait;
1210 }
1211
1212 if (direction & LSM_B) {
1213 address -= offset;
1214 }
1215
1216 if (direction & LSM_D) {
1217 address -= (popcount << 2) + 4;
1218 }
1219
1220 return address | addressMisalign;
1221}
1222
1223void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1224 struct GBAMemory* memory = &gba->memory;
1225 struct ARMCore* cpu = gba->cpu;
1226 int sram = parameters & 0x0003;
1227 int ws0 = (parameters & 0x000C) >> 2;
1228 int ws0seq = (parameters & 0x0010) >> 4;
1229 int ws1 = (parameters & 0x0060) >> 5;
1230 int ws1seq = (parameters & 0x0080) >> 7;
1231 int ws2 = (parameters & 0x0300) >> 8;
1232 int ws2seq = (parameters & 0x0400) >> 10;
1233 int prefetch = parameters & 0x4000;
1234
1235 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1236 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1237 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1238 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1239
1240 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1241 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1242 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1243
1244 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1245 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1246 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1247
1248 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1249 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1250 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1251
1252 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1253 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1254 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1255
1256 if (!prefetch) {
1257 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1258 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1259 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1260
1261 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1262 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1263 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1264
1265 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1266 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1267 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1268
1269 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1270 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1271 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1272 } else {
1273 // Assume it stalls one cycle to pull a value from the prefetch
1274 // This needs more research to tell if it's accurate or not
1275 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 1;
1276 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 1;
1277 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 1;
1278
1279 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 2;
1280 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 2;
1281 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 2;
1282
1283 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 1;
1284 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 1;
1285 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 1;
1286
1287 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 2;
1288 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 2;
1289 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 2;
1290 }
1291
1292 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1293 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1294
1295 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1296 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1297
1298 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1299 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1300}
1301
1302void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1303 struct GBAMemory* memory = &gba->memory;
1304 memory->dma[dma].source = address & 0x0FFFFFFE;
1305}
1306
1307void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1308 struct GBAMemory* memory = &gba->memory;
1309 memory->dma[dma].dest = address & 0x0FFFFFFE;
1310}
1311
1312void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1313 struct GBAMemory* memory = &gba->memory;
1314 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1315}
1316
1317uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1318 struct GBAMemory* memory = &gba->memory;
1319 struct GBADMA* currentDma = &memory->dma[dma];
1320 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1321 currentDma->reg = control;
1322
1323 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1324 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1325 }
1326
1327 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1328 currentDma->nextSource = currentDma->source;
1329 currentDma->nextDest = currentDma->dest;
1330 currentDma->nextCount = currentDma->count;
1331 GBAMemoryScheduleDMA(gba, dma, currentDma);
1332 }
1333 // If the DMA has already occurred, this value might have changed since the function started
1334 return currentDma->reg;
1335};
1336
1337void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1338 struct ARMCore* cpu = gba->cpu;
1339 switch (GBADMARegisterGetTiming(info->reg)) {
1340 case DMA_TIMING_NOW:
1341 info->nextEvent = cpu->cycles;
1342 GBAMemoryUpdateDMAs(gba, 0);
1343 break;
1344 case DMA_TIMING_HBLANK:
1345 // Handled implicitly
1346 info->nextEvent = INT_MAX;
1347 break;
1348 case DMA_TIMING_VBLANK:
1349 // Handled implicitly
1350 info->nextEvent = INT_MAX;
1351 break;
1352 case DMA_TIMING_CUSTOM:
1353 info->nextEvent = INT_MAX;
1354 switch (number) {
1355 case 0:
1356 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1357 break;
1358 case 1:
1359 case 2:
1360 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1361 break;
1362 case 3:
1363 // GBAVideoScheduleVCaptureDma(dma, info);
1364 break;
1365 }
1366 }
1367}
1368
1369void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1370 struct GBAMemory* memory = &gba->memory;
1371 struct GBADMA* dma;
1372 int i;
1373 for (i = 0; i < 4; ++i) {
1374 dma = &memory->dma[i];
1375 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1376 dma->nextEvent = cycles;
1377 }
1378 }
1379 GBAMemoryUpdateDMAs(gba, 0);
1380}
1381
1382void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1383 struct GBAMemory* memory = &gba->memory;
1384 struct GBADMA* dma;
1385 int i;
1386 for (i = 0; i < 4; ++i) {
1387 dma = &memory->dma[i];
1388 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1389 dma->nextEvent = cycles;
1390 }
1391 }
1392 GBAMemoryUpdateDMAs(gba, 0);
1393}
1394
1395int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1396 struct GBAMemory* memory = &gba->memory;
1397 if (memory->nextDMA == INT_MAX) {
1398 return INT_MAX;
1399 }
1400 memory->nextDMA -= cycles;
1401 memory->eventDiff += cycles;
1402 if (memory->nextDMA <= 0) {
1403 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1404 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1405 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1406 memory->eventDiff = 0;
1407 }
1408 return memory->nextDMA;
1409}
1410
1411void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1412 int i;
1413 struct GBAMemory* memory = &gba->memory;
1414 struct ARMCore* cpu = gba->cpu;
1415 memory->activeDMA = -1;
1416 memory->nextDMA = INT_MAX;
1417 for (i = 3; i >= 0; --i) {
1418 struct GBADMA* dma = &memory->dma[i];
1419 if (dma->nextEvent != INT_MAX) {
1420 dma->nextEvent -= cycles;
1421 if (GBADMARegisterIsEnable(dma->reg)) {
1422 memory->activeDMA = i;
1423 memory->nextDMA = dma->nextEvent;
1424 }
1425 }
1426 }
1427 if (memory->nextDMA < cpu->nextEvent) {
1428 cpu->nextEvent = memory->nextDMA;
1429 }
1430}
1431
1432void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1433 struct GBAMemory* memory = &gba->memory;
1434 struct ARMCore* cpu = gba->cpu;
1435 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1436 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1437 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1438 int32_t wordsRemaining = info->nextCount;
1439 uint32_t source = info->nextSource;
1440 uint32_t dest = info->nextDest;
1441 uint32_t sourceRegion = source >> BASE_OFFSET;
1442 uint32_t destRegion = dest >> BASE_OFFSET;
1443 int32_t cycles = 2;
1444
1445 if (source == info->source) {
1446 // TODO: support 4 cycles for ROM access
1447 cycles += 2;
1448 if (width == 4) {
1449 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1450 source &= 0xFFFFFFFC;
1451 dest &= 0xFFFFFFFC;
1452 } else {
1453 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1454 }
1455 } else {
1456 if (width == 4) {
1457 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1458 } else {
1459 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1460 }
1461 }
1462
1463 gba->performingDMA = true;
1464 int32_t word;
1465 if (width == 4) {
1466 word = cpu->memory.load32(cpu, source, 0);
1467 gba->bus = word;
1468 cpu->memory.store32(cpu, dest, word, 0);
1469 source += sourceOffset;
1470 dest += destOffset;
1471 --wordsRemaining;
1472 } else {
1473 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1474 word = GBASavedataReadEEPROM(&memory->savedata);
1475 gba->bus = word | (word << 16);
1476 cpu->memory.store16(cpu, dest, word, 0);
1477 source += sourceOffset;
1478 dest += destOffset;
1479 --wordsRemaining;
1480 } else if (destRegion == REGION_CART2_EX) {
1481 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1482 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1483 GBASavedataInitEEPROM(&memory->savedata);
1484 }
1485 word = cpu->memory.load16(cpu, source, 0);
1486 gba->bus = word | (word << 16);
1487 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1488 source += sourceOffset;
1489 dest += destOffset;
1490 --wordsRemaining;
1491 } else {
1492 word = cpu->memory.load16(cpu, source, 0);
1493 gba->bus = word | (word << 16);
1494 cpu->memory.store16(cpu, dest, word, 0);
1495 source += sourceOffset;
1496 dest += destOffset;
1497 --wordsRemaining;
1498 }
1499 }
1500 gba->performingDMA = false;
1501
1502 if (!wordsRemaining) {
1503 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1504 info->reg = GBADMARegisterClearEnable(info->reg);
1505 info->nextEvent = INT_MAX;
1506
1507 // Clear the enable bit in memory
1508 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1509 } else {
1510 info->nextCount = info->count;
1511 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1512 info->nextDest = info->dest;
1513 }
1514 GBAMemoryScheduleDMA(gba, number, info);
1515 }
1516 if (GBADMARegisterIsDoIRQ(info->reg)) {
1517 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1518 }
1519 } else {
1520 info->nextDest = dest;
1521 info->nextCount = wordsRemaining;
1522 }
1523 info->nextSource = source;
1524
1525 if (info->nextEvent != INT_MAX) {
1526 info->nextEvent += cycles;
1527 }
1528 cpu->cycles += cycles;
1529}
1530
1531void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1532 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1533 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1534}
1535
1536void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1537 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1538 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1539}
1540
1541uint32_t _popcount32(unsigned bits) {
1542 bits = bits - ((bits >> 1) & 0x55555555);
1543 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1544 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1545}
1546
1547void _pristineCow(struct GBA* gba) {
1548 if (gba->memory.rom != gba->pristineRom) {
1549 return;
1550 }
1551 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1552 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1553 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1554}