1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#include "ds.h"
  7
  8#include "arm/decoder.h"
  9#include "arm/debugger/debugger.h"
 10#include "arm/isa-inlines.h"
 11
 12#include "util/crc32.h"
 13#include "util/memory.h"
 14#include "util/math.h"
 15#include "util/patch.h"
 16#include "util/vfs.h"
 17
 18mLOG_DEFINE_CATEGORY(DS, "DS");
 19
 20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
 21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
 22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
 23
 24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
 25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
 26
 27enum {
 28	DS7_SP_BASE = 0x380FD80,
 29	DS7_SP_BASE_IRQ = 0x380FF80,
 30	DS7_SP_BASE_SVC = 0x380FFC0,
 31
 32	DS9_SP_BASE = 0x3002F7C,
 33	DS9_SP_BASE_IRQ = 0x3003F80,
 34	DS9_SP_BASE_SVC = 0x3003FC0,
 35};
 36
 37static void DSInit(void* cpu, struct mCPUComponent* component);
 38
 39static void DS7Reset(struct ARMCore* cpu);
 40static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
 41
 42static void DS9Reset(struct ARMCore* cpu);
 43static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
 44
 45static void DSProcessEvents(struct ARMCore* cpu);
 46static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
 47static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
 48static void DSBreakpoint(struct ARMCore* cpu, int immediate);
 49
 50void DSCreate(struct DS* ds) {
 51	ds->d.id = DS_COMPONENT_MAGIC;
 52	ds->d.init = DSInit;
 53	ds->d.deinit = NULL;
 54	ds->arm7 = NULL;
 55	ds->arm9 = NULL;
 56}
 57
 58static void DSInit(void* cpu, struct mCPUComponent* component) {
 59	struct DS* ds = (struct DS*) component;
 60	struct ARMCore* core = cpu;
 61	if (!ds->arm7) {
 62		// The ARM7 must get initialized first
 63		ds->arm7 = core;
 64		ds->debugger = 0;
 65		ds->sync = 0;
 66		return;
 67	}
 68	ds->arm9 = cpu;
 69
 70	DS7InterruptHandlerInit(&ds->arm7->irqh);
 71	DS9InterruptHandlerInit(&ds->arm9->irqh);
 72
 73	ds->video.p = ds;
 74
 75	ds->springIRQ7 = 0;
 76	ds->springIRQ9 = 0;
 77	ds->keySource = NULL;
 78	ds->rtcSource = NULL;
 79	ds->rumble = NULL;
 80
 81	ds->romVf = NULL;
 82
 83	ds->keyCallback = NULL;
 84}
 85
 86void DSUnloadROM(struct DS* ds) {
 87	if (ds->romVf) {
 88		ds->romVf->close(ds->romVf);
 89		ds->romVf = NULL;
 90	}
 91}
 92
 93void DSDestroy(struct DS* ds) {
 94	DSUnloadROM(ds);
 95}
 96
 97void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
 98	irqh->reset = DS7Reset;
 99	irqh->processEvents = DSProcessEvents;
100	irqh->swi16 = NULL;
101	irqh->swi32 = NULL;
102	irqh->hitIllegal = DSIllegal;
103	irqh->readCPSR = NULL;
104	irqh->hitStub = DSHitStub;
105	irqh->bkpt16 = DSBreakpoint;
106	irqh->bkpt32 = DSBreakpoint;
107}
108
109void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
110	irqh->reset = DS9Reset;
111	irqh->processEvents = DSProcessEvents;
112	irqh->swi16 = NULL;
113	irqh->swi32 = NULL;
114	irqh->hitIllegal = DSIllegal;
115	irqh->readCPSR = NULL;
116	irqh->hitStub = DSHitStub;
117	irqh->bkpt16 = DSBreakpoint;
118	irqh->bkpt32 = DSBreakpoint;
119}
120
121void DS7Reset(struct ARMCore* cpu) {
122	ARMSetPrivilegeMode(cpu, MODE_IRQ);
123	cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
124	ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
125	cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
126	ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
127	cpu->gprs[ARM_SP] = DS7_SP_BASE;
128}
129
130void DS9Reset(struct ARMCore* cpu) {
131	ARMSetPrivilegeMode(cpu, MODE_IRQ);
132	cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
133	ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
134	cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
135	ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
136	cpu->gprs[ARM_SP] = DS9_SP_BASE;
137}
138
139static void DSProcessEvents(struct ARMCore* cpu) {
140	struct DS* ds = (struct DS*) cpu->master;
141
142	if (ds->springIRQ7) {
143		ARMRaiseIRQ(cpu);
144		ds->springIRQ7 = 0;
145	}
146
147	do {
148		int32_t cycles = cpu->nextEvent;
149		int32_t nextEvent = INT_MAX;
150#ifndef NDEBUG
151		if (cycles < 0) {
152			mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
153		}
154#endif
155
156		cpu->cycles -= cycles;
157		cpu->nextEvent = nextEvent;
158
159		if (cpu->halted) {
160			cpu->cycles = cpu->nextEvent;
161		}
162	} while (cpu->cycles >= cpu->nextEvent);
163}
164
165void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
166	ds->debugger = (struct ARMDebugger*) debugger->platform;
167	ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
168	ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
169	ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
170	ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
171}
172
173
174void DSDetachDebugger(struct DS* ds) {
175	ds->debugger = NULL;
176	ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
177	ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
178	ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
179	ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
180}
181
182bool DSLoadROM(struct DS* ds, struct VFile* vf) {
183	DSUnloadROM(ds);
184	ds->romVf = vf;
185	// TODO: Checksum?
186	// TODO: error check
187	return true;
188}
189
190bool DSIsROM(struct VFile* vf) {
191	if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
192		return false;
193	}
194	uint8_t signature[sizeof(DS_ROM_MAGIC)];
195	if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
196		return false;
197	}
198	return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
199}
200
201void DSGetGameCode(struct DS* ds, char* out) {
202	memset(out, 0, 8);
203	if (!ds->romVf) {
204		return;
205	}
206
207	struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
208	memcpy(out, "NTR-", 4);
209	memcpy(&out[4], &cart->id, 4);
210	ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
211}
212
213void DSGetGameTitle(struct DS* ds, char* out) {
214	memset(out, 0, 12);
215	if (!ds->romVf) {
216		return;
217	}
218
219	struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
220	memcpy(out, &cart->title, 4);
221	ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
222}
223
224void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
225	struct DS* ds = (struct DS*) cpu->master;
226	if (ds->debugger) {
227		struct mDebuggerEntryInfo info = {
228			.address = _ARMPCAddress(cpu),
229			.opcode = opcode
230		};
231		mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
232	}
233	// TODO: More sensible category?
234	mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
235}
236
237void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
238	struct DS* ds = (struct DS*) cpu->master;
239	if (ds->debugger) {
240		struct mDebuggerEntryInfo info = {
241			.address = _ARMPCAddress(cpu),
242			.opcode = opcode
243		};
244		mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
245	} else {
246		ARMRaiseUndefined(cpu);
247	}
248}
249
250void DSBreakpoint(struct ARMCore* cpu, int immediate) {
251	struct DS* ds = (struct DS*) cpu->master;
252	if (immediate >= CPU_COMPONENT_MAX) {
253		return;
254	}
255	switch (immediate) {
256	case CPU_COMPONENT_DEBUGGER:
257		if (ds->debugger) {
258			struct mDebuggerEntryInfo info = {
259				.address = _ARMPCAddress(cpu)
260			};
261			mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
262		}
263		break;
264	default:
265		break;
266	}
267}