src/arm/emitter-arm.h (view raw)
1#ifndef EMITTER_ARM_H
2#define EMITTER_ARM_H
3
4#include "emitter-inlines.h"
5
6#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
7 EMITTER ## NAME
8
9#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
10 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
11 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
12
13#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
14 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
15 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
16 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
17 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
18 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
19 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
20 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
21 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
22 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
23 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
24 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
25 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
26 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
27 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
28 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
29 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
30
31#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
32 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
33 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
34
35#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
36 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
37 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
38 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
39 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
40 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
41 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
42 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
43 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
44 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
45 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
46 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
47 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
48 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
49 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
50 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
51 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
52
53#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
54 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
55 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
56
57#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
58 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
59
60// TODO: Support coprocessors
61#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
62 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
63 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
64
65#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
66 DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
67
68#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
69 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
70
71#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
72 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
73 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
74 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
75 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
76 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
77 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
78 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
79 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
80 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
81 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
82 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
83 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
84 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
85 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
86 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
87 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
88 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
89 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
90 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
91 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
92 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
93 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
94 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
95 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
96 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
97 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
98 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
99 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
100 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
101 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
102 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
103 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
104 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
105 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
106 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
107 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
108 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
109 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
110 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
111 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
112 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
113 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
114 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
115 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
116 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
117 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
118 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
119 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
120 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
121 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
122 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
123 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
124 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
125 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
126 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
127 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
128 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
129 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
130 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
131 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
132 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
133 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
134 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
135 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
136 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
137 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
138 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
139 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
140 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
141 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
142 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
143 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
144 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
145 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
146 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
147 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
148 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
149 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
150 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
151 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
152 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
153 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
154 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
155 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
156 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
157 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
158 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
159 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
160 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
161 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
162 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
163 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
164 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
165 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
166 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
167 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
168 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
169 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
170 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
171 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
172 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
173 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
174 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
175 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
176 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
177 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
178 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
179 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
180 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
181 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
182 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
183 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
184 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
185 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
186 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
187 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
188 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
189 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
190 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
191 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
192 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
193 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
194 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
195 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
196 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
197 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
198 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
199 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
200 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
201 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
202 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
203 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
204 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
205 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
206 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
207 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
208 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
209 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
210 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
211 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
212 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
213 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
214 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
215 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
216 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
217 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
218 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
219 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
220 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
221 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
222 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
223 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
224 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
225 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
226 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
227 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
228 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
229 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
230 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
231 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
232 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
233 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
234 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
235 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
236 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
237 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
238 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
239 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
240 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
241 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
242 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
243 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
244 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
245 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
246 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
247 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
248 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
249 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
250 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
251 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
252 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
253 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
254 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
255 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
256 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
257 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
258 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
259 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
260 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
261 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
262 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
263 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
264 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
265 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
266 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
267 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
268 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
269 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
270 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
271 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
272 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
273 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
274 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
275 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
276 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
277 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
278 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
279 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
280 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
281 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
282 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
283 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
284 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
285 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
286 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
287 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
288 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
289 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
290 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
291 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
292 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
293 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
294 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
295 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
296 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
297 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
298 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
299 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
300 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
301 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
302 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
303 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
304 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
305 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
306 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
307 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
308 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
309 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
310 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
311 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
312 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
313 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
314 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
315 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
316 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
317 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
318 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
319 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
320 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
321 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
322 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
323 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
324 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
325 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
326 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
327 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
328 DECLARE_ARM_SWI_BLOCK(EMITTER)
329
330#endif