1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/internal/arm/arm.h>
 16#include <mgba/internal/ds/dma.h>
 17#include <mgba/internal/ds/io.h>
 18
 19enum DSMemoryRegion {
 20	DS7_REGION_BIOS = 0x0,
 21	DS9_REGION_ITCM = 0x0,
 22	DS9_REGION_ITCM_MIRROR = 0x1,
 23	DS_REGION_RAM = 0x2,
 24	DS_REGION_WORKING_RAM = 0x3,
 25	DS_REGION_IO = 0x4,
 26	DS9_REGION_PALETTE_RAM = 0x5,
 27	DS_REGION_VRAM = 0x6,
 28	DS9_REGION_OAM = 0x7,
 29	DS_REGION_SLOT2 = 0x8,
 30	DS_REGION_SLOT2_EX = 0x9,
 31	DS_REGION_SLOT2_SRAM = 0xA,
 32	DS9_REGION_BIOS = 0xFF,
 33};
 34
 35enum DSMemoryBase {
 36	DS7_BASE_BIOS = 0x00000000,
 37	DS9_BASE_ITCM = 0x00000000,
 38	DS_BASE_RAM = 0x02000000,
 39	DS9_BASE_DTCM = 0x027C0000,
 40	DS_BASE_WORKING_RAM = 0x03000000,
 41	DS7_BASE_WORKING_RAM = 0x03800000,
 42	DS_BASE_IO = 0x04000000,
 43	DS9_BASE_PALETTE_RAM = 0x05000000,
 44	DS_BASE_VRAM = 0x06000000,
 45	DS9_BASE_OAM = 0x07000000,
 46	DS_BASE_SLOT2 = 0x08000000,
 47	DS_BASE_SLOT2_EX = 0x09000000,
 48	DS9_BASE_BIOS = 0xFFFF0000,
 49};
 50
 51enum {
 52	DS9_SIZE_ITCM = 0x00008000,
 53	DS9_SIZE_DTCM = 0x00004000,
 54	DS7_SIZE_BIOS = 0x00004000,
 55	DS9_SIZE_BIOS = 0x00008000,
 56	DS_SIZE_RAM = 0x00400000,
 57	DS_SIZE_VRAM = 0x000A4000,
 58	DS_SIZE_WORKING_RAM = 0x00008000,
 59	DS7_SIZE_WORKING_RAM = 0x00010000,
 60	DS9_SIZE_PALETTE_RAM = 0x00000800,
 61	DS9_SIZE_OAM = 0x00000800,
 62	DS_SIZE_SLOT2 = 0x02000000,
 63	DS_SIZE_SLOT2_SRAM = 0x00010000,
 64};
 65
 66enum {
 67	DS_OFFSET_MASK = 0x00FFFFFF,
 68	DS_BASE_OFFSET = 24,
 69	DS_VRAM_OFFSET = 14
 70};
 71
 72mLOG_DECLARE_CATEGORY(DS_MEM);
 73
 74struct DSMemory {
 75	uint32_t* bios7;
 76	uint32_t* bios9;
 77	uint32_t* itcm;
 78	uint32_t* dtcm;
 79	uint32_t* ram;
 80	uint32_t* wram;
 81	uint32_t* wramBase7;
 82	uint32_t* wramBase9;
 83	uint32_t* wram7;
 84	uint32_t* rom;
 85	uint16_t io7[DS7_REG_MAX >> 1];
 86	uint16_t io9[DS9_REG_MAX >> 1];
 87
 88	uint16_t vramMirror[9][0x40];
 89	uint16_t vramMode[9][8];
 90	uint16_t* vramBank[9];
 91
 92	size_t romSize;
 93	size_t wramSize7;
 94	size_t wramSize9;
 95
 96	uint32_t dtcmBase;
 97	uint32_t dtcmSize;
 98	uint32_t itcmSize;
 99};
100
101struct DSCoreMemory {
102	uint16_t* io;
103	int activeRegion;
104
105	char waitstatesSeq32[256];
106	char waitstatesSeq16[256];
107	char waitstatesNonseq32[256];
108	char waitstatesNonseq16[256];
109	char waitstatesPrefetchSeq32[16];
110	char waitstatesPrefetchSeq16[16];
111	char waitstatesPrefetchNonseq32[16];
112	char waitstatesPrefetchNonseq16[16];
113
114	struct GBADMA dma[4];
115	struct mTimingEvent dmaEvent;
116	int activeDMA;
117};
118
119struct DS;
120void DSMemoryInit(struct DS* ds);
121void DSMemoryDeinit(struct DS* ds);
122
123void DSMemoryReset(struct DS* ds);
124
125uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
126uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
127uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
128
129void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
130void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
131void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
132
133uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
134                         int* cycleCounter);
135uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
136                          int* cycleCounter);
137
138uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
139uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
140uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
141
142void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
143void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
144void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
145
146uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
147                         int* cycleCounter);
148uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
149                          int* cycleCounter);
150
151void DSConfigureWRAM(struct DSMemory*, uint8_t config);
152
153#endif