src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77 ds->earlyExit = true;
78}
79
80static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
81 UNUSED(timing);
82 UNUSED(cyclesLate);
83 struct DS* ds = context;
84 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
85 int64_t numerator;
86 int64_t denominator;
87 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
88 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
89 bool max = false;
90 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
91 case 0:
92 numerator = (int64_t)(int32_t) numerator;
93 case 1:
94 case 3:
95 denominator = (int64_t)(int32_t) denominator;
96 break;
97 }
98 if (numerator == INT64_MIN) {
99 max = true;
100 }
101 if (!denominator) {
102 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
103 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
104 numerator >>= 63LL;
105 numerator = -numerator;
106 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
107 return;
108 }
109 if (denominator == -1LL && max) {
110 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
111 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
112 return;
113 }
114 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
115 int64_t result = numerator / denominator;
116 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
117 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
118 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
119}
120
121 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
122 UNUSED(timing);
123 UNUSED(cyclesLate);
124 struct DS* ds = context;
125 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
126 uint64_t param;
127 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
128 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
129 param &= 0xFFFFFFFFULL;
130 }
131
132 uint64_t result = 0;
133 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
134
135 // "bit" starts at the highest power of four <= the argument.
136 while (bit > param) {
137 bit >>= 2;
138 }
139
140 while (bit != 0) {
141 if (param >= param + bit) {
142 param -= param + bit;
143 param = (result >> 1) + bit;
144 } else {
145 param >>= 1;
146 }
147 bit >>= 2;
148 }
149 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
150}
151
152void DSCreate(struct DS* ds) {
153 ds->d.id = DS_COMPONENT_MAGIC;
154 ds->d.init = DSInit;
155 ds->d.deinit = NULL;
156 ds->ds7.p = ds;
157 ds->ds9.p = ds;
158 ds->ds7.cpu = NULL;
159 ds->ds9.cpu = NULL;
160 ds->ds7.ipc = &ds->ds9;
161 ds->ds9.ipc = &ds->ds7;
162}
163
164static void DSInit(void* cpu, struct mCPUComponent* component) {
165 struct DS* ds = (struct DS*) component;
166 struct ARMCore* core = cpu;
167 if (!ds->ds7.cpu) {
168 // The ARM7 must get initialized first
169 ds->ds7.cpu = core;
170 ds->debugger = 0;
171 ds->sync = 0;
172 return;
173 }
174 ds->ds9.cpu = cpu;
175 ds->activeCpu = NULL;
176
177 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
178
179 ds->slice.name = "DS CPU Time Slicing";
180 ds->slice.callback = _slice;
181 ds->slice.context = ds;
182 ds->slice.priority = UINT_MAX;
183
184 CircleBufferInit(&ds->ds7.fifo, 64);
185 CircleBufferInit(&ds->ds9.fifo, 64);
186
187 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
188 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
189 DSMemoryInit(ds);
190 DSDMAInit(ds);
191
192 DSVideoInit(&ds->video);
193 ds->video.p = ds;
194
195 ds->ds7.springIRQ = 0;
196 ds->ds9.springIRQ = 0;
197 DSTimerInit(ds);
198 ds->keySource = NULL;
199 ds->rtcSource = NULL;
200 ds->rumble = NULL;
201
202 ds->romVf = NULL;
203
204 ds->keyCallback = NULL;
205
206 ds->divEvent.name = "DS Hardware Divide";
207 ds->divEvent.callback = _divide;
208 ds->divEvent.context = ds;
209 ds->divEvent.priority = 0x50;
210
211 ds->sqrtEvent.name = "DS Hardware Sqrt";
212 ds->sqrtEvent.callback = _sqrt;
213 ds->sqrtEvent.context = ds;
214 ds->sqrtEvent.priority = 0x51;
215
216 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
217 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
218}
219
220void DSUnloadROM(struct DS* ds) {
221 if (ds->romVf) {
222 ds->romVf->close(ds->romVf);
223 ds->romVf = NULL;
224 }
225}
226
227void DSDestroy(struct DS* ds) {
228 CircleBufferDeinit(&ds->ds7.fifo);
229 CircleBufferDeinit(&ds->ds9.fifo);
230 DSUnloadROM(ds);
231 DSMemoryDeinit(ds);
232 mTimingDeinit(&ds->ds7.timing);
233 mTimingDeinit(&ds->ds9.timing);
234}
235
236void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
237 irqh->reset = DS7Reset;
238 irqh->processEvents = DS7ProcessEvents;
239 irqh->swi16 = DS7Swi16;
240 irqh->swi32 = DS7Swi32;
241 irqh->hitIllegal = DSIllegal;
242 irqh->readCPSR = DS7TestIRQ;
243 irqh->writeCP15 = NULL;
244 irqh->readCP15 = NULL;
245 irqh->hitStub = DSHitStub;
246 irqh->bkpt16 = DSBreakpoint;
247 irqh->bkpt32 = DSBreakpoint;
248}
249
250void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
251 irqh->reset = DS9Reset;
252 irqh->processEvents = DS9ProcessEvents;
253 irqh->swi16 = DS9Swi16;
254 irqh->swi32 = DS9Swi32;
255 irqh->hitIllegal = DSIllegal;
256 irqh->readCPSR = DS9TestIRQ;
257 irqh->writeCP15 = DS9WriteCP15;
258 irqh->readCP15 = DS9ReadCP15;
259 irqh->hitStub = DSHitStub;
260 irqh->bkpt16 = DSBreakpoint;
261 irqh->bkpt32 = DSBreakpoint;
262}
263
264void DS7Reset(struct ARMCore* cpu) {
265 ARMSetPrivilegeMode(cpu, MODE_IRQ);
266 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
267 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
268 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
269 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
270 cpu->gprs[ARM_SP] = DS7_SP_BASE;
271
272 struct DS* ds = (struct DS*) cpu->master;
273 mTimingClear(&ds->ds7.timing);
274 CircleBufferInit(&ds->ds7.fifo, 64);
275 DSMemoryReset(ds);
276 DSDMAReset(&ds->ds7);
277 DS7IOInit(ds);
278
279 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
280 if (header) {
281 // TODO: Error check
282 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
283 uint32_t base = header->arm7Base - DS_BASE_RAM;
284 uint32_t* basePointer = &ds->memory.ram[base >> 2];
285 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
286 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
287 }
288 cpu->gprs[12] = header->arm7Entry;
289 cpu->gprs[ARM_LR] = header->arm7Entry;
290 cpu->gprs[ARM_PC] = header->arm7Entry;
291 int currentCycles = 0;
292 ARM_WRITE_PC;
293
294 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
295 }
296}
297
298void DS9Reset(struct ARMCore* cpu) {
299 ARMSetPrivilegeMode(cpu, MODE_IRQ);
300 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
301 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
302 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
303 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
304 cpu->gprs[ARM_SP] = DS9_SP_BASE;
305
306 struct DS* ds = (struct DS*) cpu->master;
307 mTimingClear(&ds->ds9.timing);
308 CircleBufferInit(&ds->ds9.fifo, 64);
309 DSVideoReset(&ds->video);
310 DSDMAReset(&ds->ds9);
311 DS9IOInit(ds);
312
313 ds->activeCpu = cpu;
314 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
315 ds->cycleDrift = 0;
316 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
317
318 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
319 if (header) {
320 // TODO: Error check
321 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
322 uint32_t base = header->arm9Base - DS_BASE_RAM;
323 uint32_t* basePointer = &ds->memory.ram[base >> 2];
324 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
325 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
326 }
327 cpu->gprs[12] = header->arm9Entry;
328 cpu->gprs[ARM_LR] = header->arm9Entry;
329 cpu->gprs[ARM_PC] = header->arm9Entry;
330 int currentCycles = 0;
331 ARM_WRITE_PC;
332
333 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
334 }
335}
336
337static void DS7ProcessEvents(struct ARMCore* cpu) {
338 struct DS* ds = (struct DS*) cpu->master;
339 DSProcessEvents(&ds->ds7);
340}
341
342static void DS9ProcessEvents(struct ARMCore* cpu) {
343 struct DS* ds = (struct DS*) cpu->master;
344 DSProcessEvents(&ds->ds9);
345}
346
347static void DSProcessEvents(struct DSCommon* dscore) {
348 struct ARMCore* cpu = dscore->cpu;
349 struct DS* ds = dscore->p;
350 if (dscore->springIRQ && !cpu->cpsr.i) {
351 ARMRaiseIRQ(cpu);
352 dscore->springIRQ = 0;
353 }
354
355 int32_t nextEvent = cpu->nextEvent;
356 while (cpu->cycles >= nextEvent) {
357 int32_t cycles = cpu->cycles;
358
359 cpu->cycles = 0;
360 cpu->nextEvent = INT_MAX;
361
362#ifndef NDEBUG
363 if (cycles < 0) {
364 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
365 }
366#endif
367 nextEvent = cycles;
368 do {
369 nextEvent = mTimingTick(&dscore->timing, nextEvent);
370 } while (ds->cpuBlocked);
371
372 cpu->nextEvent = nextEvent;
373
374 if (ds->earlyExit) {
375 ds->earlyExit = false;
376 break;
377 }
378 if (cpu->halted) {
379 cpu->cycles = nextEvent;
380 }
381#ifndef NDEBUG
382 else if (nextEvent < 0) {
383 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
384 }
385#endif
386 }
387}
388
389void DSRunLoop(struct DS* ds) {
390 if (ds->activeCpu == ds->ds9.cpu) {
391 ARMv5RunLoop(ds->ds9.cpu);
392 } else {
393 ARMv4RunLoop(ds->ds7.cpu);
394 }
395}
396
397void DS7Step(struct DS* ds) {
398 while (ds->activeCpu == ds->ds9.cpu) {
399 ARMv5RunLoop(ds->ds9.cpu);
400 }
401 ARMv4Run(ds->ds7.cpu);
402}
403
404void DS9Step(struct DS* ds) {
405 while (ds->activeCpu == ds->ds7.cpu) {
406 ARMv4RunLoop(ds->ds7.cpu);
407 }
408 ARMv5Run(ds->ds9.cpu);
409}
410
411void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
412 ds->debugger = (struct ARMDebugger*) debugger->platform;
413 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
414 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
415 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
416 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
417}
418
419void DSDetachDebugger(struct DS* ds) {
420 ds->debugger = NULL;
421 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
422 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
423 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
424 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
425}
426
427bool DSLoadROM(struct DS* ds, struct VFile* vf) {
428 DSUnloadROM(ds);
429 ds->romVf = vf;
430 // TODO: error check
431 return true;
432}
433
434bool DSIsROM(struct VFile* vf) {
435 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
436 return false;
437 }
438 uint8_t signature[sizeof(DS_ROM_MAGIC)];
439 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
440 return false;
441 }
442 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
443}
444
445bool DSIsBIOS7(struct VFile* vf) {
446 size_t size = vf->size(vf);
447 void* data = NULL;
448 uint32_t crc;
449 if (size == DS7_SIZE_BIOS) {
450 data = vf->map(vf, size, MAP_READ);
451 }
452 if (!data) {
453 return false;
454 }
455 crc = doCrc32(data, size);
456 vf->unmap(vf, data, size);
457 return crc == DS7_BIOS_CHECKSUM;
458}
459
460bool DSIsBIOS9(struct VFile* vf) {
461 size_t size = vf->size(vf);
462 void* data = NULL;
463 uint32_t crc;
464 if (size == DS9_SIZE_BIOS) {
465 data = vf->map(vf, 0x1000, MAP_READ);
466 } else if (size == 0x1000) {
467 data = vf->map(vf, 0x1000, MAP_READ);
468 }
469 if (!data) {
470 return false;
471 }
472 crc = doCrc32(data, 0x1000);
473 vf->unmap(vf, data, 0x1000);
474 return crc == DS9_BIOS_CHECKSUM;
475}
476
477bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
478 size_t size = vf->size(vf);
479 void* data = NULL;
480 uint32_t crc;
481 if (size == DS7_SIZE_BIOS) {
482 data = vf->map(vf, size, MAP_READ);
483 } else if (size == 0x1000) {
484 data = calloc(DS9_SIZE_BIOS, 1);
485 vf->read(vf, data, size);
486 } else if (size == DS9_SIZE_BIOS) {
487 data = vf->map(vf, size, MAP_READ);
488 }
489 if (!data) {
490 return false;
491 }
492 crc = doCrc32(data, size);
493 if (crc == DS7_BIOS_CHECKSUM) {
494 ds->bios7Vf = vf;
495 ds->memory.bios7 = data;
496 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
497 } else if (crc == DS9_BIOS_CHECKSUM) {
498 ds->bios9Vf = vf;
499 ds->memory.bios9 = data;
500 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
501 } else {
502 mLOG(DS, WARN, "BIOS checksum incorrect");
503 vf->unmap(vf, data, size);
504 return false;
505 }
506 return true;
507}
508
509void DSGetGameCode(struct DS* ds, char* out) {
510 memset(out, 0, 8);
511 if (!ds->romVf) {
512 return;
513 }
514
515 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
516 // TODO: TWL-?
517 memcpy(out, "NTR-", 4);
518 memcpy(&out[4], &cart->id, 4);
519 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
520}
521
522void DSGetGameTitle(struct DS* ds, char* out) {
523 memset(out, 0, 12);
524 if (!ds->romVf) {
525 return;
526 }
527
528 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
529 memcpy(out, &cart->title, 12);
530 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
531}
532
533void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
534 struct DS* ds = (struct DS*) cpu->master;
535 if (ds->debugger) {
536 struct mDebuggerEntryInfo info = {
537 .address = _ARMPCAddress(cpu),
538 .opcode = opcode
539 };
540 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
541 }
542 // TODO: More sensible category?
543 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
544}
545
546void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
547 struct DS* ds = (struct DS*) cpu->master;
548 if (ds->debugger) {
549 struct mDebuggerEntryInfo info = {
550 .address = _ARMPCAddress(cpu),
551 .opcode = opcode
552 };
553 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
554 } else {
555 ARMRaiseUndefined(cpu);
556 }
557}
558
559void DSBreakpoint(struct ARMCore* cpu, int immediate) {
560 struct DS* ds = (struct DS*) cpu->master;
561 if (immediate >= CPU_COMPONENT_MAX) {
562 return;
563 }
564 switch (immediate) {
565 case CPU_COMPONENT_DEBUGGER:
566 if (ds->debugger) {
567 struct mDebuggerEntryInfo info = {
568 .address = _ARMPCAddress(cpu)
569 };
570 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
571 }
572 break;
573 default:
574 break;
575 }
576}
577
578void DS7TestIRQ(struct ARMCore* cpu) {
579 struct DS* ds = (struct DS*) cpu->master;
580 if (!ds->memory.io7[DS_REG_IME >> 1]) {
581 return;
582 }
583 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
584 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
585 if (test) {
586 ds->ds7.springIRQ = test;
587 cpu->nextEvent = cpu->cycles;
588 }
589}
590
591void DS9TestIRQ(struct ARMCore* cpu) {
592 struct DS* ds = (struct DS*) cpu->master;
593 if (!ds->memory.io9[DS_REG_IME >> 1]) {
594 return;
595 }
596 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
597 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
598 if (test) {
599 ds->ds9.springIRQ = test;
600 cpu->nextEvent = cpu->cycles;
601 }
602}
603
604static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
605 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
606}
607
608static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
609 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
610 switch (opcode2) {
611 case 0:
612 cpu->cp15.r2.d = value;
613 break;
614 case 1:
615 cpu->cp15.r2.i = value;
616 break;
617 default:
618 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
619 break;
620 }
621}
622
623static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
624 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
625 switch (opcode2) {
626 case 0:
627 cpu->cp15.r3.d = value;
628 break;
629 default:
630 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
631 break;
632 }
633}
634
635static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
636 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
637}
638
639static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
640 cpu->cp15.r6.region[crm] = value;
641 uint32_t base = ARMProtectionGetBase(value) << 12;
642 uint32_t size = 2 << ARMProtectionGetSize(value);
643 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
644}
645
646static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
647 switch (crm) {
648 case 0:
649 if (opcode2 == 4) {
650 ARMHalt(cpu);
651 return;
652 }
653 break;
654 }
655 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
656}
657
658static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
659 uint32_t base = ARMTCMControlGetBase(value) << 12;
660 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
661 struct DS* ds = (struct DS*) cpu->master;
662 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
663 switch (opcode2) {
664 case 0:
665 cpu->cp15.r9.d = value;
666 ds->memory.dtcmBase = base;
667 ds->memory.dtcmSize = size;
668 break;
669 case 1:
670 cpu->cp15.r9.i = value;
671 ds->memory.itcmSize = size;
672 break;
673 default:
674 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
675 break;
676 }
677}
678
679void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
680 switch (crn) {
681 default:
682 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
683 break;
684 case 0:
685 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
686 ARMRaiseUndefined(cpu);
687 break;
688 case 1:
689 _writeSysControl(cpu, crm, opcode2, value);
690 break;
691 case 2:
692 _writeCacheControl(cpu, crm, opcode2, value);
693 break;
694 case 3:
695 _writeWriteBufferControl(cpu, crm, opcode2, value);
696 break;
697 case 5:
698 _writeAccessControl(cpu, crm, opcode2, value);
699 break;
700 case 6:
701 _writeRegionConfiguration(cpu, crm, opcode2, value);
702 break;
703 case 7:
704 _writeCache(cpu, crm, opcode2, value);
705 break;
706 case 9:
707 _writeTCMControl(cpu, crm, opcode2, value);
708 break;
709 }
710}
711
712static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
713 switch (opcode2) {
714 case 0:
715 return cpu->cp15.r9.d;
716 case 1:
717 return cpu->cp15.r9.i;
718 default:
719 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
720 return 0;
721 }
722}
723
724uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
725 switch (crn) {
726 default:
727 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
728 return 0;
729 case 9:
730 return _readTCMControl(cpu, crm, opcode2);
731 }
732}
733
734void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
735 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
736 ARMRaiseIRQ(cpu);
737 }
738}
739void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
740 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
741 ARMRaiseIRQ(cpu);
742 }
743}
744
745void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
746 if (irq < 16) {
747 io[DS_REG_IF_LO >> 1] |= 1 << irq;
748 } else {
749 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
750 }
751
752 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
753 cpu->halted = 0;
754 if (io[DS_REG_IME >> 1]) {
755 ARMRaiseIRQ(cpu);
756 }
757 }
758}
759
760void DSFrameStarted(struct DS* ds) {
761 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
762 if (callbacks && callbacks->videoFrameStarted) {
763 callbacks->videoFrameStarted(callbacks->context);
764 }
765}
766
767void DSFrameEnded(struct DS* ds) {
768 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
769 if (callbacks && callbacks->videoFrameEnded) {
770 callbacks->videoFrameEnded(callbacks->context);
771 }
772}